28. Oktober 2019

Open Seminar - Eingebettete Systeme, M.Sc. cand. Purnima Dutt

STT-MRAM memories in embedded system design and optimization (Final Master Thesis Presentation)

28. Oktober 2019 11:45 Uhr bis 12:30 Uhr

11:45 - 12:30, FZI 1.021,

Institut für Technische Informatik


Complexity in embedded system design is steadily increasing. This is due to miniaturization of logic, on the one hand, and the rising demand for computational power at minimal power budgets, on the other hand. To cope with these opposing design goals and related challenges, automated system design and optimization methods are of essential importance and subject to intensive research.
In this context, an ongoing research project at the Chair of Embedded Systems investigates automated design concepts and optimization methods for power-efficient memory subsystems. Main goal is the minimization of total memory subsystem energy comsumption, while respecting certain constraints in terms of time and power. Due to the predominant use of SRAM and partially DRAM memory in embedded systems, existing optimization methods have been developed with focus on these memory technologies.

With Spin Transfer Torque Magnetic Random Access Memory (STT-RAM), lately a new type of memory technology is on the rise. Following the promises of the nanomagnetic research community, this technology is providing a solution to the main drawbacks of SRAM (volatility, large cell size, leakage) and DRAM (volatility, refresh current). Besides different critical parameters related to production, e.g. thermal stability or retention time, especially the write operation appears to be a promising target for design-time optimization at system level. Recent publications show further that a variation of the memory cell’s write current allows for the realization of different trade-off working points in terms of write energy and write latency.

This master thesis deals with optimization concepts for embedded systems and their memory subsystem that allow to exploit this write energy/latency trade-off characteristic in STT-RAM memories.

Seminarraum Eingebettete Systeme
Seminarraum Eingebettete Systeme
[Bild: ITI]
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