Main Page

From Signs - VHDL Hardware Developement

Signs - VHDL Hardware Developement


Signs Eclipse plugin running a netlist simulation
Enlarge
Signs Eclipse plugin running a netlist simulation


Table of contents
1 News
2 About
3 Project Objectives and Goals
4 Documentation
5 Copyright and Authors
6 Download
7 Contact
[edit]

News

February 13th 2007: In an effort to make Signs developement more transparent and in the hope to attract outside developers, the Signs source code has been uploaded to the subversion repository (https://sourceforge.net/svn/?group_id=64498) provided by SourceForge. From this point on, developement will take place there.

January 10th 2007: After months of bug-fixing and regression-testing a new signs release is available: Signs 0.6.3 (http://www.iti.uni-stuttgart.de/~bartscgr/signs/download). While the release focus is clearly on bugfixes, there are some feature improvements as well such as enhanced test bench support and improved netlist and simulator views. The VHDL compiler has support for subprograms now and elaboration of big designs is much faster because of improved context handling. Internally the intermediate representation layer was cleaned up, so intermediate objects form a proper tree now.

June 23rd 2006: A new signs release is available: Signs 0.6.2 (http://www.iti.uni-stuttgart.de/~bartscgr/signs/download). Besides many bugfixes this release features an improved Eclipse plugin which includes a new Signs console, autobuilder improvements and outline view navigation. The VHDL compiler has support for attribute elaboration, VHDL87 style file declarations and reports precise source locations for netlist annotations and error messages. New features in this release include an experimental Berkeley SIS interface, BLIF netlist output, adder and comparator generation and better support for testbenches.

May 05th 2006: The last release has gotten quite a lot of attention out there and we received quite a few very good bug reports. Most of the bugs reported have been fixed, so it is time for a new release: Signs 0.6.1 (http://www.iti.uni-stuttgart.de/~bartscgr/signs/download). From the change log: NAND/NOR tree generation for ISCAS netlists has been fixed, (limited) support for selected signal assignment elaboration has been added, CLA (adder) generation has been fixed, the netlist viewer has gotten additional tool bar buttons to access dump and netlist processing functions from the Eclipse plugin, mouse signal selection has been fixed and finally our ant build script is no longer missing from the source distribution.

Apr 28th 2006: Finally! Signs V0.6.0 has been released (http://www.iti.uni-stuttgart.de/~bartscgr/signs/download). This includes a new JavaCC based VHDL parser supporting a much bigger VHDL Subset than before, the GUI has been removed and instead a Signs Eclipse plugin is offered for design entry and exploration. Furthermore Signs can dump out (and very quickly read back in) intermediate library files and netlists. For computer-aided testing, the ATPG and Faultsim modules have been vastly improved.

Dec 08th 2005: A new beta release is ready for download: Signs 0.5.7 features lots of ATPG/Faultsim bugfixes plus a much improved netlist viewer which handles busses correctly now. Christian Zoellin has contributed lots of performance improvements for handling large netlists to this release.

Aug 03rd 2005: The upcoming Signs V0.6.0 release will feature a new JavaCC generated VHDL parser which will support a much larger subset of the VHDL 93 language than the 0.5.0 one. You can find preview releases named 0.5.x in the beta directory (http://www.iti.uni-stuttgart.de/~bartscgr/signs/download/beta).

Also available for download is a Presentation on VHDL Synthesis (http://www.iti.uni-stuttgart.de/~bartscgr/signs/download/documentation/vhdl_synth.sxi) held by Guenter Bartsch at ITI Open Seminar on Aug 01st 2005. Contains a lot of information on the netlist data structure and on the VHDL synthesis algorithms in Signs.

Jul 13th 2005: Signs V0.5.0 released (http://www.iti.uni-stuttgart.de/~bartscgr/signs/download). Changes include: ATPG and FaultSim functions officially added, JavaScript scripting, many bugfixes, BLIF output (incomplete), new function to flatten hierarchical netlists.

Jul 4th 2005: Signs V0.4.2 released (http://www.iti.uni-stuttgart.de/~bartscgr/signs/download). Changes: Many bugfixes, poster print function added to netlist viewer.

Jul 3rd 2005: Signs V0.4.1 released (http://www.iti.uni-stuttgart.de/~bartscgr/signs/download)

[edit]

About

Signs is a development environment for hardware designs in VHDL and other hardware description languages. The tackled tasks are compilation, synthesis, simulation and testing of designs. Due to the integration of these main areas it provides the ability to debug designs in an all-embracing manner by switching between source code, netlist and simulation.

Signs is free software and a protectionist of the open source spirit. Thereby it is especially suited as framework for research and teaching as it eases the development of new algorithms and hardware description languages.

Signs comes in two flavours: A command-line only version useful for processing and analyzing large netlists and as an Eclipse (http://www.eclipse.org) plugin for hardware design and simulation. Here, Signs benefits from the stable infrastructure like builders, editors and viewers from the eclipse framework.

Main Features:

Signs dynamic netlist viewer
Enlarge
Signs dynamic netlist viewer
  • Supported file formats for design input and output:
    • Aims to be VHDL93 (http://tech-www.informatik.uni-hamburg.de/vhdl/tools/grammar/vhdl93-bnf.html) compliant, at the moment a VHDL Subset is supported
    • ISCAS benchmark format
    • Verilog (limited)
    • EDIF (very limited)
  • Gate level true value simulators: event-based (any circuit), bit-parallel (combinational circuits only)
  • Computer-aided testing:
    • Fault simulators: PPSFP, simple single faultsim
    • Input and output of pattern lists in WGL (Waveform Generation Language) format
    • ATPG for combinational circuits: Implication-Graph based, PODEM
  • Interactive Rhino: JavaScript for Java (http://www.mozilla.org/rhino/) interpreter, powerful command-line options
  • Eclipse plugin:
    • Integrated design environment
    • Source code editors for supported file formats with syntax highlighting
    • Netlist Viewer with source-code back-annotation, signal value display, dynamic mode (for design exploration)
    • Tree views of whole project
    • Integrated build system and compilers
    • Simulator View
  • Written in Java (http://java.sun.com), therefore platform-independent

Although because of the platform-independant nature of both Java and Eclipse Signs should run on all platforms supported by these, because of limited resources the only platform Signs officially supports is GNU/Linux using the GTK port of Eclipse/SWT. The command-line version of Signs is written in 100% pure Java.

Big thanks to the Eclipse Project (http://www.eclipse.org) for their excellent work on the best Java IDE out there!

[edit]

Project Objectives and Goals

The main objective of Signs is to provide free open source software in the electronic design automation field. By doing so Signs can be seen as a door opener for education and teaching as the used algorithms are open to the public and not black boxed like in the tools of huge companies. Due to this openness it is easy for interested people to learn what's happening inside of modern tools and to be used as a starting point for future approaches and improvements. Another goal is to bring assisted coding known from java coding tools to the design-entry. At long sight Signs wants to become a widespread open source eda tool that integrates all major parts of the design flow into a combined framework that assists the user during his tasks and helps researches to explore new ideas.

[edit]

Documentation

[edit]

Copyright and Authors

Signs is free software distributed under a BSD-style License except for those parts which are imported from other projects which may have different license terms and restrictions:

Authors (main contributors only):

  • Guenter Bartsch (project leader, parsing, intermediate layer, netlist viewer, true value simulator, fault simulator, eclipse plugin)
  • Stefan Holst (regression testing, gui, simulation)
  • Michael Imhof, Michael Kochte (automatic test pattern generation, fault simulation, distributed computing support / rmi)
  • Christian Zoellin (performance optimization, IBM VIM format support, test)
  • Alejandro Cook (vhdl support improvements and bugfixes)
  • Ge Gao (eclipse plugin prototype)

Signs ist developed in part at the Institut fuer Technische Informatik (http://www.iti.uni-stuttgart.de) in Stuttgart, Germany.

[edit]

Download

Signs Releases (http://sourceforge.net/project/showfiles.php?group_id=64498)

Signs Nightly Builds and Regression Tests (http://www.iti.uni-stuttgart.de/~holstsn/signs/)

Subversion repository (https://sourceforge.net/svn/?group_id=64498)

[edit]

Contact

Signs mailing lists are hosted at sourceforge now: Signs mailing lists (https://sourceforge.net/mail/?group_id=64498)

Signs project site on Sourceforge (http://sourceforge.net/projects/signs)

Please note: Bug reports must at least contain the following information in order to be considered:

  • Detailed description of the problem
  • Instructions on how to reproduce the problem
  • Operating system used
  • Java version used
  • Eclipse version used
  • Error messages and command line output, if any
Retrieved from "http://www.iti.uni-stuttgart.de/~bartscgr/signs/wiki/index.php/Main_Page"