Developer documentation

From Signs - VHDL Hardware Developement

Table of contents
1 Development Environment Setup
2 Signs Internals

2.1 Java Packages

3 Signs API Documentation
4 Roadmap
5 Further Information, Plans and Throughts
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Development Environment Setup

To get involved with the Signs development, you should first set up an eclipse project using the latest source package released (http://www.iti.uni-stuttgart.de/~bartscgr/signs/download) or the latest nightly snapshot (http://www.iti.uni-stuttgart.de/~holstsn/signs/snapshots).

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Signs Internals

Just a few hints to get you started on understanding Signs' internal workings:

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Java Packages

net.sf.signs.atpg Implication graph based test pattern generator
net.sf.signs.blif BLIF input/output
net.sf.signs.edif EDIF input/output
net.sf.signs.editors Eclipse plugin editors with syntax highlighting
net.sf.signs.faultsim PPSFP-based parallel faul simulator
net.sf.signs.gates Implementation of basic. built-in gates
net.sf.signs.intermediate Intermediate level representation of parsed input files
net.sf.signs.iscas ISCAS input/output
net.sf.signs.pcb Printed circuit board design support, Lee router
net.sf.signs.plugin Eclipse plugin related classes
net.sf.signs.rmi Support for distributed test pattern generation
net.sf.signs.cli Command line interface, JavaScript interpreter
net.sf.signs.sim Event/TimeWheel-driven true-value netlist simulator
net.sf.signs.test JUnit test cases
net.sf.signs.views Eclipse plugin views
net.sf.signs.vim VIM input/output
net.sf.signs.fsm FSM recognition/synthesis
net.sf.signs.xml Netlist input/output in signs XML format
net.sf.signs.optimization Logic optimization
net.sf.signs Core signs classes (netlist representation mainly)
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Signs API Documentation

API Reference generated by JavaDOC (http://www.iti.uni-stuttgart.de/~holstsn/signs/api/)

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Roadmap

This is just a rough overview of ideas and plans for further developement of Signs:

  • intermediate libs
    • store as directories on disc
  • autobuilder
    • dependencies
    • clean up intermediate libs
  • SIS
    • lib selection dialog
    • error checking (e.g. no netlist loaded, fail to export BLIF)
  • Netlist file format support
    • BLIF output error checking
    • BLIF parsing
    • EDIF support
  • VHDL support
    • for use statements
    • port signals with default values
    • functions
    • generics/generate
    • SRAM junit test case
    • Plasma test case
  • Simulator/Interpreter
    • improve testbench support (e.g. file access, array handling, function calls)
    • command line / scripting interface
  • Waveform viewer
    • improve zooming and scrolling
    • save and re-load traced signals and position
  • Netlist
    • consistency checks
    • implement unique, numeric gate, port and fault ids
  • Synthesis and optimization
    • implement standard two-level and multilevel logic optimizers
    • FSM recognition
    • sequential optimization: retiming, fsm state encoding, ...
    • technology mapping (for FPGAs, ASICs)
  • Verilog
    • support
  • Web front end
    • for educational purposes and promoting Signs, an AJAX/echo2 based frontend would be nice
  • PCB
    • fix lee-based auto-router
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Further Information, Plans and Throughts

  • Presentation on VHDL Synthesis (http://www.iti.uni-stuttgart.de/~bartscgr/signs/download/documentation/vhdl_synth.sxi) held by Guenter Bartsch at ITI Open Seminar on Aug 1st 2005. Contains a lot of information on the netlist data structure and on the VHDL synthesis algorithms in Signs.
  • Logic Optimization
  • FSM Synthesis
  • JavaBDD (http://javabdd.sourceforge.net/performance.html)
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