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This lecture covers advanced concepts in computer architecture. Beside classical concepts like processor design and manufacturing, performance evaluation and optimization, and computer arithmetic new trends are discussed like low power design. Low power design is essential in mobile computing and communication which is expected to be a dominating application of microprocessors in a few years.

Computation power is increasing by exploiting parallelism on all levels of computation. In this course we will discuss instruction level parallelism, thread level parallelism, multiprocessor systems and emerging many-core technologies found in current graphic accelerators.

The lecture provides a solid background for the courses:

• Design & Test of Systems-on-a-Chip
• Hardware Verification
• Self-Testable Systems
• Fault Tolerant Systems

Staff

• Dipl.-Inf Stefan Holst office: 3.164, Pfaffenwaldring 47
• Prof. Hans-Joachim Wunderlich office: 3.162, Pfaffenwaldring 47

Schedule

• Mondays, 11:30-13:00, Exercises in room V38.04
• Tuesdays, 9:45-11:15, Lecture in room V38.04
• Thursdays, 9:45-11:15, Lecture/Exercises in room V47.05

Material

Here you can download the latest revisions of the lecture slides and additional material using login and password given in the first lecture. If you find any errors or typos, drop me a mail. I'll correct them and publish new revisions here.

• Slides: 1. Scope of Computer Architecture (Rev 1)
• Slides: 2. Technology (Rev 1)
  • Kuo, W. and Kim, T.: An overview of manufacturing yield and reliability modeling for semiconductor products Proceedings of the IEEE, 1999, 87, 1329-1344
  • Williams, T. and Brown, N.: Defect Level as a Function of Fault Coverage IEEE Transactions on Computers, 1981, C-30, 987-988
  • J. Vial, A. Bosio, P. Girard, C. Landrault, S. Pravossoudovitch, and A. Virazel: Yield Improvement, Fault-Tolerance to the Rescue? 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 6-9 July 2008, Rhodes, Greece, IEEE Computer Society, 2008, 165-166
  • Exercise Sheet Discussion 2.11.2009 and 5.11.2009
• Slides: 3. Power and Performance (Rev 1)
  • Chapter 14 of the book S. Hassoun, T. Sasao and R.K. Brayton: Logic Synthesis and Verification, Kluwer Academic Publishers, 2002, discusses static timing analysis (dealing with path delays and path sensitization). Many good references are also given for further reading.
  • K. Singh, A. Wang, R. Brayton and A. Sangiovanni-Vincentelli: Timing optimization of combinational logic Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on, 1988, 282-285.
  • McGeer, P.C.; Brayton, R.K.; Sangiovanni-Vincentelli, A.L.; Sahni, S.K.: Performance Enhancement Through the Generalized Bypass Transform Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on, Vol., Iss., 11-14 Nov 1991, pp 184-187.
  • Keutzer, K.; Malik, S.; Saldanha, A.: Is Redundancy Necessary to Reduce Delay? Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol.10, Iss.4, Apr 1991, pp 427-435.
  • Berman, C.L.; Hathaway, D.J.; LaPaugh, A.S.; Trevillyan, L.H.: Efficient Techniques for Timing Correction Circuits and Systems, 1990., IEEE International Symposium on, Vol., Iss., 1-3 May 1990, pp 415-419, vol.1.
  • Touati, H.J.; Savoj, H.; Brayton, R.K.: Delay Optimization of Combinational Logic Circuits by Clustering and Partial Collapsing Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on, Vol., Iss., 11-14 Nov 1991, pp. 188-191.
  • Eugene L. Lawler, Karl N. Levitt, James Turner: Module Clustering to Minimize Delay in Digital Networks IEEE Trans. on Computers, Vol.C-18, Number 1, pp. 47-57, Jan 1969.
  • Gonzalez, R.; Gordon, B.M.; Horowitz, M.A.: Supply and Threshold Voltage Scaling for Low Power CMOS Solid-State Circuits, IEEE Journal of, Vol.32, Iss.8, Aug 1997, pp 1210-1216.
  • Exercise Sheet Discussion starting on 16.11.2009
• Slides: 4. Computer Arithmetics (Rev 1)
  • Appendix I of the book: Hennessy, Patterson: Computer Architecture - A Quantitative Approach 4th ed.
  • Vojin G. Oklobdzija, Earl R. Barnes: Some optimal schemes for ALU implementation in VLSI technology Proc. 7th Symp. Comput. Arithmetic, 1985.
  • Volder, J. E.: The CORDIC Trigonometric Computing Technique IRE Trans. on Electron. Computers, 1959, EC-8, 330-334.
  • Naini, A.; Dhablania, A.; James, W. and Das Sarma, D.: 1 GHz HAL SPARC64R Dual Floating Point Unit with RAS features Computer Arithmetic, 2001. Proceedings. 15th IEEE Symposium on, 2001, 173-183
  • Oh, H.; Mueller et al.: A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor Solid-State Circuits, IEEE Journal of, 2006, 41, 759-771