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The exponential performance increase of a single core has come to an end. Many multi-core-processors are already available on the market. In the next years this trend will continue towards hundreds of cores on a single die which imposes new challenges. Current interconnection approaches like buses and crossbar switches will not be efficient anymore and new interconnection schemes are needed. Network-on-Chip (NoC) is a multi-hop on-chip interconnection network that usually features packet switching and a regular topology. A variety of different NoC architectures are currently being investigated, with different flow control, routing algorithms, and network topologies. Beside these functional aspects, future NoCs will have to deal with massive defects, production variations, ageing effects, crosstalk and single event upsets, leading to permanent, intermittent, and transient faults that affect NoC communication. In this seminar, the students learn, how different design decisions and alternatives influence properties like reliability, power, area and performance. News
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Last change $Date: 2009/07/15 13:21:16 $( mi) | © Universität Stuttgart | Impressum |