My Experience at 23rd VLSI Test Symposium

In this presentation I will share my experience at the 23rd IEEE VLSI Test Symposium held from 1st to 5th May 2005 in Palm Springs and will introduce some new concepts and techniques presented at this symposium about Memory Testing, Low Power Testing and Diagnosis.

Reliability in the BlueGene/L series of supercomputers

Generating a theoretical peak computing speed of 360 trillion operations (TFLOP/s) per second, occupying 300 sq. m. of floor space, and consuming 1.5 MW of electrical power - a fraction of the space and power needed by other supercomputers at this scale - BlueGene/L will likely be the fastest supercomputer on the planet when it is fully deployed this year. This massively parallel system of 65,536 nodes is based on a new architecture that exploits system-on-a-chip technology to deliver a very high compute density and energy efficiency. The design point of BG/L utilizes IBM PowerPC embedded CMOS processors, embedded DRAM, and system-on-a-chip techniques that allow for integration of all system functions including compute processor, communications processor, 3 cache levels, and multiple high speed interconnection networks with sophisticated routing onto a single ASIC. Every node has access to 256 or 512MB of main memory in 9 DRAM chips and is connected to 3 multi-dimensional networks of various topologies. With 64k compute ASICs, more than 500k DRAM chips and miles and miles of cabling things are bound to fail. The reliability of systems this large can only be assured using a strict design with redundancy in the hardware as well as in the software. This presentation gives an introduction to the BlueGene/L supercomputer with an additional focus on the measures taken with respect to the system reliability.

From Embedded Test to Embedded Diagnosis

Testing integrated circuits with millions of transistors puts strong requirements on test volume, test application time, test speed, and test resolution. To overcome these challenges, it is widely accepted to partition test resources between the automatic test equipment (ATE) and the circuit under test (CUT). These strategies may reach from simple test data compression/decompression schemes to implementing a complete built-in self-test. Very often these schemes come with reduced diagnostic resolution. In this paper, an overview is given on techniques for embedding test into a circuit while still keeping diagnostic capabilities. Built-in diagnosis techniques may be used after manufacturing, for chip characterization and field return analysis, and even for rapid prototyping.

Backend zum Erzeugen von Testmustergeneratoren für den Pseudo Erschöpfenden Test von Schaltnetzen

Die Komplexität hochintegrieter Schaltungen nimmt immer weiter zu. Ein 32-Bit Volladdierer mag bei Taktfrequenzen im Gigahertzbereich noch mit akzeptablem Zeitaufwand erschöpfend testbar sein. Eine Schaltung mit 64 oder mehr Eingängen ist nicht mehr in wenigen Sekunden erschöpfend zu testen, da der Zeitaufwand exponentiell mit der Anzahl der Eingänge zunimmt. Analysiert man eine Schaltung, so ist ersichtlich, dass ein Ausgang meist nur von einer Teilmenge aller Eingägne abhängt. Ein "Pseudo Erschöpfender Test" (PET) führt nun einen Test der Ausgänge einer Schaltung so durch, dass nur die Eingänge berücksichtigt werden, die den Wert an einem Ausgang auch verändern können. So lassen sich Ausgänge eventuell parallel testen, und die einzelnen Testlängen werden deutlich reduziert. Ziel der Arbeit ist es, ein Backend zu erstellen, welches zu einer gegebenen Überdeckung eines Schaltnetzes einen Pseudo Erschöpfenden Test erzeugt, d. h. es wird ein Testmustergenerator erzeugt. Um die Qualität des berechneten Testmustergenerators zu bestimmen, soll Fehlersimulationen durchgeführte werden. Dazu soll eine äquivalente Beschreibung des Testmustergenerators in VHDL erzeugt werden. Anschliessend wird dann einerseits eine compilierte Fehlersimulation durchgeführt, und andererseits wird die Ausgabe des vom Backend erzeugten Testmustergenerators direkt benutzt, um eine Sofwarefehlersimulation durchzuführen. Anschliessend sind die Ergebnisse der Fehlersimulation zu vergleichen.

Finding the maximum solvable set in a system of linear equations

The behavior of a Linear Feedback Shift Register (LFSR), for a given characteristic polynomial, can be completely described by a system of linear equations. Finding the maximum number of linearly independent equations amongst a system of equations is an NP-complete problem. A heuristic is developed that finds the best or nearly best solution in a reasonable time. This heuristic along with the experimental results for ISCAS as well as some industrial circuits will be presented in this talk.

Eclipse Plug-In for Signs Gate Netlist Simulator

Signs, or SImple Gate Netlist Simulator, is a gate-level circuit analysis and simulation tool for VHDL and ISCAS design descriptions. Based on the Plug-In mechanism of Eclipse platform, a Signs plugin is contributed. In this presentation, the functions of this plugin will be shown, also the feutures of Eclipse Plug-In Development will be introduced. The algorithms for compiling the VHDL language and the architecture of this Plug-In will be presented.

On The Reliability Evaluation of SRAM-Based FPGA Designs

Benefits of Field Programmable Gate Arrays (FPGAs) have lead to a spectrum of use ranging from consumer products to astronautics. This diversity necessitates the need to evaluate the reliability of the FPGA, because of their high susceptibility to soft errors, which are due to the high density of embedded SRAM cells. Reliability evaluation is an important step in designing highly reliable systems, which results in a strong competititve advantage in todays marketplace. This presentation will introduce a mathematical model able to evaluate and therefore help improve the reliability of SRAM-based FPGAs.

Studies on Software-based Self-test of Processors

This talk is split into two parts. In the first part, the extension of our preceding work on software-based self-test of processors under power constraints is presented, where the whole methodology is applied to a 32-bit processor core. We make an effort on exploration of changes to the methodology when applied to different designs. In the second part, some basics on instruction level DFT are addressed. For our initial step, we only concentrate on a simple core with 16-bit buses.

A low power error detecting scheme for high speed low latency address busses

A low power error detecting scheme will be presented and compared to state-of-the-art error detecting codes for the same purpose. It features low power, low latency, low hardware overhead as well as high adaptibility towards design constraints like bus width, number of code bits and power consumption.

Synthesis of Irregular Combinational Functions with Large Dont Care Sets

Finding efficient multi-level implementations for Boolean functions is essential in logic design and test. A special case is when these functions are irregular, which means that the input assignments mapped to 1 are randomly spread over their definition space. Here an efficient way is presented to implement irregular Boolean functions with dont cares. A key feature of these functions is their incomplete specification, which is based on a large don t care set. In a first step, reduced ordered binary decision diagrams (ROBDD) are used for representing and manipulating the involved functions. Then, a multi-level representation is obtained with the help of free binary decision diagrams (FBDD). For all the considered functions, implementations are found with a significant node count reduction compared to methods offered by a state-of-the-art BDD package. Furthermore, the average gate count per node is reduced, as well.

VHDL-Synthesis

Over the past year Signs, a free synthesis tool developed at the insitute, has learned to synthesize a lot more VHDL constructs. In this talk some of the problems which had to be solved will be discussed and the algorithms used for synthesis will be presented. Currently Signs supports RT-level VHDL synthesis (defined by IEEE Standard 1076.6) but some high-level synthesis algorithms as well as optimization algorithms will also be presented.

Computing-Cluster-Based ATPG for Combinational Circuits

Deterministic Automated Test Pattern Generation is known to be NP-complete. Efficient serial algorithms exist that tackle current industrial sized circuits. But increasing circuit sizes result in long runtimes and demand for a better solution. The objective of this work is a parallelized implementation of a suitable state-of-the-art ATPG algorithm optimized for performance. This implementation should not harm the quality of the test pattern set with respect to compactness and resolution compared to serial algorithms.

Evaluation of Agile Methodologies for Embedded Systems

Agile methodologies are the emerging force in the world of development process models designed to face the challenges of an increasingly volatile marketplace. Changing requirements and shorter deadlines have led to an increased deviation from the practices of traditional, heavyweight processes to the adoption of practices which promote a more lightweight development environment. While many agile methods have been introduced, none of them are specifically targeted for the development of embedded systems. Can agile development methods fit to embedded systems where the amount of code is not the primary scaling factor, but rather issues of performance, reliability and constantly changing requirements are significant. I would like to present some of the evaluation results of my master thesis that explores the possibility of applying agile methodologies in the domain of embedded systems.