http://www.iti.uni-stuttgart.de/ News - Institut für Technische Informatik de http://www.iti.uni-stuttgart.de/fileadmin/templates/ITI/rss/ITI_194x116.png http://www.iti.uni-stuttgart.de/ 194 116 News - Institut für Technische Informatik TYPO3 - get.content.right http://blogs.law.harvard.edu/tech/rss Thu, 19 Jul 2012 15:45:00 +0200 http://www.iti.uni-stuttgart.de/aktuell/details/efficient-simulation-based-characterization-of-single-event-transients-in-floating-point-data-paths/3494da7f60fcea613ee51d6e1a72a4ed.html 15:45-16:30, V47.06, Dipl.-Inform. Claus Braun, Institut für Technische Informatik
Floating-point arithmetic is an essential component of most applications in scientific computing and simulation technology. For GPGPU accelerators, floating-point processing is even the main operational task. In this talk, a standard-compliant Floating-point Processing Unit (FPU) is used to investigate the impact of soft errors in the data path. How vulnerable is such a data path? What kinds of errors become visible and how critical are they?]]> Open Seminar - Rechnerarchitektur SS 12 Thu, 19 Jul 2012 15:45:00 +0200 http://www.iti.uni-stuttgart.de/aktuell/details/modeling-of-design-for-test-infrastructure-in-complex-systems-on-chips/965cef6636395fcdec2aa581cd0bda97.html 15:45-16:30, V47.06, M. Sc. cand. David Buntoro, Institut für Technische Informatik
In order to assess the hardware integrity of a chip over its complete life-cycle, it is promising to reuse the DFT infrastructure as part of system-level test.

In this thesis, the provided system, a Tricore processor from Infineon,  must me partitioned and modified in order to enable the autonomous structural  test of every component of the system in the field without expensive external equipment.]]> Open Seminar - Rechnerarchitektur SS 12 Thu, 12 Jul 2012 15:45:00 +0200 http://www.iti.uni-stuttgart.de/aktuell/details/effectivity-of-high-level-mutants-in-lower-level-fault-representation/d6968302e875b09a7b6ae602520603c5.html 16:30-17:15, V47.06, Dipl.-Inf. Laura Rodríguez Gómez, Institut für Technische Informatik Open Seminar - Rechnerarchitektur SS 12 Thu, 05 Jul 2012 16:30:00 +0200 http://www.iti.uni-stuttgart.de/aktuell/details/aging-monitor-path-selective-monitoring/b6ab394ebd0061c085c252d9f09e6c0c.html 15:45-16:30, V47.06, M. Sc. Chang Liu, Institut für Technische Informatik In this seminar, to avoid above unwanted situation, two solutions are proposed: stability checker relocation and path activation monitor development. The efficiency of these synergic solutions is proved by the experimental results.]]> Open Seminar - Rechnerarchitektur SS 12 Thu, 05 Jul 2012 15:45:00 +0200 http://www.iti.uni-stuttgart.de/aktuell/details/tag-der-wissenschaften/3adf6f7503d93b6dfbaf0002fa5c94c0.html 11:00 - 19:00 Uhr, Campus Vaihingen Link.]]> Events Sat, 30 Jun 2012 11:00:00 +0200 http://www.iti.uni-stuttgart.de/aktuell/details/emulation-of-automotive-complex-systems-on-chips/e6eec1b0586ff29162882275708a6a02.html 16:30-17:15, V47.06, M. Sc. cand. Mina Tawfik, Institut für Technische Informatik
In this thesis, an emulation system for a target automotive controller must be architected and implemented. The controller is the Tricore, a current microprocessor design provided by our industrial partners.]]> Open Seminar - Rechnerarchitektur SS 12 Thu, 28 Jun 2012 16:30:00 +0200 http://www.iti.uni-stuttgart.de/aktuell/details/test-pattern-generation-for-sh-time-violations-under-variations/82160003e8277772a5e8156203a2f9d0.html 15:45-16:30, V47.06, M.Sc., Anusha Kakarala, Institut für Technische Informatik Open Seminar - Rechnerarchitektur SS 12 Thu, 28 Jun 2012 15:45:00 +0200 http://www.iti.uni-stuttgart.de/aktuell/details/efficient-multi-level-parallel-nfp-simulation-platform/ceb133d741ccac10d718e2981f06ab5b.html 16:30-17:15, V47.06, M.Sc. Nadereh Hatami, Institut für Technische Informatik techniques for fast high-level simulation do not provide enough details for NFP analysis. The goal of this paper is to bridge this gap by combining the accuracy of low-level models with high-level simulation speed. We introduce an efficient mixed-level NFP prediction methodology that considers both the structure and application of a system. The system is modeled at transaction-level to enable high simulation speed. To maintain accuracy, NFP assessment for cores under analysis is conducted at gate-level by cycle-accurate simulation. To speed up the simulation, high level transactions are being simulated in parallel using gate-level state prediction. We propose effective techniques for cross-level synchronization and idle simulation speed-up. The proposed method is from 7 up to 400 times faster with mean error below 0.006%. ]]> Open Seminar - Rechnerarchitektur SS 12 Thu, 21 Jun 2012 16:30:00 +0200 http://www.iti.uni-stuttgart.de/aktuell/details/optimal-pattern-retargeting-for-reconfigurable-scan-networks/249b7e4370fe0df741f53f7002b52917.html 15:45-16:30, V47.04, M.Sc. Rafal Baranowski, Institut für Technische Informatik Open Seminar - Rechnerarchitektur SS 12 Thu, 21 Jun 2012 15:45:00 +0200 http://www.iti.uni-stuttgart.de/aktuell/details/in-field-scan-test-of-automotive-ics/3c101cf30ea9ad8ac96c4750b8049f7c.html 16:15-16:45, V47.06, Dipl.-Inf. Dominik Ull, Institut für Technische Informatik Open Seminar - Rechnerarchitektur SS 12 Thu, 24 May 2012 16:15:00 +0200