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Institut für Technische Informatik

Journals and Conferences

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    2010

  1. Efficient Fault Simulation on Many-Core Processors
    Michael A. Kochte, Marcel Schaal, Hans-Joachim Wunderlich, Christian G. Zoellin
    accepted for publication at 47th ACM/IEEE Design Automation Conference, Anaheim, CA, USA, June 13 - 18, 2010

  2. Low-Power Test Planning for Arbitrary At-Speed Delay-Test Clock Schemes
    Christian Zoellin, Hans-Joachim Wunderlich
    accepted for publication at IEEE VLSI Test Conference (VTS), Santa Cruz, CA, USA, April 18 - 21, 2010

  3. BISD: Scan-Based Built-In Self-Diagnosis
    Melanie Elm, Hans-Joachim Wunderlich
    accepted for publication at ACM/IEEE Design Automation and Test in Europe (DATE), 2010

    4. 2009

  4. XP-SISR: Eingebaute Selbstdiagnose für Schaltungen mit Prüfpfad
    Melanie Elm, Hans-Joachim Wunderlich
    VDE Tagung "Zuverlässigkeit und Entwurf" (ZuE), Stuttgart, Germany, September 21-23, 2009, pp. 21-28 , docid: 453178004

  5. Adaptive Debug and Diagnosis Without Fault Dictionaries
    Stefan Holst, Hans-Joachim Wunderlich
    Journal of Electronic Testing - Theory and Applications (JETTA), Vol. 25, No. 4-5, August 2009, pp. 259-268, doi: 10.1007/s10836-009-5109-3

  6. Test Encoding for Extreme Response Compaction
    Michael A. Kochte, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich
    IEEE European Test Symposium (ETS'09), Sevilla, Spain, May 25-29, 2009, pp. 155-160, doi: 10.1109/ETS.2009.22

  7. Concurrent Self-Test with Partially Specified Patterns For Low Test Latency and Overhead
    Michael A. Kochte, Christian G. Zoellin, Hans-Joachim Wunderlich
    IEEE European Test Symposium (ETS'09), Sevilla, Spain, May 25-29, 2009, pp. 53-58, doi: 10.1109/ETS.2009.26

  8. Restrict Encoding for Mixed--Mode BIST
    Abdul-Wahid Hakmi, Stefan Holst, Hans-Joachim Wunderlich, Juergen Schloeffel, Friedrich Hapke, Andreas Glowatz
    IEEE VLSI Test Symposium (VTS'09), Santa Cruz, California, USA, May 3-7, 2009, pp. 179-184, doi: 10.1109/VTS.2009.43

  9. A Diagnosis Algorithm for Extreme Space Compaction
    Stefan Holst, Hans-Joachim Wunderlich
    Design, Automation and Test in Europe (DATE'09), Nice, France, April 20-24, 2009, pp. 1355-1360, ieee: 5090875

  10. Test Exploration and Validation Using Transaction Level Models
    Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Rauf Salimi Khaligh, Martin Radetzki, Hans-Joachim Wunderlich, Stefano Di Carlo, Paolo Prinetto
    Design, Automation and Test in Europe (DATE'09), Nice, France, April 20-24, 2009, pp. 1250-1253, ieee: 5090856

    11. 2008

  11. Erkennung von transienten Fehlern in Schaltungen mit reduzierter Verlustleistung
    Detection of transient faults in circuits with reduced power dissipation
    M. E. Imhof, H.-J. Wunderlich, C. G. Zoellin
    2. GMM/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE), Ingolstadt, Germany, 29.09. - 01.10.2008, pp. 107-114, docid: 453119017

  12. Zur Zuverlässigkeitsmodellierung von Hardware-Software-Systemen
    On the Reliability Modeling of Hardware-Software-Systems
    M. Kochte, R. Baranowski, H.-J. Wunderlich
    2. GMM/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE), 29.09 - 01.10.2008, Ingolstadt, Germany, docid: 453119013

  13. Integrating Scan Design and Soft Error Correction in Low-Power Applications
    M. E. Imhof, H.-J. Wunderlich, C. G. Zoellin
    14th IEEE International On-Line Testing Symposium (IOLTS), Rhodes, Greece, July 7-9, 2008, pp. 59-64, doi: 10.1109/IOLTS.2008.31

  14. Scan Chain Clustering for Test Power Reduction
    M. Elm, M. E. Imhof, H.-J. Wunderlich, C. G. Zoellin, J. Leenstra, N. Maeding
    45th ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, USA, June 8-13, 2008, pp. 828-833, doi: 10.1145/1391469.1391680

  15. Selective Hardening in Early Design Steps
    C. G. Zoellin, H.-J. Wunderlich, I. Polian, B. Becker
    13th IEEE European Test Symposium (ETS), Lago Maggiore, Italy, May 25-29, 2008, pp. 185-190, doi: 10.1109/ETS.2008.30

  16. A Framework for Scheduling Parallel DBMS User-Defined Programs on an Attached High-Performance Computer
    M. A. Kochte, R. Natarajan
    ACM International Conference on Computing Frontiers, Ischia, Italy, May 5-7, 2008, pp. 97-104, doi: 10.1145/1366230.1366245

  17. Signature Rollback - A Technique for Testing Robust Circuits
    U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich
    IEEE VTS'08 (26th VLSI Test Symposium), San Diego, California, USA, Apr 27th to May 1st, 2008, pp. 125-130, doi: 10.1109/VTS.2008.34

  18. Scan Chain Organization for Embedded Diagnosis
    M. Elm, H.-J. Wunderlich
    Design, Automation and Test in Europe (DATE'08), Munich, Germany, March 10-14, 2008, pp. 468-473, doi: 10.1109/DATE.2008.4484725

  19. Test Set Stripping Limiting the Maximum Number of Specified Bits
    M. A. Kochte, C. G. Zoellin, M. E. Imhof, H.-J. Wunderlich
    4th IEEE International Symposium on Electronic Design, Test & Applications (DELTA'08), Hong Kong, January 23-25, 2008, pp. 581-586, doi: 10.1109/DELTA.2008.64
    Best paper award

    20. 2007

  20. Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip
    H.-J. Wunderlich, M. Elm, and S. Holst
    Informacije MIDEM, Vol. 37, No. 4(124), Ljubljana, December 2007, pp. 235-243

  21. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance (Invited Paper)
    S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube
    Informacije MIDEM, Vol. 37, No. 4(124), Ljubljana, December 2007, pp. 212-219

  22. Academic Network for Microelectronic Test Education
    F.Novak, A.Biasizzo, Y.Bertrand, M-L.Flottes, L.Balado, J.Figueras, S.Di Carlo, P.Prinetto, N.Pricopi, H-J.Wunderlich and J-P.van der Hayden
    International Journal of Engineering Education, Volume 23 Number 6 2007, pp. 1245-1253, ijee: 2007/00000023/00000006/art00021

  23. Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip (Invited Paper)
    H.-J. Wunderlich, M. Elm, S. Holst
    43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07), Bled, Slovenia, September 12-14, 2007, pp. 27-36

  24. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance (Invited Paper)
    S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube
    43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07), Bled, Slovenia, September 12-14, 2007, pp. 3-10

  25. A Refined Electrical Model for Drift Processes and its Impact on SEU Prediction
    S. Hellebrand, C.G. Zoellin, H.-J. Wunderlich, T. Coym, S. Ludwig, B. Straube
    Proc. of the 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007, pp. 50-58, doi: 10.1109/DFT.2007.43

  26. Programmable Deterministic Built-in Self-test
    A.-W. Hakmi, H.-J. Wunderlich, C.G. Zoellin, A. Glowatz, F. Hapke, J. Schloeffel, L. Souef
    Proc. of the International Test Conference (ITC), Santa Clara, CA, USA, October 23 - 25, 2007, pp. 1-9., doi: 10.1109/TEST.2007.4437611

  27. Scan Test Planning for Power Reduction
    M.E. Imhof, C.G. Zöllin, H.-J. Wunderlich, N. Maeding, J. Leenstra
    44th ACM/IEEE Design Automation Conference (DAC), San Diego, Ca, USA, June 4-8, 2007, pp. 521-526, doi: 10.1145/1278480.1278614

  28. Analyzing Test and Repair Times for 2D Integrated Memory Built-In Test and Repair
    P. Öhler, S. Hellebrand, H.-J. Wunderlich
    10th IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems (DDECS), Krakow, Poland, April 11-13, 2007, pp. 1-6, doi: 10.1109/DDECS.2007.4295278
    Best paper award

  29. An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy
    P. Öhler, S. Hellebrand, H.-J. Wunderlich
    12th IEEE European Test Symposium (ETS), Freiburg, Germany, May 21-24, 2007, pp. 91-96, doi: 10.1109/ETS.2007.10

  30. Adaptive Debug and Diagnosis without Fault Dictionaries
    S. Holst, H.-J. Wunderlich
    12th IEEE European Test Symposium (ETS), Freiburg, Germany, May 21-24, 2007, pp. 7-12, doi: 10.1109/ETS.2007.9
    Best paper award

  31. Domänenübergreifende Zuverlässigkeitsbewertung in frühen Entwicklungsphasen unter Berücksichtigung von Wechselwirkungen
    M. Wedel, P. Göhner, J. Gäng, B. Bertsche, H.-J. Wunderlich, T. Arnaout
    In: 5. Paderborner Workshop "Entwurf mechatronischer Systeme", J. Gausemeier et al. (ed.), Bd. 210, Paderborn, Germany, March 22-23, 2007, pp. 257-272

  32. Deterministic Logic BIST for Transition Fault Testing
    V. Gherman, H.-J. Wunderlich, J. Schlöffel, M. Garbers
    IET Proceedings on "Computers & Digital Techniques" 1, (3), 2007, pp. 180-186, doi: 10.1049/iet-cdt:20060131

  33. Test und Zuverlässigkeit nanoelektronischer Systeme
    B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich
    Tagung Zuverlässigkeit und Entwurf (ZuD), Munich, Germany, March 26-28, 2007, pp. 139-140

  34. Synthesis of Irregular Combinational Functions with Large Don't Care Sets
    V. Gherman, H.-J. Wunderlich, R.D.- Mascarenas, J.Schloeffel, M. Garbers
    ACM Great Lakes Symposium on VLSI (GLSVLSI), Stresa - Lago Maggiore, Italy, March 11-13, 2007, pp. 287-292, doi: 10.1145/1228784.1228856

  35. Verlustleistungsoptimierende Testplanung zur Steigerung von Zuverlässigkeit und Ausbeute
    M.E. Imhof, C.G. Zöllin, H.-J. Wunderlich, N. Maeding, J. Leenstra
    Tagung Zuverlässigkeit und Entwurf (ZuD), Munich, Germany, March 26-28, 2007, pp.69-76, docid: 463023008

    36. 2006

  36. DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme
    B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich
    it - Information Technology, Vol. 48, No. 5, 2006, pp. 304-311, doi: 10.1524/itit.2006.48.5.304

  37. BIST Power Reduction Using Scan-Chain Disable in the Cell Processor
    C. Zoellin, H.-J. Wunderlich, N. Maeding, J. Leenstra
    Proc. of the International Test Conference (ITC), Santa Clara, CA, USA, October 24 - 26, 2006, pp. 1-8, doi: 10.1109/TEST.2006.297695

  38. Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing
    N. Badereddine, P. Girard, S. Pravossoudovitch, C. Landrault, A. Virazel, H.-J. Wunderlich
    Proc. of the IFIP International Conference on Very Large Scale Integration (VLSI-Soc), Nice, France, October 16 - 18, 2006, pp. 403-408, doi: 10.1109/VLSISOC.2006.313222

  39. Minimizing Peak Power Consumption during Scan Testing: Test Pattern Modification with X Filling Heuristics
    N. Badereddine, P. Girard, S. Pravossoudovitch, C. Landrault, A. Virazel, H.-J. Wunderlich
    Proc. of the Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS), Tunis, Tunisia, September 5 - 7, 2006, pp. 359-364, doi: 10.1109/DTIS.2006.1708693

  40. Deterministic Logic BIST for Transition Fault Testing
    V. Gherman, H.-J. Wunderlich, J. Schlöffel, M. Garbers
    Proc. of the European Test Symposium (ETS), Southampton, UK, May 22 - 25, 2006, pp. 123-128, doi: 10.1109/ETS.2006.12

  41. X-Masking During Logic BIST and its Impact on Defect Coverage
    Y. Tang, H.-J. Wunderlich, P. Engelke, I. Polian, B. Becker, J. Schlöffel, F. Hapke, M. Wittke
    IEEE Transactions on Very Large Scale Integrated (VLSI) Systems, Vol. 14, No. 2, February 2006, pp. 193-202, doi: 10.1109/TVLSI.2005.863742

  42. Software-Based Self-Test of Processors under Power Constraints
    J. Zhou, H.-J. Wunderlich
    Proc. of the 9th Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, pp. 430 - 436, March 06 - 10, 2006, doi: 10.1109/DATE.2006.243798

  43. Some Common Aspects of Design Validation, Debug and Diagnosis
    T. Arnaout, G. Bartsch, H.-J. Wunderlich
    Proc. of the 3rd IEEE International Workshop on Electronic Design, Test and Applications (DELTA), Kuala Lumpur, Malaysia, January 17-19, 2006, pp. 3-8, doi: 10.1109/DELTA.2006.79

    44. 2005

  44. On the Reliability Evaluation of SRAM-based FPGA Designs
    O. Héron, T. Arnaout, H.-J. Wunderlich
    Proc. of the 15th IEEE International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24 - 26, 2005, pp. 403-408, doi: 10.1109/FPL.2005.1515755

  45. Development of an Audio Player as System-on-a-Chip using an Open Source Platform
    P. Kiatisevi, L. Azuara, R. Dorsch, H.-J. Wunderlich
    Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, Vol. 3, May 23 - 26, 2005, pp. 2935-2938, doi: 10.1109/ISCAS.2005.1465242

  46. From Embedded Test to Embedded Diagnosis
    H.-J. Wunderlich
    Proc. of the 10th IEEE European Test Symposium (ETS), Tallinn, Estonia, May 22 - 25, 2005, pp. 216-221, doi: 10.1109/ETS.2005.26

  47. Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST
    P. Engelke, V. Gherman, I. Polian, Y. Tang, H.-J. Wunderlich, B. Becker
    Proc. of the 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Sopron, Hungary, April 13-16, 2005, pp.11-18

  48. Implementing a Scheme for External Deterministic Self-Test
    A. W. Hakmi, V. Gherman, H.-J. Wunderlich, M. Garbers, J. Schlöffel
    Proc. of the 23rd IEEE VLSI Test Symposium (VTS), Palm Springs, CA, USA, May 1-5, 2005, pp. 101-106, doi: 10.1109/VTS.2005.50

  49. Frühe Zuverlässigkeitsanalyse mechatronischer Systeme
    P. Jäger, B. Bertsche, T. Arnaout, H.-J. Wunderlich
    Proc. 22. VDI Tagung Technische Zuverlässigkeit, Stuttgart, Germany, April 7-8, 2005, pp. 39-56

    50. 2004

  50. X-Masking During Logic BIST and its Impact on Defect Coverage
    Y.Tang, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, P. Engelke, I. Polian, B. Becker,
    Proc. of the 35th IEEE International Test Conference (ITC), Charlotte, NC, USA, October 25-28, 2004, pp. 442-451, doi: 10.1109/TEST.2004.1386980

  51. Efficient Pattern Mapping for Deterministic Logic BIST
    V. Gherman, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, M. Garbers
    Proc. of the 35th IEEE International Test Conference (ITC), Charlotte, NC, USA, October 25-28, 2004, pp. 48-56, ieee: 1386936

  52. Reliability Considerations for Mechatronic Systems on the Basis of a State Model
    P. Göhner, E. Zimmer, T. Arnaout, H.-J. Wunderlich,
    Proc. of the 17th International Conference on Architecture of Computing Systems (ARCS) Augsburg, Germany, March 23-26, 2004, pp. 106-112

  53. Impact of Test Point Insertion on Silicon Area and Timing during Layout
    H. Vranken, F. S. Sapei, H.-J. Wunderlich
    Proc. of the 7th Conference on Design, Automation and Test in Europe (DATE) Paris, France, February 16-20, 2004, pp. 810-815, doi: 10.1109/DATE.2004.1268981

    54. 2003

  54. Test Engineering Education in Europe: the EuNICE-Test Project
    Y. Bertrand, M.-L. Flottes, L. Balado, J. Figueras, A. Biasizzo, F. Novak, S. Di Carlo, P. Prinetto, N. Pricopi, H.- J. Wunderlich
    Proc. of the IEEE International Conference on Microelectronic Systems Education (MSE), Anaheim, CA, June 1-2, 2003, pp. 85-86, doi: 10.1109/MSE.2003.1205266

    55. 2002

  55. Adapting a SoC to ATE Concurrent Test Capabilities
    M. Fischer, R. Huerta Rivera, R. Dorsch, H.-J. Wunderlich
    Proc. of the 33rd International Test Conference (ITC), Baltimore, MD, October 8-10, 2002, pp. 1169-1175, doi: 10.1109/TEST.2002.1041875

  56. High Defect Coverage with Low Power Test Sequences in a BIST Environment
    P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel, H.-J. Wunderlich
    IEEE Design and Test of Computers, Vol. 19, Issue 5, September/October 2002, pp. 44-52, doi: 10.1109/MDT.2002.1033791

  57. Efficient On- and Off-Line Testing of Embedded DRAMs
    S. Hellebrand, H.-J. Wunderlich, A. Ivaniuk, Y. Klimets, V. N. Yarmolik
    IEEE Transaction on Computers, Vol. 51, No. 7, July 2002, pp. 801-809, doi: 10.1109/TC.2002.1017700

  58. Combining Deterministic Logic BIST with Test Point Insertion
    H. Vranken, F. Meister, H.-J. Wunderlich
    Proc. of the 7th European Test Workshop (ETW), Korfu, Greece, May 26-29, 2002, pp. 389-394, doi: 10.1109/ETW.2002.1029646

  59. RESPIN++ - Deterministic Embedded Test
    L. Schäfer, R. Dorsch, H.-J. Wunderlich
    Proc. of the 7th European Test Workshop (ETW), Korfu, Greece, May 26-29, 2002, pp. 139-146, doi: 10.1109/ETW.2002.1029637

  60. Reusing Scan Chains for Test Pattern Decompression
    R. Dorsch and H.-J. Wunderlich
    Journal of Electronic Testing - Theory and Applications (JETTA), Vol. 18, No. 2, April 2002, pp. 231-240, doi: 10.1023/A:1014968930415

  61. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
    H.-G. Liang, S. Hellebrand, H.-J. Wunderlich
    Journal of Electronic Testing - Theory and Applications (JETTA), Vol. 18, No. 2, April 2002, pp. 157-168, doi: 10.1023/A:1014993509806

    62. 2001

  62. Application of deterministic logic BIST on industrial circuits
    G. Kiefer and H. Vranken and E.-J. Marinissen and H.-J. Wunderlich
    Journal of Electronic Testing - Theory and Applications (JETTA), Vol. 17, No. 3, June 2001, pp. 351-362, doi: 10.1023/A:1012283800306

  63. On applying the set covering model to reseeding
    S. Chiusano and S. di Carlo and P. Prinetto and H. Wunderlich
    Proceedings of the conference on Design, automation and test in Europe (DATE01), 2001, pp. 156-161, doi: 10.1109/DATE.2001.915017

  64. Using a Hierarchical DfT Methodology in High Frequency Processor Designs for Improved Delay Fault Testability
    M. Kessler, G. Kiefer, J. Leenstra, K. Schünemann, T. Schwarz and H.-J. Wunderlich
    Proc. of the 32nd IEEE International Test Conference (ITC), Baltimore, MD, October 30-November 1, 2001, pp. 461-469, doi: 10.1109/TEST.2001.966663

  65. Tailoring ATPG for Embedded Testing
    R. Dorsch, H.-J. Wunderlich
    Proc. of the 32nd IEEE International Test Conference (ITC), Baltimore, MD, October 30-November 1, 2001, pp. 530-537, doi: 10.1109/TEST.2001.966671

  66. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
    H.-G. Liang, S. Hellebrand, H.-J. Wunderlich
    Proc. of the 32nd IEEE International Test Conference (ITC), Baltimore, MD, October 30-November 1, 2001, pp. 894-902, doi: 10.1109/TEST.2001.966712

  67. Reusing Scan Chains for Test Pattern Decompression
    R. Dorsch, H.-J. Wunderlich
    Proc. of the 6th European Test Workshop (ETW), Stockholm, Sweden, May 29-June 1, 2001, pp. 124-132, doi: 10.1109/ETW.2001.946677

  68. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
    S. Hellebrand, H-G Liang, H.-J. Wunderlich
    Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 17, No. 3/4, June/August 2001, pp. 341-349, doi: 10.1023/A:1012279716236

  69. A Modified Clock Scheme for a Low Power BIST Test Pattern Generator
    P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, H.-J. Wunderlich
    Proc. of the 19th IEEE VLSI Test Symposium (VTS), Marina Del Rey, CA, April 29-May 3, 2001, pp. 306-311, doi: 10.1109/VTS.2001.923454

  70. Circuit Partitioning for Efficient Logic BIST Synthesis
    A. Irion, G. Kiefer, H. Vranken, H.-J. Wunderlich
    Proc. of the 4th Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, March 12-16, 2001, pp. 86-91, doi: 10.1109/DATE.2001.915005

    71. 2000

  71. Minimized Power Consumption for Scan-Based BIST
    S. Gerstendörfer, H.-J. Wunderlich
    Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 16, No. 3, June 2000, pp. 203-212, doi: 10.1023/A:1008383013319

  72. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
    S. Hellebrand, H-G Liang, H.-J. Wunderlich
    Proc. of the 31st IEEE International Test Conference (ITC), Atlantic City, NJ, October 3-5, 2000, pp. 778-784, doi: 10.1109/TEST.2000.894274

  73. Non-Intrusive BIST for Systems-on-a-Chip
    S. Chiusano, P. Prinetto, H.-J. Wunderlich
    Proc. of the 31st IEEE International Test Conference (ITC), Atlantic City, NJ, October 3-5, 2000, pp. 644-651, doi: 10.1109/TEST.2000.894259

  74. Application of Deterministic Logic BIST on Industrial Circuits
    G. Kiefer, H. Vranken, E. J. Marinissen, H.-J. Wunderlich
    Proc. of the 31st IEEE International Test Conference (ITC), Atlantic City, NJ, October 3-5, 2000, pp. 105-114, doi: 10.1109/TEST.2000.894197

  75. Optimal Hardware Pattern Generation for Functional BIST
    S. Cataldo, S. Chiusano, P. Prinetto, H.-J. Wunderlich
    Proc. of the 3rd Conference on Design, Automation and Test in Europe (DATE), Paris, France, March 27 - 30, 2000, pp. 292-297, doi: 10.1109/DATE.2000.840286

  76. Deterministic BIST with Partial Scan
    G. Kiefer, H.-J. Wunderlich
    Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 16, No. 3, June 2000, pp. 169-177, doi: 10.1023/A:1008374811502

    77. 1999

  77. Minimized Power Consumption for Scan-Based BIST
    S. Gerstendörfer, H.-J. Wunderlich
    Proc. of the 30th IEEE International Test Conference (ITC), Atlantic City, NJ, September 28-30, 1999, pp. 77-84, doi: 10.1109/TEST.1999.805616

  78. Transparent Word-oriented Memory BIST Based on Symmetric March Algorithms
    V. N. Yarmolik, I. V. Bykov, S. Hellebrand, H.-J. Wunderlich
    Proc. of the 3rd European Dependable Computing Conference (EDCC), Prague, Czech Republic, September 15-17, 1999, pp. 339-350, doi: 10.1007/3-540-48254-7_23

  79. Deterministic BIST with Partial Scan
    G. Kiefer, H.-J. Wunderlich
    Proc. of the 4th IEEE European Test Workshop (ETW), Constance, May 25-28, 1999, pp. 110-117, doi: 10.1109/ETW.1999.804415

  80. Error Detecting Refreshment for Embedded DRAMs
    S. Hellebrand, H.-J. Wunderlich, A. Ivaniuk, Y. Klimets, V. N. Yarmolik
    Proc. of the 17th IEEE VLSI Test Symposium (VTS), Dana Point, California, April 25-29, 1999, pp. 384-390, doi: 10.1109/VTEST.1999.766693

  81. Symmetric Transparent BIST for RAMs
    V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich
    Proc. of the 2nd Conference on Design and Test in Europe (DATE), Munich, Germany, March 9-12, 1999, pp. 702-708, doi: 10.1109/DATE.1999.761206

  82. Deterministic BIST with Multiple Scan Chains
    G. Kiefer, H.-J. Wunderlich
    Journal of Electronic Testing: Theory and Applications (JETTA), Volume 14, No 1-2, February 1999, pp. 85-93, doi: 10.1023/A:1008353423305

    83. 1998

  83. Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST
    M. Karkala, N. A. Touba, H.-J. Wunderlich
    Proc. of the 7th Asian Test Symposium (ATS), Singapore, December 2-4, 1998, pp. 492-499, doi: 10.1109/ATS.1998.741662

  84. BIST for Systems-on-a-Chip
    H.-J. Wunderlich
    INTEGRATION - The VLSI Journal, December 1998, pp. 55-78, doi: 10.1016/S0167-9260(98)00021-2

  85. New Transparent RAM BIST Based on Self-Adjusting Output Data Compression
    V. N. Yarmolik, Y. Klimets, S. Hellebrand, H.-J. Wunderlich
    Proc. of Design & Diagnostics of Electronic Circuits & Systems (DDECS), Szczyrk, Poland, September 1998, pp. 27-33

  86. Synthesizing Fast, Online-Testable Control Units
    S. Hellebrand, H.-J. Wunderlich, A. Hertwig
    IEEE Design and Test, Vol. 15, No. 4, October-December 1998, pp. 36-41, doi: 10.1109/54.735925

  87. Deterministic BIST with Multiple Scan Chains
    G. Kiefer, H.-J. Wunderlich
    Proc. of the 29th IEEE International Test Conference (ITC), Washington, DC, October 1998, pp. 1057-1064, doi: 10.1109/TEST.1998.743304

  88. Accumulator Based Deterministic BIST
    R. Dorsch, H.-J. Wunderlich
    Proc. of the 29th IEEE International Test Conference (ITC), Washington, DC, October 1998, pp. 412-421, doi: 10.1109/TEST.1998.743181

  89. Hardware-Optimal Test Register Insertion
    A. P. Stroele, H.-J. Wunderlich
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 6, June 1998, pp. 531-540, doi: 10.1109/43.703833

  90. Fast Self-Recovering Controllers
    A. Hertwig, S. Hellebrand, H.-J. Wunderlich
    Proc. of the 16th IEEE VLSI Test Symposium (VTS), Monterey, CA, April 1998, pp. 296-302, doi: 10.1109/VTEST.1998.670883

  91. Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs
    V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich
    Proc. of the 1st Conference on Design, Automation and Test in Europe (DATE), Paris, France, February 1998 pp. 173-179, doi: 10.1109/DATE.1998.655853

  92. Mixed-Mode BIST Using Embedded Processors
    S. Hellebrand, H.-J. Wunderlich, A. Hertwig
    Journal of Electronic Testing Theory and Applications (JETTA), Vol. 12, Nos. 1/2, February/April 1998, pp. 127-138, doi: 10.1023/A:1008294125692

    93. 1997

  93. Using BIST Control for Pattern Generation
    G. Kiefer, H.-J. Wunderlich
    Proc. of the 28th IEEE International Test Conference (ITC), Washington, DC, November 1997, pp. 347-355, doi: 10.1109/TEST.1997.639636

  94. STARBIST: Scan Autocorrelated Random Pattern Generation
    K.-H. Tsai, S. Hellebrand, J. Rajski, M. Marek Sadowska
    Proc. of the ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, June 1997, pp. 472-478, doi: 10.1145/266021.266203

  95. Fast Controllers for Data Dominated Applications
    A. Hertwig, H.-J. Wunderlich
    Proc. of the European Design & Test Conference (ED&TC), Paris, France, March 1997, pp. 84-89, doi: 10.1109/EDTC.1997.582337

    96. 1996

  96. Bit-Flipping BIST
    H.-J. Wunderlich, G. Kiefer
    Proc. of the ACM/IEEE International Conference on CAD-96 (ICCAD), San Jose, CA, November 1996, pp. 337-343, doi: 10.1109/ICCAD.1996.569803

  97. Mixed-Mode BIST Using Embedded Processors
    S. Hellebrand, H.-J. Wunderlich, A. Hertwig
    Proc. of the 27th IEEE International Test Conference (ITC), Washington, DC, October 1996, pp. 195-204, doi: 10.1109/TEST.1996.556962

  98. Deterministic Pattern Generation for Weighted Random Pattern Testing
    B. Reeb, H.-J. Wunderlich
    Proc. of the European Design & Test Conference (ED&TC), Paris, France, March 1996, pp. 30-36, doi: 10.1109/EDTC.1996.494124

    99. 1995

  99. Pattern Generation for a Deterministic BIST Scheme
    S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich
    Proc. of the ACM/IEEE International Conference on CAD-95 (ICCAD), San Jose, CA, November 1995, pp. 88-94, doi: 10.1109/ICCAD.1995.479997

  100. Test Register Insertion with Minimum Hardware Cost
    A. P. Ströle, H.-J. Wunderlich
    Proc. of the ACM/IEEE International Conference on CAD-95 (ICCAD), San Jose, CA, November 1995, pp. 95-101, doi: 10.1109/ICCAD.1995.479998

  101. Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
    S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois
    IEEE Transactions on Computers, Vol. 44, No. 2, February 1995, pp. 223-233, doi: 10.1109/12.364534

  102. Synthesis of Iddq-Testable Circuits: Integrating Built-In Current Sensors
    H.-J. Wunderlich, M. Herzog, J. Figueras, J.A. Carrasco, A. Calderon
    Proc. of the European Design & Test Conference (ED&TC), March 1995, pp. 573-580, doi: 10.1109/EDTC.1995.470342

    103. 1994

  103. An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures
    S. Hellebrand, H.-J. Wunderlich
    Proc. of the ACM/IEEE International Conference on CAD-94 (ICCAD), San Jose, CA, November 1994, pp. 110-116, ieee: 629752

  104. A Unified Method for Assembling Global Test Schedules
    A. Ströle, H.- J. Wunderlich
    Proc. of the 3rd Asian Test Symposium (ATS), Nara, Japan, November 1994, pp. 268-273, doi: 10.1109/ATS.1994.367220

  105. Simulation Results of an Efficient Defect Analysis Procedure
    O. Stern, H.-J. Wunderlich
    Proc. of the 25th IEEE International Test Conference (ITC), Washington, DC, October 1994, pp. 729-738, doi: 10.1109/TEST.1994.528019

  106. Configuring Flip-Flops to BIST Registers
    A. Ströle, H.-J. Wunderlich
    Proc. of the 25th IEEE International Test Conference (ITC), Washington, DC, October 1994, pp. 939-948, doi: 10.1109/TEST.1994.528043

  107. Synthesis of Self-Testable Controllers
    S. Hellebrand, H.-J. Wunderlich
    Proc. of the European Design Automation Conference (EDAC/ETC/EuroAsic), Paris, France, March 1994, pp. 580-585, doi: 10.1109/EDTC.1994.326815

    108. 1993

  108. An Efficient BIST Scheme Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers
    S. Venkataraman, J. Rajski, S. Hellebrand, S. Tarnick
    Proc. of the ACM/IEEE International Conference on CAD-93 (ICCAD), Santa Clara, CA, November 1993, pp. 572-577, ieee: 580117

    109. 1992

  109. Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
    S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois
    Proc. of the 23rd IEEE International Test Conference (ITC), Baltimore, MD, September 1992, pp. 120-129, ieee: 527812

  110. Erfassung und Modellierung komplexer Funktionsfehler in Mikroelektronik-Bauelementen
    O. Stern, H.-J. Wunderlich
    ITG-Fachbericht 119, 5. ITG-Fachtagung Mikroelektronik für die Informationstechnik, VDE-Verlag Stuttgart, March 1992, pp. 117-122

  111. Efficient Test Set Evaluation
    H.-J. Wunderlich, M. Warnecke
    Proc. of the European Conference on Design Automation (EDAC), Brussels, March 1992, pp. 428-433, doi: 10.1109/EDAC.1992.205970

  112. Prüfgerechter Entwurf und Test hochintegrierter Schaltungen
    H.-J. Wunderlich, M. H. Schulz
    Informatik-Spektrum, Vol. 15, Issue 1, February 1992, pp. 23-32, doi: 10.1109/43.124417

  113. Optimized Synthesis Techniques for Testable Sequential Circuits
    B. Eschermann, H.-J. Wunderlich
    IEEE Transactions on Computer-Aided Design, Vol. 11, No.3, March 1992, pp. 301-312, doi: 10.1109/43.124417

  114. The Pseudoexhaustive Test of Sequential Circuits
    H.-J. Wunderlich, S. Hellebrand
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 11, No.1, January 1992, pp. 26-33, doi: 10.1109/43.108616

    115. 1991

  115. Emulation of Scan Paths in Sequential Circuit Synthesis
    B. Eschermann, H.-J. Wunderlich
    Proc. of the 5th International Conference on Fault-Tolerant Computing Systems, Nürnberg, Springer-Verlag, Informatik Fachberichte, September 1991, pp. 136-147

  116. A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic
    T. Kropf, H.-J. Wunderlich
    Proc. of the 22nd IEEE International Test Conference (ITC), Nashville, TE, October 1991, pp. 57-66, ieee: 519494

  117. Signature Analysis and Test Scheduling for Self-Testable Circuits
    A. Ströle, H.-J. Wunderlich
    Proc. of the 21st International Symposium on Fault-Tolerant Computing (FTCS), Montreal, June 25-27, 1991, pp. 96-103, doi: 10.1109/FTCS.1991.146640

  118. A Unified Approach for the Synthesis of Self-Testable Finite State Machines
    B. Eschermann, H.-J. Wunderlich
    Proc. of the 28th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 1991, pp. 372-377, ieee: 979744

  119. Maximizing the Fault Coverage in Complex Circuits by Minimal Number of Signatures
    H.-J. Wunderlich, A. Ströle
    Proc. of the International Symposium on Circuits and Systems (ISCAS), Singapur, June 11-14, 1991, pp. 1881-1884, doi: 10.1109/ISCAS.1991.176774

  120. TESTCHIP: A Chip for Weighted Random Pattern Generation, Evaluation, and Test Control
    A. Ströle, H.-J. Wunderlich
    IEEE Journal of Solid-State Circuits, Vol.26, No.7, July 1991, pp. 1056-1063, doi: 10.1109/4.92026

  121. Parallel Self-Test and the Synthesis of Control Units
    B. Eschermann, H.-J. Wunderlich
    Proc. of the 2nd European Test Conference (ETC), Munich, April 1991, pp. 73-82

    122. 1990

  122. TEST CHIP: A Chip for Weighted Random Pattern Generation, Evaluation and Test Control
    A. Ströle, H.-J. Wunderlich, O.F. Haberl
    Proc. of the 16th European Solid-State Circuits Conference (ESSCC), Grenoble, France, 1990, pp. 101-104

  123. Error Masking in Self-Testable Circuits
    A. Ströle, H.-J. Wunderlich
    Proc. of the 21st IEEE International Test Conference (ITC), Washington, DC, September 10-14, 1990, pp. 544-552, doi: 10.1109/TEST.1990.114066

  124. Generating Pseudo-Exhaustive Vectors for External Testing
    S. Hellebrand, H.-J. Wunderlich, O. F. Haberl
    Proc. of the 21st IEEE International Test Conference (ITC), Washington, DC, September 10-14, 1990, pp. 670-679, doi: 10.1109/TEST.1990.114082

  125. Methoden der Testvorbereitung zum IC-Entwurf
    H.-J. Wunderlich, M. H. Schulz
    Mikroelektronik, VDE-Verlag, Vol. 4, Issue 3, May/June 1990, pp. 112-115

  126. Optimized Synthesis of Self-Testable Finite State Machines
    B. Eschermann, H.-J. Wunderlich
    Proc. of the 20th International Symposium on Fault-Tolerant Computing (FTCS), Newcastle, UK, June 26-28, 1990, pp. 390-397, doi: 10.1109/FTCS.1990.89393

  127. The Effictiveness of Different Test Sets For PLAs
    P.C. Maxwell, H.-J. Wunderlich
    Proc. of the 1st European Design Automation Conference (EDAC), Glasgow, UK, March 1990, pp. 628-632, doi: 10.1109/EDAC.1990.136722

  128. Tools and Devices Supporting the Pseudo-Exhaustive Test
    S. Hellebrand, H.-J. Wunderlich
    Proc. of the 1st European Design Automation Conference (EDAC), Glasgow, UK, March 1990, pp. 13-17, doi: 10.1109/EDAC.1990.136612

  129. A Synthesis Approach to Reduce Test Overhead
    H.-J. Wunderlich, B. Eschermann
    Proc. of the 1st European Design Automation Conference (EDAC), Glasgow, UK, March 1990, p. 671

  130. Multiple Distributions for Biased Random Test Patterns
    H.-J. Wunderlich
    IEEE Transactions on Computer-Aided Design, Vol. 9, No.6, June 1990, pp. 584-593, doi: 10.1109/43.55187

  131. An Analytical Approach to the Partial Scan Problem
    H.-J. Wunderlich, A. Kunzmann
    Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 1, No. 2, 1990, pp. 163-174, doi: 10.1007/BF00137392

    132. 1989

  132. Methoden der Testvorbereitung
    H.-J. Wunderlich, M. H. Schulz
    Proc. of the ITG-Fachtagung Mikroelektronik für die Informationstechnik, Stuttgart, October 3-5, 1989, pp. 55-62

  133. Automatische Synthese selbsttestbarer Moduln für hochkomplexe Schaltungen
    F. Kesel, H.-J. Wunderlich
    Proc. of the ITG-Fachtagung Mikroelektronik für die Informationstechnik, Stuttgart, October 3-5, 1989, pp. 63-68

  134. The Pseudo-Exhaustive Test of Sequential Circuits
    H.-J. Wunderlich, S. Hellebrand
    Proc. of the 20th IEEE International Test Conference (ITC), Washington, DC, 1989, pp. 19-27, doi: 10.1109/TEST.1989.82273

  135. The Design of Random-Testable Sequential Circuits
    H.-J. Wunderlich
    Proc. of the 19th International Symposium on Fault-Tolerant Computing (FTCS), Chicago, June 21-23, 1989, pp. 110-117, doi: 10.1109/FTCS.1989.105552

  136. Parametrisierte Speicherzellen zur Unterstützung des Selbsttests mit optimierten und konventionellen Zufallsmustern
    H.-J. Wunderlich, F. Kesel
    GMD Berichte, 4. E.I.S.-Workshop, Bonn, February 1989, pp. 75-84

  137. The Synthesis of Self-Test Control Logic
    O. Haberl, H.-J. Wunderlich
    Proc. of the COMPEURO 1989, Hamburg, May 8-12, 1989, pp. 5134-5136, doi: 10.1109/CMPEUR.1989.93499

    138. 1988

  138. Automatisierung des Entwurfs vollständig testbarer Schaltungen
    S. Hellebrand, H.-J. Wunderlich
    Proc. GI - 18. Jahrestagung II, Hamburg, Informatik-Fachberichte 188, Springer-Verlag, 1988, pp. 145-159

  139. Multiple Distributions for Biased Random Test Patterns
    H.-J. Wunderlich
    Proc. of the 19th IEEE International Test Conference (ITC), Washington, DC, September 12-14, 1988, pp. 236-244, doi: 10.1109/TEST.1988.207808

  140. Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits
    H.-J. Wunderlich, S. Hellebrand
    Proc. of the 18th International Symposium on Fault-Tolerant Computing (FTCS), Tokyo, Japan, June 27-30, 1988, pp. 36-45

  141. Weighted Random Testing with Multiple Distributions
    Hans-Joachim Wunderlich
    Proc. of the 11th International Conference on Fault Tolerant Systems and Diagnostics , Akademie der Wissenschaften der DDR, Suhl, 1988, pp. 88-93, doi: 10.1109/FTCS.1988.5294

  142. Integrated Tools for Automatic Design for Testability
    D. Schmid, H.-J. Wunderlich and F. Feldbusch, S. Hellebrand, J. Holzinger,A. Kunzmann
    Tool Integration and Design Environments, F. J. Rammig (Editor), Amsterdam: Elsevier Science Publishers B. V. (North Holland), IFIP, 1988, pp. 233-258

  143. Output-maximal control policies for cascaded production-inventory systems with control and state constraints
    J. Warschat, H.-J. Wunderlich
    Int. Journal of Systems Sci., Vol. 19, No. 6, 1988, pp. 1011-1020, doi: 10.1080/00207728808547182

    144. 1987

  144. The Random Pattern Testability of Programmable Logic Arrays
    H.-J. Wunderlich
    Proc. of the IEEE International Conference on Computer Design (ICCD), New York, 1987, pp. 682-685

  145. On Computing Optimized Input Probabilities for Random Tests
    H.-J. Wunderlich
    Proc. of the 24th ACM/IEEE Design Automation Conference (DAC), Miami Beach, 1987, pp. 392-398, doi: 10.1145/37888.37947

  146. Self Test Using Unequiprobable Random Patterns
    H.-J. Wunderlich
    Proc. of the 17th International Symposium on Fault-Tolerant Computing (FTCS), Pittsburgh, 1987, pp. 258-263

    147. 1986

  147. The Integration of Test and High Level Synthesis in a General Design Environment
    D. Schmid, R. Camposano, A. Kunzmann, W. Rosenstiel, H.-J. Wunderlich
    Proc. of the Integrated Circuits Technology Conference (ICTC), Limerick, Irland, 1986, pp. 317-331

  148. On Fault Modeling for Dynamic MOS Circuits
    H.-J. Wunderlich, W. Rosenstiel
    Proc. of the 23rd ACM/IEEE Design Automation Conference (DAC), Las Vegas, 1986, pp. 540-546, ieee: 1586140

    149. 1985

  149. Design Automation of Random Testable Circuits
    A. Kunzmann, H.-J. Wunderlich
    Proc. of the European Solid-State Circuits Conference (ESSCIRC), Toulouse, 1985, pp. 277-285

  150. PROTEST: A Tool for Probabilistic Testability Analysis
    H.-J. Wunderlich
    Proc. of the 22nd ACM/IEEE Design Automation Conference (DAC), Las Vegas, 1985, pp. 204-211, ieee: 1585936

    151. 1984

  151. Time-optimal control policies for cascaded production-inventory systems with control and state constraints
    J. Warschat, H.-J. Wunderlich
    Int. Journal of Systems Sci., Vol. 15, No. 5, 1984, pp. 513-524, doi: 10.1080/00207729408926580









  1. Adaptive Debug and Diagnosis Without Fault Dictionaries
    Stefan Holst, Hans-Joachim Wunderlich
    Journal of Electronic Testing - Theory and Applications (JETTA), Vol. 25, No. 4-5, August 2009, pp. 259-268, doi: 10.1007/s10836-009-5109-3
    Abstract:
    Diagnosis is essential in modern chip production to increase yield, and debug constitutes a major part in the pre-silicon development process. For recent process technologies, defect mechanisms are increasingly complex, and continuous efforts are made to model these defects by using sophisticated fault models. Traditional static approaches for debug and diagnosis with a simplified fault model are more and more limited. In this paper, a method is presented, which identifies possible faulty regions in a combinational circuit, based on its input/output behavior and independent of a fault model. The new adaptive, statistical approach is named POINTER for 'Partially Overlapping Impact couNTER' and combines a flexible and powerful effect-cause pattern analysis algorithm with high-resolution ATPG. We show the effectiveness of the approach through experiments with benchmark and industrial circuits. In addition, even without additional patterns this analysis method provides good resolution for volume diagnosis, too.
    ftp pdf?

  2. Test Encoding for Extreme Response Compaction
    Michael A. Kochte, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich
    IEEE European Test Symposium (ETS'09), Sevilla, Spain, May 25-29, 2009
    Abstract:
    Optimizing bandwidth by compression and compaction always has to solve the trade-off between input bandwidth reduction and output bandwidth reduction. Recently it has been shown that splitting scan chains into shorter segments and compacting the shift data outputs into a singleparity bit reduces the test response data to one bit per cycle without affecting fault coverage and diagnostic resolution if the compactor's structure is included into the ATPG process.This test data reduction at the output side comes with challenges at the input side. The bandwidth requirement grows due to the increased number of chains and due to a drastically decreased amount of don't care values in the test patterns. The paper at hand presents a new iterative approach to test set encoding which optimizes bandwidth on both input and output side while keeping the diagnostic resolution and fault coverage. Experiments with industrial designs demonstrate that test application time, test data volume and diagnostic resolution are improved at the same time and for most designs testing with a bandwidth of three bits per cycle is possible.
    ftp pdf?

  3. Concurrent Self-Test with Partially Specified Patterns For Low Test Latency and Overhead
    Michael A. Kochte, Christian G. Zoellin, Hans-Joachim Wunderlich
    IEEE European Test Symposium (ETS'09), Sevilla, Spain, May 25-29, 2009
    Abstract:
    Structural on-line self-test may be performed to detect permanent faults and avoid their accumulation. This paper improves concurrent BIST techniques based on a deterministic test set. Here, the test patterns are specially generated with a small number of specified bits. This results in very low test latency, which reduces the likelihood of fault accumulation. Experiments with a large number of circuits show that the hardware overhead is significantly lower than the overhead for previously published methods. Furthermore, the method allows to trade- off fault coverage, test latency and hardware overhead.
    ftp pdf?

  4. Restrict Encoding for Mixed--Mode BIST
    Abdul-Wahid Hakmi, Stefan Holst, Hans-Joachim Wunderlich, Juergen Schloeffel, Friedrich Hapke, Andreas Glowatz
    IEEE VLSI Test Symposium (VTS'09), Santa Cruz, California, USA, May 3-7, 2009
    Abstract:
    Programmable mixed-mode BIST schemes combine pseudo-random pattern testing and deterministic test. This paper presents a synthesis technique for a mixed-mode BIST scheme which is able to exploit the regularities of a deterministic test pattern set for minimizing the hardware overhead and memory requirements. The scheme saves more than 50% hardware costs compared with the best schemes known so far while complete programmability is still preserved.
    ftp pdf?

  5. A Diagnosis Algorithm for Extreme Space Compaction
    Stefan Holst, Hans-Joachim Wunderlich
    Design, Automation and Test in Europe (DATE'09), Nice, France, April 20-24, 2009
    Abstract:
    During volume testing, test application time, test data volume and high performance automatic test equipment (ATE) are the major cost factors. Embedded testing including built-in self-test (BIST) and multi-site testing are quite effective cost reduction techniques which may make diagnosis more complex. This paper presents a test response compaction scheme and a corresponding diagnosis algorithm which are especially suited for BIST and multi-site testing. The experimental results on industrial designs show, that test time and response data volume reduces significantly and the diagnostic resolution even improves with this scheme. A comparison with X-Compact shows, that simple parity information provides higher diagnostic resolution per response data bit than more complex signatures.
    ftp pdf?

  6. Test Exploration and Validation Using Transaction Level Models
    Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Rauf Salimi Khaligh, Martin Radetzki, Hans-Joachim Wunderlich, Stefano Di Carlo, Paolo Prinetto
    Design, Automation and Test in Europe (DATE'09), Nice, France, April 20-24, 2009
    Abstract:
    The complexity of the test infrastructure and test strategies in systems-on-chip approaches the complexity of the functional design space. This paper presents test design space exploration and validation of test strategies and schedules using transaction level models (TLMs). All aspects of the test infrastructure such as test access mechanisms, test wrappers, test data compression and test controllers are modeled at transaction level. Since many aspects of testing involve the transfer of a significant amount of test stimuli and responses, the communication-centric view of TLMs suits this purpose exceptionally well. A case study shows how TLMs can be used to efficiently evaluate DfT decisions in early design steps and how to evaluate test scheduling and resource partitioning during test planning. The presented approach has significantly higher simulation efficiency than RTL and gate level approaches.
    ftp pdf?

  7. Erkennung von transienten Fehlern in Schaltungen mit reduzierter Verlustleistung
    Detection of transient faults in circuits with reduced power dissipation
    M. E. Imhof, H.-J. Wunderlich, C. G. Zoellin
    2. GMM/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE), Ingolstadt, Germany, 29.09. - 01.10.2008, pp. 107-114
    Abstract:
    Für Speicherfelder sind fehlerkorrigiernde Codes die vorherrschende Methode um akzeptable Fehlerraten zu erreichen. In vielen aktuellen Schaltungen erreicht die Zahl der Speicherelemente in freier Logik die Größenordnung der Zahl von SRAM-Zellen vor wenigen Jahren. Zur Reduktion der Verlustleistung wird häufig der Takt der pegelgesteuerten Speicherelemente unterdrückt und die Speicherlemente müssen ihren Zustand über lange Zeitintervalle halten. Die Notwendigkeit der Absicherung der Speicherzellen wird zusätzlich durch die Miniaturisierung verstärkt, die zu einer erhöhten Empfindlichkeit der Speicherelemente geführt hat.
    Dieser Artikel stellt eine Methode zur fehlertoleranten Anordnung von pegelgesteuerten Speicherelementen vor, die bei unterdrücktem Takt Einfachfehler lokalisieren und Mehrfachfehler detektieren kann. Bei aktiviertem Takt können Einfach- und Mehrfachfehler erkannt werden. Die Register können ähnlich wie Prüfpfade effizient in den Entwurfsgang integriert werden. Die Diagnoseinformation kann auf Modulebene leicht berechnet und genutzt werden.

    For memories error correcting codes are the method of choice to guarantee acceptable error rates. In many current designs the number of storage elements in random logic reaches the number of SRAM-cells some years ago. Clock-gating is often employed to reduce the power dissipation of level-sensitive storage elements while the elements have to retain their state over long periods of time. The necessity to protect storage elements is amplified by the miniaturization, which leads to an increased susceptibility of the storage elements.
    This article proposes a method for the fault-tolerant arrangement of level-sensitive storage elements, which can locate single faults and detect multiple faults while being clock-gated. With active clock single and multiple faults can be detected. The registers can be efficiently integrated similar to the scan design flow. The diagnostic information can be easily computed and used at module level.
    ftp pdf?

  8. Zur Zuverlässigkeitsmodellierung von Hardware-Software-Systemen
    On the Reliability Modeling of Hardware-Software-Systems
    M. Kochte, R. Baranowski, H.-J. Wunderlich
    2. GMM/ITG-Fachtagung „Zuverlässigkeit und Entwurf” (ZuE), 29.09 – 01.10.2008, Ingolstadt, Germany
    Abstract:
    Zur Zuverlässigkeitsanalyse von Hardware-Software-Systemen ist ein Systemmodell notwendig, welches sowohl Struktur und Architektur der Hardware als auch die ausgeführte Funktion betrachtet. Wird einer dieser Aspekte des Gesamtsystems vernachlässigt, kann sich eine zu optimische oder zu konservative Schätzung der Zuverlässigkeit ergeben.
    Ein reines Strukturmodell der Hardware erlaubt, den Einfluss von logischer und struktureller Fehlermaskierung auf die Fehlerhäufigkeit der Hardware zu bestimmen. Allerdings kann ein solches Modell nicht die Fehlerhäu- figkeit des Gesamtsystems hinreichend genau schätzen. Die Ausführung der Funktion auf dem System führt zu speziellen Nutzungs- und Kommunikationsmustern der Systemkomponenten, die zu erhöhter oder verminderter Anfälligkeit gegenüber Fehlern führen.
    Diese Arbeit motiviert die Modellierung funktionaler Aspekte zusammen mit der Struktur des Systems. Mittels Fehlerinjektion und Simulation wird der starke Einfluss der Funktion auf die Fehleranfälligkeit des Systems aufgezeigt. Die vorgestellte Methodik, funktionale Aspekte mit in die Zuverlässigkeitsmodellierung einzubinden, verspricht eine realistischere Bewertung von Hardware-Software-Systemen.

    Estimating the reliability of hardware-software systems allows to determine the robustness of design al- ternatives during design exploration. A system model used to derive such a reliability estimate has to incorporate the hardware structure and architecture of the system as well as the performed function. If merely the functional model or the structural model is considered separate from the other one, reliability estimation may be either too optimistic or too conservative.
    While an architectural model allows to determine the impact of logical and architectural fault masking on the design's error rate, it fails to correctly predict the failure rate of the overall system. The function that is performed by the design exhibits particular usage and communication patterns that may--depending on the function--result in increased or reduced susceptibility to faults.
    This work motivates to model functional aspects together with the architecture of the system. Fault injection and simulation show the strong influence of the function on the susceptability of the system. The proposed methodology to incorporate functional aspects into the system model for reliability estimation promises a more accurate assessment of hardware-software systems.

  9. Integrating Scan Design and Soft Error Correction in Low-Power Applications
    M. E. Imhof, H.-J. Wunderlich, C. G. Zoellin
    14th IEEE International On-Line Testing Symposium (IOLTS), Rhodes, Greece, July 7-9, 2008, pp. 59-64
    Abstract:
    Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random logic is in the order of the number of SRAM cells on chips only a few years ago. Often latches are clock gated and have to retain their states during longer periods. Moreover, miniaturization has led to elevated susceptibility of the memory elements and further increases the need for protection.
    This paper presents a fault-tolerant register latch organization that is able t$ single-bit errors while it is clock gated. With active clock, single and multiple errors are detected. The registers can be efficiently integrated simil$ scan design flow, and error detecting or locating information can be collected at module level. The resulting structure can be efficiently reused for offline and general online testing.
    ftp pdf?

  10. Scan Chain Clustering for Test Power Reduction
    Melanie Elm, Michael Imhof, Hans-Joachim Wunderlich, Christian Zoellin, Jens Leenstra, Nicolas Maeding
    45th ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, USA, June 8-13, 2008, pp. 828-833
    Abstract:
    An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-flops into scan chains, which determines how many chains can be deactivated per pattern. In this paper, a new method to cluster flip-flops into scan chains is presented, which minimizes the power consumption during test. The approach does not specify any ordering inside the chains and fits seamlessly to any standard tool for scan chain integration. The application of known test power reduction techniques to the optimized scan chain configurations shows significant improvements for large industrial circuits.
    ftp pdf?

  11. Selective Hardening in Early Design Steps
    Christian G. Zoellin, Hans-Joachim Wunderlich, Ilia Polian, Bernd Becker
    13th IEEE European Test Symposium (ETS), Lago Maggiore, Italy, May 25-29, 2008, pp. 185-190
    Abstract:
    Hardening a circuit against soft errors should be performed in early design steps before the circuit is laid out. A viable approach to achieve soft error rate (SER) reduction at a reasonable cost is to harden only parts of a circuit. When selecting which locations in the circuit to harden, priority should be given to critical spots for which an error is likely to cause a system malfunction. The criticality of the spots depends on parameters not all available in early design steps. We employ a selection strategy which takes only gate-level information into account and does not use any low-level electrical or timing information. We validate the quality of the solution using an accurate SER estimator based on the new UGC particle strike model. Although only partial information is utilized for hardening, the exact validation shows that the susceptibility of a circuit to soft errors is reduced significantly. The results of the hardening strategy presented are also superior to known purely topological strategies in terms of both hardware overhead and protection.
    ftp pdf?

  12. A Framework for Scheduling Parallel DBMS User-Defined Programs on an Attached High-Performance Computer
    M. A. Kochte, R. Natarajan
    ACM International Conference on Computing Frontiers, Ischia, Italy, May 5-7, 2008, pp. 97-104
    Abstract:
    We describe a software framework for deploying, scheduling and executing parallel DBMS user-defined programs on an attached high-performance computer (HPC) platform. This framework is advantageous for many DBMS workloads in the following two aspects. First, the long-running user-defined programs can be speeded up by taking advantage of the greater hardware parallelism available on the attached HPC platform. Second, the interactive response time of the remaining applications on the database server platform is improved by the off-loading of long-running user-defined programs to the attached HPC platform. Our framework provides a new approach for integrating high-performance computing into the workflow of query-oriented, computationally-intensive applications.
    ftp pdf?

  13. Signature Rollback - A Technique for Testing Robust Circuits
    Uranmandakh Amgalan, Christian Hachmann, Sybille Hellebrand, Hans-Joachim Wunderlich
    IEEE VTS'08 (26th VLSI Test Symposium), San Diego, California, USA, Apr 27th to May 1st, 2008, pp. 125-130
    Abstract:
    Dealing with static and dynamic parameter varia- tions has become a major challenge for design and test. To avoid unnecessary yield loss and to ensure reliable system operation a robust design has become mandatory. However, standard structural test proce- dures still address classical fault models and cannot deal with the non-deterministic behavior caused by parameter variations and other reasons. Chips may be rejected, even if the test reveals only non-critical fail- ures that could be compensated during system opera- tion. This paper introduces a scheme for embedded test, which can distinguish critical permanent and non- critical transient failures for circuits with time redun- dancy. To minimize both yield loss and the overall test time, the scheme relies on partitioning the test into shorter sessions. If a faulty signature is observed at the end of a session, a rollback is triggered, and this par- ticular session is repeated. An analytical model for the expected overall test time provides guidelines to deter- mine the optimal parameters of the scheme.
    ftp pdf?

  14. Scan Chain Organization for Embedded Diagnosis
    Melanie Elm, Hans-Joachim Wunderlich
    Design, Automation and Test in Europe (DATE'08), Munich, Germany, March 10-14, 2008, pp. 468-473
    Abstract:
    Keeping diagnostic resolution as high as possible while maximizing the compaction ratio is subject to research since the advent of embedded test. In this paper, we present a novel scan design methodology to maximize diagnostic resolution when compaction is employed. The essential idea is to consider the diagnostic resolution during the clustering of scan elements to scan chains. Our methodology does not depend on a fault model and is helpful with any type of compactor.
    A linear time heuristic is presented to solve the scan chain clustering problem. We evaluate our approach for industrial and academic benchmark circuits.
    It turns out to be superior to both random and to layout driven scan chain clustering. The methodology is applicable to any gate-level design and fits smoothly into an industrial design flow.
    ftp pdf?

  15. Test Set Stripping Limiting the Maximum Number of Specifed Bits
    Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Hans-Joachim Wunderlich
    4th IEEE International Symposium on Electronic Design, Test & Applications (DELTA'08), Hong Kong, January 23-25, 2008, pp. 581-586
    Abstract:
    This paper presents a technique that limits the maximum number of specified bits of any pattern in a given test set. The outlined method uses algorithms similar to ATPG, but exploits the information in the test set to quickly find test patterns with the desired properties. The resulting test sets show a significant reduction in the maximum number of specified bits in the test patterns. Furthermore, results for commercial ATPG test sets show that even the overall number of specified bits is reduced substantially.
    ftp pdf?

  16. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance (Invited Paper)
    S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube
    Informacije MIDEM, Vol. 37, No. 4(124), Ljubljana, December 2007, pp. 212-219
    Abstract:
    The increased number of fabrication defects, spatial and temporal variability of parameters, as well as the growing impact of soft errors in nanoelectronic systems require a paradigm shift in design, verification and test. A robust design becomes mandatory to ensure dependable systems and acceptable yields. Design robustness, however, invalidates many traditional approaches for testing and implies enormous challenges. The RealTest Project addresses these problems for nanoscale CMOS and targets unified design and test strategies to support both a robust design and a coordinated quality assurance after manufacturing and during the lifetime of a system. The paper first gives a short overview of the research activities within the project and then focuses on a first result concerning soft errors in combinational logic. It will be shown that common electrical models for particle strikes in random logic have underestimated the effects on the system behavior. The refined model developed within the RealTest Project predicts about twice as many single events upsets (SEUs) caused by particle strikes as traditional models.

  17. Academic Network for Microelectronic Test Education
    F.Novak, A.Biasizzo, Y.Bertrand, M-L.Flottes, L.Balado, J.Figueras, S.Di Carlo, P.Prinetto, N.Pricopi, H-J.Wunderlich and J-P.van der Hayden
    International Journal of Engineering Education, Volume 23 Number 6 2007, pp. 1245-1253
    Abstract:
    This paper is an overview of the activities performed in the framework of the European IST project EuNICE-Test (European Network for Initial and Continuing Education in VLSI/SOC Testing) using remote automatic test equipment (ATE) ), addressing the shortage of skills in the microelectronics industry in the field of electronic testing. The project was based on the experience of the common test resource centre (CRTC) for French universities. In the framework of the EuNICE-Test project, the existing network expanded to 4 new academic centres: Universitat Politecnica de Catalunya, Spain, Politecnico di Torino, Italy, University of Stuttgart, Germany and Jozef Stefan Institute Ljubljana, Slovenia. Assessments of the results achieved are presented as well as course topics and possible future extensions.
    ftp pdf?

  18. Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip (Invited Paper)
    H.-J. Wunderlich, M. Elm, S. Holst
    43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07), Bled, Slovenia, September 2007, pp. 27-36
    Abstract:
    Rising design complexity and shrinking structures pose new challenges for debug and diagnosis. Finding bugs and defects quickly during the whole life cycle of a product is crucial for time to market, time to volume and improved product quality. Debug of design errors and diagnosis of defects have many common aspects. In this paper we give an overview of state of the art algorithms, which tackle both tasks, and present an adaptive approach to design debug and logic diagnosis.

    Special design for diagnosis is needed to maintain visibility of internal states and diagnosability of deeply embedded cores. This article discusses current approaches to design for diagnosis to support all debug tasks from first silicon to the system level.
    ftp pdf?

  19. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance (Invited Paper)
    S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube
    43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07), Bled, Slovenia, September 2007, pp. 3-10
    Abstract:
    The increased number of fabrication defects, spatial and temporal variability of parameters, as well as the growing impact of soft errors in nanoelectronic systems require a paradigm shift in design, verification and test. A robust design becomes mandatory to ensure dependable systems and acceptable yields. Design robustness, however, invalidates many traditional approaches for testing and implies enormous challenges. The RealTest Project addresses these problems for nanoscale CMOS and targets unified design and test strategies to support both a robust design and a coordinated quality assurance after manufacturing and during the lifetime of a system. The paper first gives a short overview of the research activities within the project and then focuses on a first result concerning soft errors in combinational logic. It will be shown that common electrical models for particle strikes in random logic have underestimated the effects on the system behavior. The refined model developed within the RealTest Project predicts about twice as many single events upsets (SEUs) caused by particle strikes as traditional models.
    ftp pdf?

  20. A Refined Electrical Model for Drift Processes and its Impact on SEU Prediction
    S. Hellebrand, C.G. Zoellin, H.-J. Wunderlich, T. Coym, S. Ludwig, B. Straube
    Proc. of the 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007, pp. 50-58
    Abstract:
    Decreasing feature sizes have led to an increased vulnerability of random logic to soft errors. In combinational logic a particle strike may lead to a glitch at the output of a gate, also referred to as single even transient (SET), which in turn can propagate to a register and cause a single event upset (SEU) there.
    Circuit level modeling and analysis of SETs provides an attractive compromise between computationally expensive simulations at device level and less accurate techniques at higher levels. At the circuit level particle strikes crossing a pn-junction are traditionally modeled with the help of a transient current source. However, the common models assume a constant voltage across the pn-junction, which may lead to inaccurate predictions concerning the shape of expected glitches. To overcome this problem, a refined circuit level model for strikes through pnjunctions is investigated and validated in this paper. The refined model yields significantly different results than common models. This has a considerable impact on SEU prediction, which is confirmed by extensive simulations at gate level. In most cases, the refined, more realistic, model reveals an almost doubled risk of a system failure after an SET.
    ftp pdf? (1000 KB)

  21. Programmable Deterministic Built-in Self-test
    A.-W. Hakmi, H.-J. Wunderlich, C.G. Zoellin, A. Glowatz, F. Hapke, J. Schloeffel, L. Souef
    Proc. of the International Test Conference (ITC), Santa Clara, CA, USA, October 23 - 25, 2007, pp. 1-9.
    Abstract:
    In this paper, we propose a new programmable deterministic Built-In Self-Test (BIST) method that requires significantly lower storage for deterministic patterns than existing programmable methods and provides high flexibility for test engineering in both internal and external test.
    Theoretical analysis suggests that significantly more care bits can be encoded in the seed of a Linear Feedback Shift Register (LFSR), if a limited number of conflicting equations is ignored in the employed linear equation system. The ignored care bits are separately embedded into the LFSR pattern. In contrast to known deterministic BIST schemes based on test set embedding, the embedding logic function is not hardwired. Instead, this information is stored in memory using a special compression and decompression method. Experiments for benchmark circuits and industrial designs demonstrate that the approach has considerably higher overall coding efficiency than the existing methods.
    ftp pdf? (300 KB)

  22. Scan Test Planning for Power Reduction
    M.E. Imhof, C.G. Zöllin, H.-J. Wunderlich, N. Maeding, J. Leenstra
    44th ACM/IEEE Design Automation Conference (DAC), San Diego, Ca, USA, June 4-8, 2007, pp. 521-526
    Abstract:
    Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can be used for reducing the power consumption during test. Here, we present an efficient algorithm for the automated generation of a test plan that keeps fault coverage as well as test time, while significantly reducing the amount of wasted energy. A fault isolation table, which is usually used for diagnosis and debug, is employed to accurately determine scan chains that can be disabled. The algorithm was successfully applied to large industrial circuits and identifies a very large amount of excess pattern shift activity.
    ftp pdf? (700 KB)

  23. Analyzing Test and Repair Times for 2D Integrated Memory Built-In Test and Repair
    P. Öhler, S. Hellebrand, H.-J. Wunderlich
    10th IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems (DDECS), Krakow, Poland, April 11-13, 2007, pp. 185-190
    Abstract:
    An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with spare rows and columns (2D redundancy). To advoid the prohibitive storage requirements for failure bitmaps and the complex data structures inherent in most algorithms for offline repair analysis, existing heuristics for built-in repair analysis (BIRA) either use very simple search strategies or restict the search to smaller local bitmaps. Exact BIRA algorithms work with sub analyzers for each possible repair combination. While a parallel implementation suffers from a high hardware overhead, a serial implementation leads to increased test times. Recently an integrated built-in test and repair approach has been proposed which interleaves test and repair analysis and supports an exact solution with moderate hardware overhead and reasonable test times. The search is based on a depth first traversal of a binary tree, which can be efficiently implemented using a stack of limited size. This algorithm can be realized with different repair strategies guiding the selection of spare rows or columns in each step. In this paper the impact of four different repair strategies on the test and repair time is analyzed.
    ftp pdf? (928 KB)

  24. An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy
    P. Öhler, S. Hellebrand, H.-J. Wunderlich
    12th IEEE European Test Symposium (ETS), Freiburg, Germany, May 21-24, 2007, pp. 91-96
    Abstract:
    An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with spare rows and columns (2D redundancy). Although exact algorithms are available for offline repair analysis, they cannot be directly applied on-chip because of the prohibitive storage requirements for failture bitmaps and the complex data structures inherent in the algorithms. Existing heuristics for built-in repair analysis (BIRA) try to circumvent this problem either by very simple search strategies or by restricting the search to smaller local bitmaps. Exact BIRA algorithms work with sub analyzers for each possible repair combination. While a parallel implementation suffers from a high hardware overhead, a serial implementation leads to high test times. The integrated built-in test and repair approach proposed in this paper interleaves test and repair analysis and supports an exact solution without failure bitmap. The search can be implemented with a stack, which is limited by the number of redundant elements. The basic search procedure is combined with an efficient technique to continuously reduce the problem complexity and keep the test and analysis time low.
    ftp pdf? (701 KB)

  25. Adaptive Debug and Diagnosis without Fault Dictionaries
    S. Holst, H.-J. Wunderlich
    12th IEEE European Test Symposium (ETS), Freiburg, Germany, May 21-24, 2007, pp. 7-12
    Abstract:
    Diagnosis is essential in modern chip production to increase yield, and debug constitutes a major part in the presilicon development process. For recent process technologies, defect mechanisms are increasingly complex, and continuous efforts are made to model these defects by using sophisticated fault models. Traditional static approaches for debug and diagnosis with a simplified fault model are more and more limited.
    In this paper, a method is presented, which identifies possible faulty regions in a combinational circiut, based on its input/output behavior and independent of a fault model. The new adaptive, statistical approach combines a flexible and powerful effect-cause pattern analysis algorithm with high-resolution ATPG. We show the effectiveness of the approach through experiments with benchmark and industrial circuits.
    ftp pdf? (242 KB)

  26. Domänenübergreifende Zuverlässigkeitsbewertung in Frühen Entwicklungsphasen unter Berücksichtigung von Wechselwirkungen
    M. Wedel, P. Göhner, J. Gäng, B. Bertsche, H.-J. Wunderlich, T. Arnaout
    In: 5. Paderborner Workshop "Entwurf mechatronischer Systeme", J. Gausemeier et al.(ed.), Bd. 210, Paderborn, Germany, March 22-23, 2007, pp. 257-272
    Abstract:
    Aufgrund der unvollständigen Informationen über ein mechatronisches System stellt die Frühe Zuverlässigkeitsbewertung eine große Herausforderung dar. Um die jeweiligen Vorteile zu nutzen, wurden klassische Ansätze in den einzelnen Domänen kombiniert und in eine ganzheitliche Methode zur Zuverlässigkeitsbewertung in den Frühen Entwicklungsphasen integriert. In Zusammenarbeit verschiedener Ingenieursdisziplinen wurde die ganzheitliche Methode um die rechnergestützte Ermittlung von Fehlerzusammenhängen im Rahmen einer Risikoabschätzung und verschiedene qualitative Modellierungs- und Analyseansätze erweitert. für die systematische Analyse des wechselseitigen Einflusses der beteiligten Domänen und die Integration in die Zuverlässigkeitsbewertung wurden Wechselwirkungen zwischen den Domänen untersucht und klassifiziert.
    ftp pdf? (314 KB)

  27. Deterministic Logic BIST for Transition Fault Testing
    V. Gherman, H.-J. Wunderlich, J. Schlöffel, M. Garbers
    IET Proceedings on "Computers & Digital Techniques" 1, (3), 2007, pp. 180-186
    Abstract:
    BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applied to stuck-at fault testing. As delay faults have lower random pattern testability than stuck-at faults, the need for DLBIST schemes is increased. Nevertheless, an extension to delay fault testing is not trivial, since this necessitates the application of pattern pairs. Consequently, delay fault testing is expected to require a larger mapping effort and logic overhead than stuck-at fault testing. In this paper, we consider the so-called transition fault model, which is widely used for complexity reasons. We present an extension of a DLBIST scheme for transition fault testing. Functional justification has been used to generate the required pattern pairs. The efficiency of the extended scheme is investigated by using difficult to test industrial designs.
    ftp pdf? (233 KB)

  28. Test und Zuverlässigkeit nanoelektronischer Systeme
    B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich
    Tagung Zuverlässigkeit und Entwurf (ZuD), Munich, Germany, March 26-28, 2007, pp. 139-140
    Abstract:
    Neben der zunehmenden Anfälligkeit gegenüber Fertigungsfehlern bereiten insbesondere vermehrte Parameterschwankungen, zeitabhängige Materialveränderung Störanfälligkeit während des Betriebs massive Probleme bei der Qualitätssicherung für nanoelektronische Systeme. Für eine wirtschaftliche Produktion und einen zuverlässigen Systembetrieb wird einerseits ein robuster Entwurf unabdingbar, andererseits ist damit auch ein Paradigmenwechsel beim Test erforderlich. Anstatt lediglich defektbehaftete Systeme zu erkennen und auszusortieren, muss der Test bestimmen, ob ein System trotz einer gewissen Menge von Fehlern funktionsfähig ist, und die verbleibende Robustheit gegenüber Störungen im Betrieb charakterisieren. Im Rahmen des Projekts RealTest werden einheitliche Entwurfs- und Teststrategien entwickelt, die sowohl einen robusten Entwurf als auch eine darauf abgestimmte Qualitätssicherung unterstützen.
    ftp pdf? (243 KB)

  29. Synthesis of Irregular Combinational Functions with Large Don't Care Sets
    V. Gherman, H.-J. Wunderlich, R.D.- Mascarenas, J.Schloeffel, M. Garbers
    ACM Great Lakes Symposium on VLSI (GLSVLSI), Stresa - Lago Maggiore, Italy, March 11-13, 2007, pp. 287-292
    Abstract:
    A special logic synthesis problem is considered for Boolean functions which have large don't care sets and are irregular. Here, a function ist considered as orregular if the input assignments mapped to specified values ('1'or'0') are randomly spread over the definition space. Such functions can be encounted in the field of design for test. The proposed method uses ordered BDDs for logic manipulations and generates freeBDD-like covers. For the considered benchmark functions, implementations were found with the significant reduction of the node/gate count as compared to SIS or the methodes offered by a state-of-the-art BDD package.
    ftp pdf? (507 KB)

  30. Verlustleistungsoptimierende Testplanung zur Steigerung von Zuverlässigkeit und Ausbeute
    M.E. Imhof, C.G. Zöllin, H.-J. Wunderlich, N. Maeding, J. Leenstra
    Tagung Zuverlässigkeit und Entwurf (ZuD), Munich, Germany, March 26-28, 2007, pp. 69-76
    Abstract:
    Die stark erhöhte durchschnittliche und maximale Verlustleistung während des Tests integrierter Schaltungen kann zu einer Beeinträchtigung der Ausbeute bei der Produktion sowie der Zuverlässigkeit im späteren Betrieb führen. Wir stellen eine Testplanung für Schaltungen mit parallelen Prüfpfaden vor, welche die Verlustleistung während des Tests reduziert. Die Testplanung wird auf ein Überdeckungsproblem abgebildet, das mit einem heuristischen Lösungsverfahren effizient auch für große Schaltungen gelöst werden kann. Die Effizienz des vorgestellten Verfahrens wird sowohl für die bekannten Benchmarkschaltungen als auch für große industrielle Schaltungen demonstriert.
    ftp pdf? (258 KB)

  31. DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme
    B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich
    it - Information Technology, Vol. 48, No. 5, 2006, pp. 304-311
    Abstract:
    Entwurf, Verifikation und Test zuverlässiger nanoelektronischer Systeme erfordern grundlegend neue Methoden und Ansätze. Ein robuster Entwurf wird unabdingbar um Fertigungsfehler, Parameterschwankungen, zeitabhängige Materialveränderungen und vorübergehende Störungen zu tolerieren. Gleichzeitig verlieren gerade dadurch viele traditionelle Testverfahren ihre Aussagekraft. Im Rahmen des Projekts RealTest werden einheitliche Entwurfs- und Teststrategien entwickelt, die sowohl einen robusten Entwurf als auch eine darauf abgestimmte Qualitätssicherung unterstützen. ftp pdf? (496 KB) (Zeitschrift: Information Technology)

  32. BIST Power Reduction Using Scan-Chain Disable in the Cell Processor
    C. Zoellin, H.-J. Wunderlich, N. Maeding, J. Leenstra
    Proc. of the International Test Conference (ITC), Santa Clara, CA, USA, October 24 - 26, 2006, pp. 1-8
    Abstract:
    Built-in self test is a major part of the manufacturing test procedure for the Cell Processor. However, pseudo random patterns cause a high switching activity which is not effectively reduced by standard low power design techniques. If special care is not taken, the scan-speed may have to be reduced significantly, thus extending test time and costs. In this paper, we describe a test power reduction method for logic BIST which uses test scheduling, planning and scan-gating. In LBIST, effective patterns that detect additional faults are very scarce after a few dozens of scan cycles and often less than one pattern in a hundred detects new faults. In most cases, such an effective pattern requires only a reduced set of the available scan chains to detect the fault and all don´t-care scan chains can be disabled, therefore significantly reducing test power. ftp pdf? (507 KB)

  33. Structural-based Power-aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing
    N. Badereddine, P. Girard, S. Pravossoudovitch, C. Landrault, A. Virazel, H.-J. Wunderlich
    Proc. of the IFIP International Conference on Very Large Scale Integration (vlsi-soc), Nice, France, October 16 - 18, 2006, pp. 403-408
    Abstract:
    Scan architectures, though widely used in modern designs for testing purpose, are expensive in power consumption. In this paper, we first discuss the issues of excessive peak power consumption during scan testing. We next show that taking care of high current levels during the test cycle (i.e. between launch and capture) is highly relevant so as to avoid noise phenomena such as irdrop or ground bounce. Then, we propose a solution based on power-aware assignment of don´t care bits in deterministic test patterns that considers structural information of the circuit under test. Experiments have been performed on ISCAS´89 and ITC´99 benchmark circuits with the proposed structural-based power-aware X-Filling technique. These results show that the proposed technique provides the best tradeoff between peak power reduction and increase of test sequence length.
    ftp pdf?

  34. Minimizing Peak Power Consumption during Scan Testing: Test Pattern Modification with X Filling Heuristics
    N. Badereddine, P. Girard, S. Pravossoudovitch, C. Landrault, A. Virazel, H.-J. Wunderlich
    Proc. of the Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS), Tunis, Tunisia, September 5 - 7, 2006, pp. 359-364
    Abstract:
    Scan architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we discuss the issues of excessive peak power consumption during scan testing. We show that taking care of high current levels during the test cycle (i.e. between launch and capture) is highly relevant to avoid noise phenomena such as IR-drop or ground bounce. We propose a solution based on power-aware assignment of don´t care bits in deterministic test patterns. For ISCAS´89 and ITC´99 benchmark circuits, this approach reduces peak power during the test cycle up to 89% compared to a random filling solution.
    ftp pdf?

  35. Deterministic Logic BIST for Transition Fault Testing
    V. Gherman, H.-J. Wunderlich, J. Schlöffel, M. Garbers
    Proc. of the European Test Symposium (ETS), Southampton, UK, May 22 - 25, 2006, pp. 123-128
    Abstract:
    BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applied to stuck-at fault testing. As delay faults have lower random pattern testability than stuck-at faults, the need for DLBIST schemes is increased. Nevertheless, an extension to delay fault testing is not trivial, since this necessitates the application of pattern pairs. Consequently, delay fault testing is expected to require a larger mapping effort and logic overhead than stuck-at fault testing. In this paper, we consider the so-called transition fault model, which is widely used for complexity reasons. We present an extension of a DLBIST scheme for transition fault testing. Functional justification is used to generate the required pattern pairs. The efficiency of the extended scheme is investigated by using industrial benchmark circuits.
    ftp pdf? (148 KB)

  36. X-Masking During Logic BIST and its Impact on Defect Coverage
    Y. Tang, H.-J. Wunderlich, P. Engelke, I. Polian, B. Becker, J. Schlöffel, F. Hapke, M. Wittke
    IEEE Transactions on Very Large Scale Integrated (VLSI) Systems, Vol. 14, No. 2, February 2006, pp. 1-10
    Abstract:
    We present a technique for making a circuit ready for logic built-in self test by masking unknown values at its outputs. In order to keep the silicon area costs low, some known bits in output responses are also allowed to me masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.
    ftp pdf? (817 KB)

  37. Software-Based Self-Test of Processors under Power Constraints
    J. Zhou, H.-J. Wunderlich
    Proc. of the 9th Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, March 06 - 10, 2006, pp. 430-436
    Abstract:
    Software-based self-test (SBST) of processors offers many benefits, such as dispense with expensive test equipments, test execution during maintenance and in the field or initialization tests for the whole system. In this paper, for the first time a structural SBST methodology is proposed which optimizes energy, average power consumption, test length and fault coverage at the same time.
    ftp pdf? (258 KB)

  38. Some Common Aspects of Design Validation, Debug and Diagnosis
    T. Arnaout, G. Bartsch, H.-J. Wunderlich
    Proc. of the 3rd IEEE International Workshop on Electronic Design, Test and Applications (DELTA), Kuala Lumpur, Malaysia, January 17-19, 2006, pp. 3-8
    Abstract:
    Design, Verification and Test of integrated circuits with millions of gates put strong requirements on design time, test volume, test application time, test speed and diagnostic resolution. In this paper, an overview is given on the common aspects of these tasks and how they interact. Diagnosis techniques may be used after manufacturing, for chip characterization and field return analysis, and even for rapid prototyping.
    ftp pdf? (232 KB)

  39. On the Reliability Evaluation of SRAM-based FPGA Designs
    O. Héron, T. Arnaout, H.-J. Wunderlich
    Proc. of the 15th IEEE International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005, pp. 403-408
    Abstract:
    Benefits of Field Programmable Gate Arrays (FPGAs) have lead to a spectrum of use ranging from consumer products to astronautics. This diversity necessitates the need to evaluate the reliability of the FPGA, because of their high susceptibility to soft errors, which are due to the high density of embedded SRAM cells. Reliability evaluation is an important step in designing highly reliable systems, which results in a strong competitive advantage in today's marketplace. This paper proposes a mathematical model able to evaluate and therefore help to improve the reliability of SRAM-based FPGAs.
    ftp pdf? (127 KB)

  40. Development of an Audio Player as System-on-a-Chip using an Open Source Platform
    P. Kiatisevi, L. Azuara, R. Dorsch, H.-J. Wunderlich
    Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, Vol. 3, May 23-26, 2005, pp. 2935-2938
    Abstract:
    Open source software are becoming more widely-used, notably in the server and desktop applications. For embedded systems development, usage of open source software can also reduce development and licensing costs. We report on our experience in developing a Systemon- a-Chip (SoC) audio player using various open source components in both hardware and software parts as well as in the development process. The Ogg Vorbis audio decoder targeted for limited computing resource and low power consumption devices was developed on the free LEON SoC platform, which features SPARC-V8 architecture compatible processor and AMBA bus. The decoder runs on the open source RTEMS operating system making use of the royalty-free open source Vorbis library. We also aim to illustrate the use of hardware/software co-design techniques. Therefore, in order to speed up the decoding process, after an analysis, a computing-intensive part of the decoding algorithm was selected and designed as an AMBA compatible hardware core. The demonstration prototype was built on the XESS XSV-800 prototyping board using GNU/Linux workstations as development workstations. This project shows that development of SoC using open source platform is viable and might be the preferred choice in the future.
    ftp pdf? (131 KB)

  41. From Embedded Test to Embedded Diagnosis
    H.-J. Wunderlich
    Proc. of the 10th IEEE European Test Sypmposium (ETS), Tallinn, Estonia, May 22-25, 2005, pp. 216-221
    Abstract:
    Testing integrated circuits with millions of transistors puts strong requirements on test volume, test application time, test speed, and test resolution. To overcome these challenges, it is widely accepted to partition test resources between the automatic test equipment (ATE) and the circuit under test (CUT). These strategies may reach from simple test data compression/decompression schemes to implementing a complete built-in self-test. Very often these schemes come with reduced diagnostic resolution. In this paper, an overview is given on techniques for embedding test into a circuit while still keeping diagnostic capabilities. Built-in diagnosis techniques may be used after manufacturing, for chip characterization and field return analysis, and even for rapid prototyping.
    ftp pdf? (215 KB)

  42. Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST
    P. Engelke, V. Gherman, I. Polian, Y. Tang, H.-J. Wunderlich, B. Becker
    Proc. of the 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Sopron, Hungary, April 13-16, 2005, pp. 11-18
    Abstract:
    For the first time, we study the coverage of non-target defects for Deterministic Logic BIST (DLBIST) architecture. We consider several DLBIST implementation options that result in test sequences of different lengths. Resistive bridging faults are used as a surrogate of non-target defects. Experimental data obtained for largest ISCAS benchmarks suggests that, although DLBIST always guarantees complete stuck-at coverage, test sequence length does influence the non-target defect detection capabilities. For circuits with a large fraction of random-pattern resistant faults, the embedded deterministic patterns as well as a sufficient amount of random patterns are both demonstrated to be essential for non-target defect detection. It turns out, moreover, that area cost is lower for DLBIST solutions with longer test sequences, due to additional degrees of freedom for the embedding procedure and a lower number of faults undetected by pseudorandom patterns. This implies that DLBIST is particularly effective in covering non-target defects.
    ftp pdf? (91 KB)

  43. Implementing a Scheme for External Deterministic Self-Test
    A. W. Hakmi, V. Gherman, H.-J. Wunderlich, M. Garbers, J. Schlöffel
    Proc. of the 23rd IEEE VLSI Test Sypmposium (VTS), Palm Springs, CA, USA, May 1-5, 2005, pp. 101-106
    Abstract:
    A method for test resource partitioning is introduced which keeps the design-for-test logic test set independent and moves the test pattern dependent information to an external, programmable chip. The scheme includes a new decompression scheme for a fast and efficient communication between the external test chip and the circuit under test. The hardware costs on chip are significantly lower compared with a deterministic BIST scheme while the test application time is still in the same range. The proposed scheme is fully programmable, flexible and can be reused at board level for testing in the field. Keywords: Deterministic self-test, external BIST, test resource partitioning, test data compression.
    ftp pdf? (202 KB)

  44. Frühe Zuverlässigkeitsanalyse mechatronischer Systeme
    P. Jäger, B. Bertsche, T. Arnaout, H.-J. Wunderlich
    Proc. 22. VDI Tagung Technische Zuverlässigkeit, Stuttgart, April 7-8, 2005, pp. 39-56
    Abstract:
    Mechatronische Systeme sind heutzutage allgegenwärtig. Durch die Kombination aus Mechanik und moderner Informationsverarbeitung (Elektronik und Software) kann die Leistungsfähigkeit von Produkten deutlich gesteigert werden. Ein Beispiel hierfür sind CVTGetriebe. Die ersten Getriebe dieser Bauart waren weitgehend mechanisch/hydraulische Strukturen [1]. Modernere CVT-Getriebe, wie das ZF Ecotronic [2] oder das Front-CVT der Mercedes-Benz A-Klasse [3] verfügen über eine elektronische Steuerung, die die Leistungsfähigkeit des Getriebes zu steigern vermag aber auch zu UnZuverlässigkeiten führen kann. In diesem Beitrag soll das Thema der Zuverlässigkeit mechatronischer Systeme aufgegriffen werden und insbesondere vor dem Hintergrund der Zuverlässigkeitsarbeit in Frühen Entwicklungsphasen diskutiert werden, da namentlich die Konzeptphase durch die Auswahl des richtigen Konzeptes für den endgültigen Produkterfolg hauptverantwortlich ist. Hierzu wird speziell das Thema der Informationsgewinnung in Frühen Phasen thematisiert, da der Erfolg der Zuverlässigkeitsarbeit maßgeblich von der Daten- und Informationslage abhängig ist.
    ftp pdf? (240 KB)

  45. X-Masking During Logic BIST and Its Impact on Defect Coverage
    Y. Tang, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, P. Engelke, I. Polian, B. Becker
    Proc. of the 35th IEEE International Test Conference (ITC), Charlotte, NC, USA, October 25-28, 2004, pp. 442-451
    Abstract:
    We present a technique for making a circuit ready for Logic BIST by masking unknown values at its outputs. In order to keep the area overhead low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.
    Keywords: X-Masking, Logic BIST, Defect Coverage,Resistive Bridging Faults
    ftp pdf? (150 KB)

  46. Efficient Pattern Mapping For Deterministic Logic BIST
    V. Gherman, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, M. Garbers
    Proc. of the 35th IEEE International Test Conference (ITC), Charlotte, NC, USA, October 25-28, 2004, pp. 48-56
    Abstract:
    Deterministic logic BIST (DLBIST) is an attractive test strategy, since it combines advantages of deterministic external testing and pseudo-random LBIST. Unfortunately, previously published DLBIST methods are unsuited for large ICs, since computing time and memory consumption of the DLBIST synthesis algorithms increase exponentially, or at least cubically, with the circuit size. In this paper, we propose a novel DLBIST synthesis procedure that has nearly linear complexity in terms of both computing time and memory consumption. The new algorithms are based on binary decision diagrams (BDDs). We demonstrate the efficiency of the new algorithms for industrial designs up to 2M gates.
    Keywords: Logic BIST, BDDs
    ftp pdf? (146 KB)

  47. Reliability Considerations for Mechatronic Systems on the Basis of a State Model
    P. Göhner, E. Zimmer, T. Arnaout, H.-J. Wunderlich
    Proc. of the 17th International Conference on Architecture of Computing Systems (ARCS), Augsburg, Germany, March 23-26, 2004, pp. 106-112
    Abstract:
    The first step in analyzing a problem is to establish a valid model that would represent this problem. The model helps mainly in understanding the problem by depicting it in a visual form. Hence, in order to analyze the reliability of mechatronic systems, we need to understand first how such systems fail and how they behave in the presence of a failure. This understanding would help us later in the analysis and the development of formal solutions to achieve the demanded reliability. This could be achieved using the model that we have developed, which will be presented in this paper.
    ftp pdf? (50 KB)

  48. Impact of Test Point Insertion on Silicon Area and Timing during Layout
    H.Vranken, F. S. Sapei, H.-J. Wunderlich
    Proc. of the 7th Conference on Design, Automation and Test in Europe (DATE), Paris, France, February 16-20, 2004, pp. 810-815
    Abstract:
    This paper presents an experimental investigation on the impact of test point insertion on circuit size and performance. Often test points are inserted into a circuit in order to improve the circuit's testability, which results in smaller test data volume, shorter test time, and higher fault coverage. Inserting test points however requires additional silicon area and influences the timing of a circuit. The paper shows how placement and routing is affected by test point insertion during layout generation. Experimental data for industrial circuits show that inserting 1% test points in general increases the silicon area after layout by less than 0.5% while the performance of the circuit may be reduced by 5% or more.
    ftp pdf? (157 KB)

  49. Test Engineering Education in Europe: the EuNICE-Test Project
    Y. Bertrand, M.-L. Flottes, L. Balado, J. Figueras, A. Biasizzo, F. Novak, S. Di Carlo, P. Prinetto, N. Pricopi,H.-J. Wunderlich
    Proc. of the IEEE International Conference on Microelectronic Systems Education (MSE), Anaheim, CA, June 1-2, 2003, pp. 85-86
    Abstract:
    The paper deals with a European experience of education in industrial test of ICs and SoCs using remote testing facilities. The project addresses the problem of the shortage in microelectronics engineers aware with the new challenge of testing mixed-signal SoCs for multimedia/telecom market. It aims at providing test training facilities at a European scale in both initial and continuing education contexts. This is done by allowing the academic and industrial partners of the consortium to train engineers using the common test resources center (CRTC) hosted by LIRMM (Laboratoire d'Informatique, de Robotique et de Micro-électronique de Montpellier, France). CRTC test tools include up-to-date/high-tech testers that are fully representative of real industrial testers as used on production testfloors. At the end of the project, it is aimed at reaching a cruising speed of about 16 trainees per year per center. Each trainee will have attend at least one one-week training using the remote test facilities of CRTC. ftp pdf? (140 KB)

  50. Adapting a SoC to ATE Concurrent Test Capabilities
    M. Fischer, R. Huerta Rivera, R. Dorsch, H.-J. Wunderlich
    Proc. of the 33rd International Test Conference (ITC), Baltimore, MD, October 8-10, 2002, pp. 1169-1175
    Abstract:
    Concurrent test features are available in the next generation SoC testers to increase ATE throughput. To exploit these new features design modifications are necessary. In a case study, these modifications were applied to the open source Leon SoC platform containing an embedded 32 bit CPU, an AMBA bus, and several embedded cores. The concurrent test of Leon was performed on an SoC tester. The gain in test application time and area costs are quantified and obstacles in the design flow for concurrent test are discussed.
    ftp pdf? (524 KB)

  51. High Defect Coverage with Low Power Test Sequences in a BIST Environment
    Girard, C. Landrault, S. Pravossoudovitch, A. Virazel, H.-J. Wunderlich
    IEEE Design and Test of Computers, Vol. 19, Issue 5, September/October 2002, pp. 44-52
    Abstract:
    A new technique, random single-input change (RSIC) test generation, generates low-power test patterns that provide a high level of defect coverage during low-power BIST of digital circuits. The authors propose a parallel BIST implementation of the RSIC generator and analyze its area-overhead impact.
    ftp pdf? (185 KB)

  52. Efficient On- and Off-Line Testing of Embedded DRAMs
    S. Hellebrand, H.-J. Wunderlich, A. Ivaniuk, Y. Klimets, V. N. Yarmolik
    IEEE Transaction on Computers, Vol. 51, No. 7, July 2002, pp. 801-809
    Abstract:
    This paper presents an integrated approach for both built-in online and offline testing of embedded DRAMs. It is based on a new technique for output data compression which offers the same benefits as signature analysis during offline test, but also supports efficient online consistency checking. The initial fault-free memory contents are compressed to a reference characteristic and compared to test characteristics periodically. The reference characteristic depends on the memory contents, but unlike similar characteristics based on signature analysis, it can be easily updated concurrently with WRITE operations. This way, changes in memory do not require a time consuming recomputation. The respective test characteristics can be efficiently computed during the periodic refresh operations of the dynamic RAM. Experiments show that the proposed technique significantly reduces the time between the occurrence of an error and its detection (error detection latency). Compared to error detecting codes (EDC) it also achieves a significantly higher error coverage at lower hardware costs. Therefore, it perfectly complements standard online checking approaches relying on EDC, where the concurrent detection of certain types of errors is guaranteed, but only during READ operations accessing the erroneous data.
    ftp pdf? (662 KB)

  53. Combining Deterministic Logic BIST with Test Point Insertion
    H. Vranken, F. Meister, H.-J. Wunderlich
    Proc. of the 7th European Test Workshop (ETW), Korfu, Greece, May 26-29, 2002, pp. 389-394
    Abstract:
    This paper presents a logic BIST approach which combines deterministic logic BIST with test point insertion. Test points are inserted to obtain a first testability improvement, and next a deterministic pattern generator is added to increase the fault efficiency up to 100%. The silicon cell area for the combined approach is smaller than for approaches that apply a deterministic pattern generator or test points only. The combined approach also removes the classical limitations and drawbacks of test point insertion, such as failing to achieve complete fault coverage and a complicated design flow. The benefits of the combined approach are demonstrated in experimental results on a large number of ISCAS and industrial circuits.
    ftp pdf? (128 KB)

  54. RESPIN++ - Deterministic Embedded Test
    L. Schäfer, R. Dorsch, H.-J. Wunderlich
    Proc. of the 7th European Test Workshop (ETW), Korfu, Greece, May 26-29, 2002, pp. 139-146
    Abstract:
    RESPIN++ is a deterministic embedded test method tailored to system chips, which implement scan test at core level. The scan chains of one core of the system-on-a-chip are reused to decompress the patterns for another core. To implement the RESPIN++ test architecture only a few gates need to be added to the test wrapper. This will not affect the critical paths of the system. The RESPIN++ method reduces both test data volume and test application time up to one order of magnitude per core compared to storing compacted test patterns on the ATE. If several cores may be tested concurrently, test data volume and test application time for the complete system test may be reduced even further. This paper presents the RESPIN++ test architecture and a compression algorithm for the architecture.
    ftp pdf? (87 KB)

  55. Reusing Scan Chains for Test Pattern Decompression
    R. Dorsch and H.-J. Wunderlich
    Journal of Electronic Testing - Theory and Applications (JETTA), Vol. 18, No. 2, April 2002, pp. 231-240
    Abstract:
    The paper presents a method for testing a system-on-a-chip by using a compressed representation of the patterns on an external tester. The patterns for a certain core under test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper, while the mission logic is untouched. Storage and bandwidth requirements for the ATE are reduced significantly. ftp pdf?

  56. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
    H.-G. Liang, S. Hellebrand, H.-J. Wunderlich
    Journal of Electronic Testing - Theory and Applications (JETTA), Vol. 18, No. 2, April, 2002, pp. 157-168
    Abstract:
    In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional compression scheme, which combines the advantages of known vertical and hoizontal compression techniques. To reduce both the number of patterns to be stored and the number of bits to be stored for each pattern, deterministic test cubes are encoded as seeds of an LFSR (horizontal compression), and the seeds are again compressed into seeds of a folding counter sequence (vertical compression). The proposed BIST architecture is fully compatible with standard scan esign, simple and flexible, so that sharing between several logic cores is p0ossible. Experimental results show that the proposed scheme requires less test data storage than previously published approaches providing the same flexibility and scan compatibility.
    ftp pdf? (152 KB)

  57. Application of deterministic logic BIST on industrial circuits
    G. Kiefer and H. Vranken and E.-J. Marinissen and H.-J. Wunderlich
    Journal of Electronic Testing - Theory and Applications (JETTA), Vol. 17, No. 3, June 2001, pp. 351-362
    Abstract:
    We present the application of a deterministic logic BIST scheme based on bit-flipping on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5% - 15%. It is demonstrated that a trade-off is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized. ftp pdf?

  58. On applying the set covering model to reseeding
    S. Chiusano and S. di Carlo and P. Prinetto and H. Wunderlich
    Proceedings of the conference on Design, automation and test in Europe (DATE01), 2001, pp. 156-161
    Abstract:
    The Functional BIST approach is a rather new BIST technique based on exploiting embedded system functionality to generate deterministic test patterns during BIST. The approach takes advantages of two well-known testing techniques, the arithmetic BIST approach and the reseeding method. The main contribution of the present paper consists in formulating the problem of an optimal reseeding computation as an instance of the set covering problem. The proposed approach guarantees high flexibility, is applicable to different functional modules, and, in general, provides a more efficient test set encoding then previous techniques. In addition, the approach shorts the computation time and allows to better exploiting the trade- off between area overhead and global test length as well as to deal with larger circuits. ftp pdf? (79 KB)

  59. Using a Hierarchical DfT Methodology in High Frequency Processor Designs for Improved Delay Fault Testability
    M. Kessler, G. Kiefer, J. Leenstra, K. Schünemann, T. Schwarz and H.-J. Wunderlich
    Proc. of the 32nd IEEE International Test Conference (ITC), Baltimore, MD, October 30-November 1, 2001, pp. 461-469
    Abstract:
    In this paper a novel hierarchical DfT methodology is presented which is targeted to improve the delay fault testability for external testing and scan-based BIST. After the partitioning of the design into high frequency macros, the analysis for delay fault testability already starts in parallel with the implementation at the macro level. A specification is generated for each macro that defines the delay fault testing characteristics at the macro boundaries. This specification is used to analyse and improve the delay fault testability by improving the scan chain ordering at macro-level before the macros are connected together into the total chip network. The hierarchical methodology has been evaluated with the instruction window buffer core of an out-of-order processor. It was shown that for this design practically no extra hardware is required.
    ftp pdf? (168 KB)

  60. Tailoring ATPG for Embedded Testing
    R. Dorsch, H.-J. Wunderlich
    Proc. of the 32nd IEEE International Test Conference (ITC), Baltimore, MD, October 30-November 1, 2001, pp. 530-537
    Abstract:
    An automatic test pattern generation (ATPG) method is presented Testability for a scan-based test architecture which min-imizes ATE storage requirements and reduces the bandwidth be-tween the automatic test equipment (ATE) and the chip under test. To generate tailored deterministic test patterns, a standard ATPG tool performing dynamic compaction and allowing constraints on circuit inputs is used. The combination of an appropriate test ar-chitecture and the tailored test patterns reduces the test data vol-ume up to two orders of magnitude compared with standard com-pacted test sets.
    ftp pdf? (117 KB)

  61. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
    H.-G. Liang, S. Hellebrand, H.-J. Wunderlich
    Proc. of the 32nd IEEE International Test Conference (ITC), Baltimore, MD, October 30-November 1, 2001, pp. 894-902
    Abstract:
    In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional compression scheme, which combines the advantages of known vertical and hoizontal compression techniques. To reduce both the number of patterns to be stored and the number of bits to be stored for each pattern, deterministic test cubes are encoded as seeds of an LFSR (horizontal compression), and the seeds are again compressed into seeds of a folding counter sequence (vertical compression). The proposed BIST architecture is fully compatible with standard scan esign, simple and flexible, so that sharing between several logic cores is p0ossible. Experimental results show that the proposed scheme requires less test data storage than previously published approaches providing the same flexibility and scan compatibility.
    ftp pdf? (152 KB)

  62. Reusing Scan Chains for Test Pattern Decompression
    R. Dorsch, H.-J. Wunderlich
    Proc. of the 6th European Test Workshop (ETW), Stockholm, Sweden, May 29-June 1, 2001, pp. 124-132
    Abstract:
    The paper presents a method for testing a system-on-a-chip by using a compressed representation of the patterns on an external tester. The patterns for a certain core under test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper, while the mission logic is untouched. Storage and bandwidth requirements for the ATE are reduced significantly.
    ftp pdf? (126 KB)

  63. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
    S. Hellebrand, H-G Liang, H.-J. Wunderlich
    Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 17, No. 3/4, June/August 2001, pp. 341-349
    Abstract:
    In this paper a new scheme for deterministic and mixed mode scan-based BIST is presented. It relies on a new type of test pattern generator which resembles a programmable Johnson counter and is called folding counter. Both the theoretical background and practical algorithms are presented to characterize a set of deterministic test cubes by a reasonably small number of seeds for a folding counter. Combined with classical techniques for test width compression and with pseudo-random pattern generation these new techniques provide an efficient and flexible solution for scan-based BIST.. Experimental results show that the proposed scheme outperforms previously published approaches based on the reseeding of LFSRs or Johnson counters.
    ftp pdf? (57 KB)

  64. A Modified Clock Scheme for a Low Power BIST Test Pattern Generator
    P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, H.-J. Wunderlich
    Proc. of the 19th VLSI Test Symposium (VTS), Marina Del Rey, CA, April 29-May 3, 2001, pp. 306-311
    Abstract:
    In this paper, we present a new low power BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation. The proposed low power/energy BIST technique is based on a modified clock scheme for the TPG and the clock tree feeding the TPG. Numerous advantages can be found in applying such a technique. The fault coverage and the test time are roughly the same as those achieved using a standard BIST scheme. The area overhead is nearly negligible and there is no penalty on the circuit delay. The proposed BIST scheme does not require any circuit design modification beyond the parallel BIST technique, is easily implemented and has low impact on the design time. It has been implemented based on an LFSR-based TPG, but can also be designed using a cellular automata. Reductions of the energy, average power and peak power consumption during test operation are up to 94%, 55% and 48% respectively for ISCAS and MCNC benchmark circuits.
    ftp pdf? (126 KB)

  65. Circuit Partitioning for Efficient Logic BIST Synthesis
    A. Irion, G. Kiefer, H. Vranken, H.-J. Wunderlich
    Proc. of the 4th Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, March 12-16, 2001, pp. 86-91
    Abstract:
    A divide-and-conquer approach using circuit partitioning is presented, which can be used to accelerate logic BIST synthesis procedures. Many BIST synthesis algorithms contain steps with a time complexity which increases more than linearly with the circuit size. By extracting sub-circuits which are almost constant in size, BIST synthesis for very large designs may be possible within linear time. The partitioning approach does not require any physical modifications of the circuit under test. Experiments show that significant performance improvements can be obtained at the cost of a longer test application time or a slight increase in silicon area for the BIST hardware.
    ftp pdf? (255 KB)

  66. Minimized Power Consumption for Scan-Based BIST
    S. Gerstendörfer, H.-J. Wunderlich
    Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 16, No. 3, June 2000, pp. 203-212
    Abstract:
    Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture are analyzed, the modules and modes with the highest power consumption are identified, and design modifications to reduce power consumption are proposed. The design modifications include some gating logic for masking the scan path activity during shifting, and the synthesis of additional logic for suppressing random patterns which do not contribute to increase the fault coverage. These design changes reduce power consumption during BIST by several orders of magnitude, at very low cost in terms of area and performance. ftp pdf? (72 KB)

  67. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
    S. Hellebrand, H-G Liang, H.-J. Wunderlich
    Proc. of the 31st IEEE International Test Conference (ITC), Atlantic City, NJ, October 3-5, 2000, pp. 778-784
    Abstract:
    In this paper a new scheme for deterministic and mixed mode scan-based BIST is presented. It relies on a new type of test pattern generator which resembles a programmable Johnson counter and is called folding counter. Both the theoretical background and practical algorithms are presented to characterize a set of deterministic test cubes by a reasonably small number of seeds for a folding counter. Combined with classical techniques for test width compression and with pseudo-random pattern generation these new techniques provide an efficient and flexible solution for scan-based BIST.. Experimental results show that the proposed scheme outperforms previously published approaches based on the reseeding of LFSRs or Johnson counters.
    ftp pdf? (57 KB)

  68. Non-Intrusive BIST for Systems-on-a-Chip
    S. Chiusano, P. Prinetto, H.-J. Wunderlich
    Proc. of the 31st IEEE International Test Conference (ITC), Atlantic City, NJ, October 3-5, 2000, pp. 644-651
    Abstract:
    The term functional BIST describes a test method to control functional modules so that they generate a deterministic test set, which targets structural faults within other parts of the system. It is a promising solution for self-testing complex digital systems at reduced costs in terms of area overhead and performance degradation. While previous work mainly investigated the use of functional modules for generating pseudo-random and pseudo-exhaustive test patterns, the present paper shows that a variety of modules can also be used as a deterministic test pattern generator via an appropriate reseeding strategy. This method enables a BIST technique that does not introduce additional hardware like test points and test registers into combinational and pipelined modules under test. The experimental results prove that the reseeding method works for accumulator based structures, multipliers, or encryption modules as efficiently as for the classic linear feedback shift registers, and some times even better.
    ftp pdf? (104 KB)

  69. Application of Deterministic Logic BIST on Industrial Circuits
    G. Kiefer, H. Vranken, E. J. Marinissen, H.-J. Wunderlich
    Proc. of the 31st IEEE International Test Conference (ITC), Atlantic City, NJ, October 3-5, 2000, pp. 105-114
    Abstract:
    We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5%-15%. It is demonstrated that a trade-off is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized.
    ftp pdf? (119 KB)

  70. Optimal Hardware Pattern Generation for Functional BIST
    S. Cataldo, S. Chiusano, P. Prinetto, H.-J. Wunderlich
    Proc. of the 3rd Conference on Design and Test in Europe (DATE), Paris, France, March 27-30, 2000, pp. 292-297
    Abstract:
    Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses the computation of optimal seeds for an arbitrary sequential module to be used as hardware test pattern generator. Up to now, only linear feedback shift registers and accumulator based structures have been used for deterministic test pattern generation by reseeding. In this paper, a method is proposed which can be applied to general finite state machines. Nevertheless the method is absolutely general, for sake of comparison with previous approaches, in this paper an accumulator based unit is assumed as pattern generator module. Experiments prove the effectiveness of the approach which outperforms previous results for accumulators, in terms of test size and test time, without sacrifying the fault detection capability.
    ftp pdf? (89 KB)

  71. Deterministic BIST with Partial Scan
    G. Kiefer, H.-J. Wunderlich
    Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 16, No. 3, June 2000, pp. 169-177
    Abstract:
    An efficient deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum number of flipflops to be scannable so that the remaining circuit has a pipeline-like structure. Experiments show that scanning less flipflops may even decrease the hardware overhead for the on-chip pattern generator besides the classical advantages of partial scan such as less impact on the system performance and less hardware overhead.
    ftp pdf? (133 KB)

  72. Minimized Power Consumption for Scan-Based BIST
    S. Gerstendörfer, H.-J. Wunderlich
    Proc. of the 30th IEEE International Test Conference (ITC), Atlantic City, NJ, September 28-30, 1999, pp. 77-84
    Abstract:
    Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture are analyzed, the modules and modes with the highest power consumption are identified, and design modifications to reduce power consumption are proposed. The design modifications include some gating logic for masking the scan path activity during shifting, and the synthesis of additional logic for suppressing random patterns which do not contribute to increase the fault coverage. These design changes reduce power consumption during BIST by several orders of magnitude, at very low cost in terms of area and performance. ftp pdf? (72 KB)

  73. Transparent Word-oriented Memory BIST Based on Symmetric March Algorithms
    V. N. Yarmolik, I. V. Bykov, S. Hellebrand, H.-J. Wunderlich
    Proc. of the 3rd European Dependable Computing Conference (EDCC), Prague, Czech Republic, September 15-17, 1999, pp. 339-350
    Abstract:
    The paper presents a new approach to transparent BIST for word-oriented RAMs which is based on the transformation of March transparent test algorithms to the symmetric versions. This approach allows to skip the signature prediction phase inherent to conventional transparent memory testing and therefore to significantly reduce test time. The hardware overhead and fault coverage of the new BIST scheme are comparable to the conventional transparent BIST structures. Experimental results show that in many cases the proposed test techniques achieve a higher fault coverage in shorter test time.
    ftp pdf? (126 KB)

  74. Deterministic BIST with Partial Scan
    G. Kiefer, H.-J. Wunderlich
    Proc. of the 4th IEEE European Test Workshop (ETW), Constance, May 25-28, 1999 , pp. 110-117
    Abstract:
    An efficient deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum number of flipflops to be scannable so that the remaining circuit has a pipeline-like structure. Experiments show that scanning less flipflops may even decrease the hardware overhead for the on-chip pattern generator besides the classical advantages of partial scan such as less impact on the system performance and less hardware overhead.
    ftp pdf? (133 KB)

  75. Error Detecting Refreshment for Embedded DRAMs
    S. Hellebrand, H.-J. Wunderlich, A. Ivaniuk, Y. Klimets, V. N. Yarmolik
    Proc. of the 17th IEEE VLSI Test Symposium (VTS), Dana Point, CA, April 25-29, 1999, pp. 384-390
    Abstract:
    This paper presents a new technique for on-line consistency checking of embedded DRAMs. The basic idea is to use the refresh cycle for concurrently computing a test characteristic of the memory contents and compare it to a precomputed reference characteristic. Experiments show that the proposed technique significantly reduces the time between the occurrence of an error and its detection (error detection latency). It also achieves a very high error coverage at low hardware costs. Therefore it perfectly complements standard on-line checking approaches relying on error detecting codes, where the detection of certain types of errors is guaranteed, but only during READ operations accessing the erroneous data.
    ftp pdf? (58 KB)

  76. Symmetric Transparent BIST for RAMs
    V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich
    Proc. of the 2nd Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, March 9-12, 1999, pp. 702-708
    Abstract:
    The paper introduces the new concept of symmetric transparent BIST for RAMs. This concept allows to skip the signature prediction phase of conventional transparent BIST approaches and therefore yields a significant reduction of test time. The hardware cost and the fault coverage of the new scheme remain comparable to that of a traditional transparent BIST scheme. In many cases, experimental studies even show a higher fault coverage obtained in shorter test time.
    ftp pdf? (59 KB)

  77. Deterministic BIST with Multiple Scan Chains
    G. Kiefer, H.-J. Wunderlich
    Journal of Electronic Testing: Theory and Applications (JETTA), Volume 14, Numbers 1-2, February 1999, pp. 85-93
    Abstract:
    A deterministic BIST scheme for circuits with multiple scan paths is presented. A procedure is described for synthesizing a pattern generator which stimulates all scan chains simultaneously and guarantees complete fault coverage.
    The new scheme may require less chip area than a classical LFSR-based approach while better or even complete fault coverage is obtained at the same time.
    ftp pdf? (248 KB)

  78. Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST
    M. Karkala, N. A. Touba, H.-J. Wunderlich
    Proc. of the 7th Asian Test Symposium (ATS), Singapore, December 2-4, 1998, pp. 492-499
    Abstract:
    In mixed-mode BIST, deterministic test patterns are generated with on-chip hardware to detect the random-pattern-resistant (r.p.r.) faults that are missed by the pseudo-random patterns. While previous work in mixed-mode BIST has focussed on developing hardware schemes for more efficiently encoding a given set of deterministic patterns (generated by a conventional ATPG procedure), the approach taken in this paper is to improve the encoding efficiency (and hence reduce hardware overhead) by specially selecting a set of deterministic patterns for the r.p.r. faults that can be efficiently encoded. A special ATPG procedure is described for finding test patterns for the r.p.r. faults that are correlated (have the same logic value) in many bit positions. Such test patterns can be efficiently encoded with one of the many "bit-fixing" schemes that have been described in the literature. Results are shown for different bit-fixing schemes which indicate dramatic reductions in BIST overhead can be achieved by using the proposed ATPG procedure to select which test patterns to encode.
    ftp pdf? (76 KB)

  79. BIST for Systems-on-a-Chip
    H.-J. Wunderlich
    INTEGRATION - The VLSI Journal, December 1998, pp. 55-78
    Abstract:
    An increasing part of microelectronic systems is implemented on the basis of predesigned and preverified modules, so-called cores, which are reused in many instances. Core-providers offer RISC-kernels, embedded memories, DSPs, and many other functions, and built-in self-test ist the appropriate method for testing complex systems composed of different cores
    In this paper, we overview BIST methods for different types of cores and present advanced BIST solutions. Special emphasis is put on deterministic BIST methods as they do not require any modifications of the core under test and help to protect intellectual property (IP).
    ftp pdf? (457 KB)

  80. New Transparent RAM BIST Based on Self-Adjusting Output Data Compression
    V. N. Yarmolik, Y. Klimets, S. Hellebrand, H.-J. Wunderlich
    Proc. of Design & Diagnostics of Electronic Circuits & Systems (DDECS), Szczyrk, Poland, September 1998, pp. 27-33
    Abstract:
    After write operations, BIST schemes for RAMs relying on signature analysis must compress the entire memory contents to update the reference signature. This paper introduces a new scheme for output data compression which avoids this overhead while retaining the benefits of signature analysis. The proposed technique is based on a new memory characteristic derived as the modulo-2 sum of all addresses pointing to non-zero cells. This characteristic can be adjusted concurrently with write operations by simple EXOR-operations on the initial characteristic and on the addresses affected by the change.
    ftp pdf? (62 KB)

  81. Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications
    S. Hellebrand, H.-J. Wunderlich, A. Hertwig
    IEEE Design and Test, Vol. 15, No. 4, October-December 1998, pp. 36-41
    Abstract:
    A target structure for implementing fast on-line testable control units for data-dominated applications is presented. In many cases, the proposed controller structure leads to a performance improvement of more than 30% for a standard benchmark set whereas the area overhead is less than 15% compared with conventional on-line testable finite state machines (FSM). The proposed approach is compatible with the state-of-the-art methods for FSM decomposition, state encoding and logic synthesis.
    ftp pdf? (29 KB)

  82. Deterministic BIST with Multiple Scan Chains
    G. Kiefer, H.-J. Wunderlich
    Proc. of the 29th IEEE International Test Conference (ITC), Washington, DC, October 1998, pp. 1057-1064
    Abstract:
    A deterministic BIST scheme for circuits with multiple scan paths is presented. A procedure is described for synthesizing a pattern generator which stimulates all scan chains simultaneously and guarantees complete fault coverage.
    The new scheme may require less chip area than a classical LFSR-based approach while better or even complete fault coverage is obtained at the same time.
    ftp pdf? (248 KB)

  83. Accumulator Based Deterministic BIST
    R. Dorsch, H.-J. Wunderlich
    Proc. of the 29th IEEE International Test Conference (ITC), Washington, DC, October 1998, pp. 412-421
    Abstract:
    Most built-in self test (BIST) solutions require specialized test pattern generation hardware which may introduce significant area overhead and performance degradation. Recently, some authors proposed test pattern generation on chip by means of functional units also used in system mode like adders or multipliers. These schemes generate pseudo-random or pseudo-exhaustive patterns for serial or parallel BIST. If the circuit under test contains random pattern resistant faults a deterministic test pattern generator is necessary to obtain complete fault coverage.
    In this paper it is shown that a deterministic test set can be encoded as initial values of an accumulator based structure, and all testable faults can be detected within a given test length by carefully selecting the seeds of the accumulator. A ROM is added for storing the seeds, and the control logic of the accumulator is modified. In most cases the size of the ROM is less than the size required by traditional LFSR-based reseeding approaches.
    ftp pdf? (137 KB)

  84. Hardware-Optimal Test Register Insertion
    A. P. Stroele, H.-J. Wunderlich
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 6, June 1998, pp. 531-540
    Abstract:
    Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults and test application time. Such a scheme is implemented by test registers, for instance BILBOs or CBILBOs, which are inserted into the circuit structure at appropriate places. An algorithm is presented which is able to find the cost optimal placement of test registers for nearly all the ISCAS'89 sequential benchmark circuits, and a suboptimal solution with slightly higher costs is obtained for all the circuits within a few minutes of computing time. The algorithm can also be applied to the Minimum Feedback Vertex Set problem in partial scan desing, and an optimal solution is found for all the benchmark circuits.
    The proveably optimal solutions for the benchmark circuits mainly use CBILBOs which can simultaneously generate test patterns and compact test responses. Hence, test scheduling is not required, test control is simplified, and test application time is reduced.
    ftp pdf? (125 KB)

  85. Fast Self-Recovering Controllers
    A. Hertwig, S. Hellebrand, H.-J. Wunderlich
    Proc. of the 16th IEEE VLSI Test Symposium (VTS), Monterey, CA, April 1998, pp. 296-302
    Abstract:
    A fast fault-tolerant controller structure is presented, which is capable of recovering from transient faults by performing a rollback operation in hardware.
    The proposed fault-tolerant controller structure utilizes the rollback hardware also for system mode and this way achieves performance improvements of more than 50% compared to controller structures made fault-tolerant by conventional techniques, while the hardware overhead is often negligible. The proposed approach is compatible with state-of-the-art methods for FSM decomposition, state encoding and logic synthesis.
    ftp pdf? (36 KB)

  86. Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs
    V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich
    Proc. of the 1st Conference on Design, Automation and Test in Europe (DATE), Paris, France,February 1998, pp. 173-179
    Abstract:
    After write operations, BIST schemes for RAMs relying on signature analysis must compress the entire memory contents to update the reference signature. This paper introduces a new scheme for output data compression which avoids this overhead while retaining the benefits of signature analysis. The proposed technique is based on a new memory characteristic derived as the modulo-2 sum of all addresses pointing to non-zero cells. This characteristic can be adjusted concurrently with write operations by simple EXOR-operations on the initial characteristic and on the addresses affected by the change.
    ftp pdf? (50 KB)

  87. Mixed-Mode BIST Using Embedded Processors
    S. Hellebrand, H.-J. Wunderlich, A. Hertwig
    Journal of Electronic Testing Theory and Applications (JETTA), Vol. 12, Nos. 1/2, February/April 1998, pp. 127-138
    Abstract:
    In complex systems, embedded processors may be used to run software for test pattern generation and response evaluation. For system components which are not completely random pattern testable, the test programs have to generate deterministic patterns after random testing. Usually the random test part of the program requires long run times whereas the part for deterministic testing has high memory requirements.
    In this paper it is shown that an appropriate selection of the random pattern test method can significantly reduce the memory requirements of the deterministic part. A new, highly efficient scheme for software-based random pattern testing is proposed, and it is shown how to extend the scheme for deterministic test pattern generation. The entire test scheme may also be used for implementing a scan based BIST in hardware.
    ftp pdf? (1039 KB)

  88. Using BIST Control for Pattern Generation
    G. Kiefer, H.-J. Wunderlich
    Proc. of the 28th IEEE International Test Conference (ITC), Washington, DC, November 1997, pp. 347-355
    Abstract:
    A deterministic BIST scheme is presented which requires less hardware overhead than pseudo-random BIST but obtains better or even complete fault coverage at the same time. It takes advantage of the fact that any autonomous BIST scheme needs a BIST control unit for indicating the completion of the self-test at least.
    Hence, pattern counters and bit counters are always available, and they provide information to be used for deterministic pattern generation by some additional circuitry. This paper presents a systematic way for synthesizing a pattern generator which needs less area than a 32-bit LFSR for random pattern generation for all the benchmark circuits.
    ftp pdf? (326 KB)

  89. STARBIST: Scan Autocorrelated Random Pattern Generation
    K.-H. Tsai, S. Hellebrand, J. Rajski, M. Marek Sadowska
    Proc. of the ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, June 1997, pp. 472-478
    Abstract:
    Traditionally, two types of approaches have been used to address the problem of pseudo-random pattern resistant faults: modification of the mission logic through test point insertion and smart pattern generators based on reseeding, mapping techniques or weighted random patterns. The former technique impacts the design, the latter usually requires test data to store or additional circuitry. To avoid these disadvantages a new scan-based BIST scheme is presented which uses scan order and polarity in scan synthesis, effectively converting the scan chain into a ROM capable of storing some "center" patterns from which the others vectors are derived by randomly complementing some of their coordinates. Experimental results demonstrate that a very high fault coverage can be obtained without any modification of the mission logic, no test data to store and very simple BIST hardware which does not depend on the size of the circuit.
    ftp pdf? (52 KB)

  90. Fast Controllers for Data Dominated Applications
    A. Hertwig, H.-J. Wunderlich
    Proc. of the European Design & Test Conference (ED&TC), Paris, France, March 1997, pp. 84-89
    Abstract:
    A target structure for implementing fast edge-triggered control units is presented. In many cases, the proposed controller is faster than a one-hot encoded structure as its correct timing does not require master-slave flip-flops even in the presence of unpredictable clocking skews. A synthesis procedure is proposed which leads to a performance improvement of 40% on average for the standard benchmark set whereas the additional area is less than 25% compared with conventional finite state machine (FSM) synthesis. The proposed approach is compatible with the state-of-the-art methods for FSM decomposition, state encoding and logic synthesis.
    ftp pdf? (38 KB)

  91. Bit-Flipping BIST
    H.-J. Wunderlich, G. Kiefer
    Proc. of the ACM/IEEE International Conference on CAD-96 (ICCAD), San Jose, CA, November 1996, pp. 337-343
    Abstract:
    A scan-based BIST scheme is presented which guarantees complete fault coverage with very low hardware overhead. A probabilistic analysis shows that the output of an LFSR which feeds a scan path has to be modified only at a few bits in order to transform the random patterns into a complete test set. These modifications may be implemented by a bit-flipping function which has the LFSR-state as an input, and flips the value shifted into the scan path at certain times. A procedure is described for synthesizing the additional bit-flipping circuitry, and the experimental results indicate that this mixed-mode BIST scheme requires less hardware for complete fault coverage than all the other scan-based BIST approaches published so far.
    ftp pdf? (48 KB)

  92. Mixed-Mode BIST Using Embedded Processors
    S. Hellebrand, H.-J. Wunderlich, A. Hertwig
    Proc. of the 27th IEEE International Test Conference (ITC), Washington, DC, October 1996, pp. 195-204
    Abstract:
    In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not completely random pattern testable, the test programs have to generate deterministic patterns after random testing. Usually the random test part of the program requires long run times whereas the part for deterministic testing has high memory requirements.
    In this paper it is shown that an appropriate selection of the random pattern test method can significantly reduce the memory requirements of the deterministic part. A new, highly efficient scheme for software-based random pattern testing is proposed, and it is shown how to extend the scheme for deterministic test pattern generation. The entire test scheme may also be used for implementing a scan based BIST in hardware.
    ftp pdf? (91 KB)

  93. Deterministic Pattern Generation for Weighted Random Pattern Testing
    B. Reeb, H.-J. Wunderlich
    Proc. of the European Design & Test Conference (ED&TC), Paris, France, March 1996, pp. 30-36
    Abstract:
    Weighted random pattern testing is now widely accepted as a very economic way for external testing as well as for implementing a built-in self-test (BIST) scheme. The weights may be computed either by structural analysis or by extracting the required information from a precomputed deterministic test set. In this paper, we present a method for generating deterministic test patterns which can easily be transformed into weight sets. These test patterns contain only minimal redundant information such that the weigth generation process is not biased, and the patterns are grouped such that the conflicts with a group are minimized. The quality of the weight sets obtained this way is superior to the approaches published so far with respect to a small number of weigths and weighted patterns, and a complete fault coverage for all the ISCAS-85 and ISCAS-89 benchmark circuits.
    ftp pdf? (705 KB)

  94. Pattern Generation for a Deterministic BIST Scheme
    S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich
    Proc. of the ACM/IEEE International Conference on CAD-95 (ICCAD), San Jose, CA, November 1995, pp. 88-94
    Abstract:
    Recently a deterministic built-in self-test scheme has been presented based on reseeding of multiple-polynomial linear feedback shift registers. This scheme encodes deterministic test sets at distinctly lower costs than previously known approaches. In this paper it is shown how this scheme can be supported during test pattern generation. The presented ATPG algorithm generates test sets which can be encoded very efficiently. Experiments show that the area required for synthesizing a BIST scheme that encodes these patterns is significantly less than the area needed for storing a compact test set. Furthermore, it is demonstrated that the proposed approach of combining ATPG and BIST synthesis leads to a considerably reduced hardware overhead compared to encoding a conventionally generated test set.
    ftp pdf? (76 KB)

  95. Test Register Insertion with Minimum Hardware Cost
    A. P. Ströle, H.-J. Wunderlich
    Proc. of the ACM/IEEE International Conference on CAD-95 (ICCAD), San Jose, CA, November 1995, pp. 95-101
    Abstract:
    Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a scheme is implemented by test registers, for instance BILBOs and CBILBOs, which are inserted into the circuit structure at appropriate places. An algorithm is presented which is able to find the cost optimal placement of test registers for nearly all the ISCAS'89 sequential benchmark circuits, and a suboptimal solution with slightly higher cost is obtained for all the circuits within a few minutes of computing time. The algorithm can also be applied to the Minimum Feedback Vertex Set problem in partial scan design, and an optimal solution is found for all the benchmark circuits. The resulting self-testable circuits are analyzed. It is found that often CBILBOs lead to a minimum hardware overhead and also simplify test scheduling and test control.
    ftp pdf? (108 KB)

  96. Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
    S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois
    IEEE Transactions on Computers, Vol. 44, No. 2, February 1995, pp. 223-233
    Abstract:
    In this paper, we propose a new scheme for Built-In Test (BIT) that uses Multiple-Polynomial Linear Feedback Shift Registers (MP-LFSRs). The same MP-LFSR that generates random patterns to cover easy to test faults is loaded with seeds to generate deterministic vectors for difficult to test faults. The seeds are obtained by solving systems of linear equations involving the seed variables for the positions where the test cubes have specified values. We demonstrate that MP-LFSRs produce sequences with significantly reduced probability of linear dependence compared to single polynomial LFSRs. We present a general method to determine the probability of encoding as a function of the number of specified bits in the test cube, the length of the LFSR and the number of polynomials. Theoretical analysis and experiments show that the probability of encoding a test cube with s specified bits in an s-stage LFSR with 16 polynomials is 1-10-6. We then present the new BIT scheme that allows for an efficient encoding of the entire test set. Here the seeds are grouped according to the polynomial they use and an implicit polynomial identification reduces the number of extra bits per seed to one bit. The paperalso shows methods of processing the entire test set consisting of test cubes with varied number of specified bits. Experimental results show the tradeoffs between test data storage and test application time while maintaining complete fault coverage.
    ftp pdf? (1.181 KB)

  97. Synthesis of Iddq-Testable Circuits: Integrating Built-In Current Sensors
    H.-J. Wunderlich, M. Herzog, J. Figueras, J.A. Carrasco, A. Calderon
    Proc. of the European Design & Test Conference (ED&TC), March 1995, pp. 573-580
    Abstract:
    "On-Chip" Iddq testing by the incorporation of Built-In Current (BIC) sensors has some advantages over "off-chip" techniques. However, the integration of sensors poses analog design problems which are hard to be solved by a digital designer. The automatic incorporation of the sensors using parameterized BIC cells could be a promising alternative. The work reported here identifies partitioning criteria to guide the synthesis of Iddq-testable circuits. The circuit must be partitioned, such that the defective Iddq is observable, and the power supply voltage pertubation is within specified limits. In addition to these constraints, also cost criteria are considered: circuit extra delay, area overhead of the BIC sensors, connectivity costs of the test circuitry, and the test application time. The parameters are estimated based on logical as well as electrical level information on the target cell library to be used in the technology mapping phase of the synthesis process. The resulting cost function is optimized by an evolution-based algorithm. When run over large benchmark circuits our method gives significantly superior results to those obtained using simpler and less comprehensive partitioning methods.
    ftp pdf? (91 KB)

  98. An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures
    S. Hellebrand, H.-J. Wunderlich
    Proc. of the ACM/IEEE International Conference on CAD-94 (ICCAD), San Jose, CA, November 1994, pp. 110-116
    Abstract:
    The BIST implementation of a conventionally synthesized controller in most cases requires the integration of an additional register only for test purposes. This leads to some serious drawbacks concerning the fault coverage, the system speed and the area overhead. A synthesis technique is presented, which uses the additional test register also to implement the system function by supporting self-testable pipeline-like controller structures. It will be shown, that if the need of two different registers in the final structure is already taken into account during synthesis, then the overall number of flipflops can be reduced,and the fault coverage and the system speed can be enhanced. The presented algorithm constructs realizations of a given finite state machine specification which can be trivially implemented by a self-testable structure. The efficiency of the procedure is ensured by a very precise characterization of the space ofsuitable realizations, which avoids the computational overhead of previously published algorithms.
    ftp pdf? (61 KB)

  99. A Unified Method for Assembling Global Test Schedules
    A. Ströle, H.- J. Wunderlich
    Proc. of the 3rd Asian Test Symposium (ATS), Nara, Japan, November 1994, pp. 268-273
    Abstract:
    In order to make a register transfer structure testable, it is usually divided into functional blocks that can be tested independently by various test methods. The test patterns are shifted in or generated autonomously at the inputs of each block. The test responses of a block are compacted or observed at its output register. In this paper a unified method for assembling all the single tests to a global schedule is presented. It is compatible with a variety of different test methods. The described scheduling procedures reduce the overall test time and minimize the number of internal registers that have to be made directly observable.

  100. Simulation Results of an Efficient Defect Analysis Procedure
    O. Stern, H.-J. Wunderlich
    Proc. of the 25th IEEE International Test Conference (ITC), Washington, DC, October 1994, pp. 729-738
    Abstract:
    For obtaining a zero defect level, a high fault coverage with respect to the stuck-at fault model is often not sufficient as there are many defects that show a more complex behavior. In this paper, a method is presented for computing the occurrence probabilities of certain defects and the realistic fault coverages for test sets. The method is highly efficient as a pre-processing step is used for partitioning the layout and extracting the defects ranked in the order of their occurrence probabilities. The method was applied to a public domain library where defects causing a complex faulty behavior are possible. The occurrence probability of these faults was computed, and the defect coverage for different test sets was determined.
    ftp pdf? (475 KB)

  101. Configuring Flip-Flops to BIST Registers
    A. Ströle, H.-J. Wunderlich
    Proc. of the 25th IEEE International Test Conference (ITC), Washington, DC, October 1994, pp. 939-948
    Abstract:
    Built-in self-test test registers must segment a circuit such that there exists a feasible test schedule. If a register transfer description is used for selecting the positions of test registers, the space for optimization is small. In this paper, 1-bit test cells are inserted at gate level, and an initial test schedule is constructed. Based on the information of this schedule, test cells that can be controlled in the same way are assembled to test registers. Finally, a test schedule at RT level is constructed and a minimal set of test control signals is determined. The presented approach can reduce both BIST hardware overhead and test application time. It is applicable to control units and circuits produced by control oriented synthesis where an RT description is not available. Considerable gains can also be obtained if existing RT structures are reconfigured for self-testing in the described way.
    ftp pdf? (956 KB)

  102. Synthesis of Self-Testable Controllers
    S. Hellebrand, H.-J. Wunderlich
    Proc. of the European Design Automation Conference (EDAC/ETC/EuroAsic), Paris, France, March 1994, pp. 580-585
    Abstract:
    The paper presents a synthesis approach for pipeline-like controller structures. These structures allow to implement a built-in self-test in two sessions without any extra test registers. Hence the additional delay imposed by the testcircuitry is reduced, the fault coverage is increased, and in many cases the overall area is minimal, too. The self-testable structure for a given finite state machine specification is derived from an appropiate realization of the machine. A theorem is proven that such realizations can be constructed by means of partition pairs. An algorithm to determine the optimal realizations is developed and benchmark experiments are presented to demonstrate the applicability of the presented approach.
    ftp pdf? (49 KB)

  103. An Efficient BIST Scheme Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers
    S. Venkataraman, J. Rajski, S. Hellebrand, S. Tarnick
    Proc. of the ACM/IEEE International Conference on CAD-93 (ICCAD), Santa Clara, CA, November 1993, pp. 572-577
    Abstract:
    In this paper we describe an optimized BIST scheme based on reseeding of multiple polynomial Linear Feedback Shift Registers (LFSRs). The same LFSR that is used to generate pseudo-random patterns, is loaded with seed from which it produces vectors that cover the testcube of difficult to test faults. The scheme is compatible with scan-design and achieves full coverage as it is based onrandom patterns combined with a deterministic test set. A method for processing the test set to allow for efficient encoding by the scheme is described. Algorithms for calculating LFSR seeds from the test set and for the selection and ordering of polynomials are described. Experimental results are provided for ISCAS-89 benchmark circuits to demonstrate the effectiveness of the scheme. The scheme allows an excellent trade-off between test data storage and test application time (number of test patterns) with a very small hardware overhead. We show the trade-off between test data storage and number of test patterns under the scheme.
    ftp pdf? (197 KB)

  104. Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
    S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois
    Proc. of the 23rd IEEE International Test Conference (ITC), Baltimore, MD, September 1992, pp. 120-129
    Abstract:
    In this paper we perform a comparative analysis of the encoding efficiency of BIST schemes based on reseeding of single polynomial LFSRs as well as LFSRs with fully programmable polynomials. Full programmability gives much better encoding efficiency. For a testcube with s carebits we need only s+4 bits in contrast to s+19 bits for reseeding of single polynomials, but since it involves solving systems of nonlinear equations it is not applicable to realistic cases. We propose a new BIST scheme where the generator can operate according to a number of primitve polynomials. The testcubes are encoded as the polynomial identifier and a seed. We present models of the encoding efficiency of this scheme and demonstrate, both theoretically and through extensive simulations, that such a scheme with 16 polynomials approaches the efficiency of the schemebased on full polynominal programmability, essentially preserving the computational simplicity of single reseeding.
    ftp pdf? (88 KB)

  105. Erfassung und Modellierung Komplexer Funktionsfehler in Mikroelektronik-Bauelementen
    O. Stern, H.-J. Wunderlich
    ITG-Fachbericht 119, 5. ITG-Fachtagung Mikroelektronik für die Informationstechnik, VDE-Verlag, Stuttgart, March 1992, pp. 117-122
    Abstract:
    Es wird ein Verfahren vorgestellt, das für die Grundzellen einer Zellbibliothek layoutabhängig die möglichen Fehlfunktionen bestimmt, die durch Fertigungsfehler verursacht werden können. Eingabe für das Verfahren sind neben dem Layout einer Zelle die Prozessparameter und die Defektverteilungen. Ausgabe sind die realistischen Fehlfunktionen mit ihren Auftrittswahrscheinlichkeiten. Damit können Testerzeugung und Testablauf beschleunigt, schwer testbare Fehler bestimmt und ihre Ursachen lokalisiert und beseitigt werden.

  106. Efficient Test Set Evaluation
    H.-J. Wunderlich, M. Warnecke
    Proc. of the European Conference on Design Automation (EDAC), Brussels, March 1992, pp. 428-433
    Abstract:
    The fault coverage obtained by a set of test patterns is usually determined by expensive fault simulation. Even using fault dropping techniques fault simulation provides more information than actually needed. For each fault the pattern is determined which detects this fault first. This is mainly redundant information if diagnosis is not required. We can dispense with this high resolution and restrict our interest on the set of faults which is detected by a set of patterns. It is shown theoretically and practically that this information is obtainable in an highly efficient way.

  107. Prüfgerechter Entwurf und Test hochintegrierter Schaltungen
    H.-J. Wunderlich, M. H. Schulz
    Informatik-Spektrum, Vol. 15, Issue 1, February 1992, pp. 23-32
    Abstract:
    Der Beitrag gibt einen Überblick über die wichtigsten praxisrelevanten Teststrategien, wobei unter einer Teststrategie nicht nur die Verfahren zur Testsatzerzeugung und zur eigentlichen Testdurchführung, sondern auch das zugrunde liegende Fehlermodell und die erforderlichen testfreundlichen Entwurfsmaßnahmen, die die Voraussetzung für die Anwendung dieser Verfahren darstellen, zu verstehen sind. Es werden die gängisten Methoden zum konventionellen externen Test vorgestellt und bewertet sowie das Prinzip der immer breitere Anwendung findenden Selbsttestmethoden und ihre Vorteile erläurtert. Nach einem kurzen Ausblick auf die Fortschritte, die Verfahren zur automatischen Synthese testbarer Schaltungen erhoffen lassen, werden schließlich Aspekte des Systemtests und insbesondere das Boundary-Scan-Prinzip und die damit verbundenen Vorteile diskutiert.

  108. Optimized Synthesis Techniques for Testable Sequential Circuits
    B. Eschermann, H.-J. Wunderlich
    IEEE Transactions on Computer-Aided Design, Vol. 11, No.3, March 1992, pp. 301-312
    Abstract:
    Innovative synthesis for testability strategies aim at considering testability while synthesizing a ciruit, whereas conventional design for testability methods modify the design after the circuit structure is synthesized. We describe a synthesis approach that maps a behavioral FSM description into a testable gate-level structure. The term "testable" in this context, besides implying the existence of tests, also means that the application of test patterns is facilitated. Depending on the test strategy, the state registers of the FSM are modified e.g. as scan path or self-test registers. The additional functionality of these state registers is utilized in system mode by interpreting them as "smart" state registers, capable of producing certain state transitions on their own. To make the best use of such registers, we propose a novel state encoding strategy based on an analytic formulation of the coding constraint satisfaction problem as a quadratic assignment problem. An additional minimization potential can be exploited by appropriately choosing the pattern generator for self-testable designs. Experimental results indicate that, compared with conventional design for testabiltiy approaches, significant savings are possible this way.
    ftp pdf? (1179 MB)

  109. The Pseudoexhaustive Test of Sequential Circuits
    H.-J. Wunderlich, S. Hellebrand
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 11, No.1, January 1992, pp. 26-33
    Abstract:
    The concept of a pseudoexhaustive test for sequential circuits is introduced in a way similar to that which is used for combinational networks. Using partial scan all cycles in the data flow of a sequential circuit are removed, such that a compact combinational model can be constructed. Pseudoexhaustive test sequences for the original circuit are constructed from a pseudoexhaustive test set for this model. To make this concept feasible for arbitrary circuits a technique for circuit segmentation is presented which provides special segmentation cells as well as the corresponding algorithms for the automatic placement of the cells. Example circuits show that the presented test strategyrequires less additional silicon area than a complete scan path. Thus the advantages of a partial scan path are combined with the well-known benefits of a pseudoexhaustive test, such as high fault coverage and simplified test generation.
    ftp pdf? (813 KB)

  110. Emulation of Scan Paths in Sequential Circuit Synthesis
    B. Eschermann, H.-J. Wunderlich
    Proc. of the 5th International Conference on Fault-Tolerant Computing Systems (FTCS), Nürnberg, Springer-Verlag, Informatik Fachberichte 1991, September 1991, pp. 136-147

  111. A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic
    T. Kropf, H.-J. Wunderlich
    Proc. of the 22nd IEEE International Test Conference (ITC), Nashville, TE, October 1991, pp. 55-66
    Abstract:
    Hardware verification and sequential test generation are aspects of the same problem, namely to prove the equal behavior determined by two circuit descriptions. During test generation, this attempt succeeds for the faulty and fault free circuit if redundancy exists, and during verification it succeeds, if the implementation is correct with regard to its specification. This observation can be used to cross-fertilize both areas, which have been treated separately up to now. In this paper, a common formal framework for hardware verification and sequential test pattern generation is presented, which is based on modeling the circuit behavior with temporal logic. In addition, a new approach to cope with non resetable flipflops in sequential test generation is proposed, which is not restricted to stuck-at faults. Based on this verification view, it is possible to provide the designer with one tool for checking circuit correctness and generating test patterns. Its first impelmentation and application is also described. ftp pdf? (333 KB)

  112. Signature Analysis and Test Scheduling for Self-Testable Circuits
    A. Ströle, H.-J. Wunderlich
    Proc. of the 21st International Symposium on Fault-Tolerant Computing (FTCS), Montreal, June 25-27, 1991, pp. 96-103
    Abstract:
    Usually in complex circuits the test execution is divided into a number of subtasks, each producing a signature in a self-test register. These signatures influence one another. In this paper it is shown how test schedules can be constructed, in order to minimize the number of signatures to be evaluated. The error masking probabilities decrease, when the subtasks of the test execution are repeated in an appropriate order, and an equilibrium situation is reached where the error masking probabilities are minimal. A method is presented for constructing test schedules such that only the signatures at the primary outputs must be evaluated to get a sufficient fault coverage. Then no internal scan path is required, only few signatures have to be evaluated at the end of the test execution, and the test control at chip and board level is simplified. The amount of hardware to implement a built-in self-test is reduced significantly.

  113. A Unified Approach for the Synthesis of Self-Testable Finite State Machines
    B. Eschermann, H.-J. Wunderlich
    Proc. of the 28th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 1991, pp. 372-377
    Abstract:
    Conventionally self-test hardware is added after synthesis is completed. For highly sequential circuits like controllers this design method either leads to high hardware overheads or compromises fault coverage. In this paper we outline a unified approach for considering self-test hardware like pattern generators and signature registers during synthesis. Three novel target structures are presented, and a method for designing parallel self-test circuits is discussed in more detail. For a collection of benchmark circuits we show that hardware overheads for self-testable circuits can be significantly reduced this way without sacrificing testability.
    ftp pdf? (770 KB)

  114. Maximizing the Fault Coverage in Complex Circuits by Minimal Number of Signatures
    H.-J. Wunderlich, A. Ströle
    Proc. of the International Symposium on Circuits and Systems (ISCAS), Singapore, June 11-14, 1991, pp. 1881-1884
    Abstract:
    Many self-test strategies use signature analysis to compress the test responses. In complex circuits the test execution is divided into a number of subtasks, each producing a signature in a self-test register. Whereas the conventional approach is to evaluate all these signatures, this paper presents methods to minimize the number of evaluated signatures without reducing the fault coverage. This is possible, since the signatures can influence one another during the test execution. For a fixed test schedule a minimal subset of signatures can be selected, and for a predetermined minimal subset of signatures the test schedule can be constructed such that the fault coverage is maximum. Both approaches result in significant hardware savings when a self-test is implemented.

  115. TESTCHIP: A Chip for Weighted Random Pattern Generation, Evaluation, and Test Control
    A. Ströle, H.-J. Wunderlich
    IEEE Journal of Solid-State Circuits, Vol.26, No.7, July 1991, pp. 1056-1063
    Abstract:
    In self-testable circuits additional hardware is incorporated for generating test patterns and evaluating test responses. In this paper a built-off test strategy is presented which moves the additional hardware to a programmable extra chip. This is a low-cost test strategy in three ways: 1) the use of random patterns eliminates the expensive test pattern computation; 2) a microcomputer and an ASIC replace the expensive automatic test equipment; and 3) the design for testability overheads are minimized. The presented ASIC generates random patterns, applies them to a circuit under test, and evaluates the test responses by signature analysis. It contains a hardware structure that can produce weighted random patterns corresponding to multiple programmable distributions. These patterns give a high fault coverage and allow short test lengths. A wide range of circuits can be tested as the only requirement is a scan path and no other test structures have to be built in.

  116. Parallel Self-Test and the Synthesis of Control Units
    B. Eschermann, H.-J. Wunderlich
    Proc. of the 2nd European Test Conference (ETC), Munich, April 1991, pp. 73-82
    Abstract:
    Most self-test techniques are implemented with so-called multifunctional test registers at any specific time either used for pattern generation or for response analysis. In a parallel self-test, however, test registers are used for pattern generation and response analysis simultaneously. In this paper a novel circuit structure for controllers with parallel self-test is presented, which does not result in a loss of fault coverage. By using a dedicated synthesis procedure, which considers the self-test hardware while generating the circuit structure instead of adding it after the design is completed ("synthesis for testability") the self-test overhead can be kept low. The structure also facilitates realistic dynamic tests. As an example to illustrate the approach, the IEEE boundary scan controller is used.

  117. TESTCHIP: A Chip for Weighted Random Pattern Generation, Evaluation, and Test Control
    A. Ströle, H.-J. Wunderlich, O.F. Haberl
    Proc. of the 16th European Solid-State Circuits Conference (ESSCIRC), Grenoble, France, 1990, pp. 101-104
    Abstract:
    A chip is presented that generates weighted random patterns, applies them to a circuit under test and evaluates the test responses. The generated test patterns correspond to multiple sets of weights. Test response evaluation is done by signature analysis. The chip can easily be connected to a micro computer and thus constitutes the key element of a low-cost test equipment.

  118. Error Masking in Self-Testable Circuits
    A. Ströle, H.-J. Wunderlich
    Proc. of the 21st IEEE International Test Conference (ITC), Washington, DC, September 10-14, 1990, pp. 544-552
    Abstract:
    In a self-test environment signature analysis is used to compact the test responses. In large circuits the test execution is divided into a number of subtasks each producing a signature in a self-test register. Aliasing occurs, if a faulty response sequence leads to a correct signature in a signature register. Aliasing probabilities for single signature registers are widely investigated. In this paper the effects of error masking in a multitude of signature registers are analysed. It is shown that a self-test can always be scheduled such that evaluating signatures only at the end of the complete test execution is sufficient. A method is presented to comute the probability that a fault leads to at least one faulty signature in a set of self-test registers. This method allows the computation of the fault coverage with respect to the complete test execution. A minimal subset of all self-test registers can be selected, so that only the signatures of these self-test registers have to be evalutated and the fault coverage is almost not affected. The benefits of the approach are a smaller number of self-test registers in the scan path, a smaller number of signatures to be evaluated, a simplified test control unit, and hence a significant reduction of the hardware required for built-in self-test structures.
    ftp pdf? (687 KB)

  119. Generating Pseudo-Exhaustive Vectors for External Testing
    S. Hellebrand, H.-J. Wunderlich, O. F. Haberl
    Proc. of the 21st IEEE International Test Conference (ITC), Washington, DC, September 10-14, 1990, pp. 670-679
    Abstract:
    In the past years special chips for external test have been sucessfully used for random pattern testing. In this paper a technique is presented to combine the advantages of such a low cost test with the advantages of pseudo-exhaustive testing, which are an enhanced fault coverage and a simplified test pattern generation.
    To achieve this goal two tasks are solved. Firstly, an algorithm is developed for pseudo-exhaustive test pattern generation, which ensures a feasible test length. Secondly, a chip design for applying these test patterns to a device under test is presented. The chip is programmed by the output of the presentedalgorithm and controls the entire test. The technique is first applied to devices with a scan path and then extended to sequential circuits. A large number of benchmark circuits have been investigated, and the results are presented.
    ftp pdf? (88 KB)

  120. Methoden der Testvorbereitung zum IC-Entwurf
    H.-J. Wunderlich, M. H. Schulz
    Mikroelektronik, VDE-Verlag, Vol. 4, Issue 3, May/June 1990, pp. 112-115
    Abstract:
    Neben dem eigentlichen Testen umfasst eine Teststrategie die Auswahl eines geeigneten Fehlermodells, ein Verfahren für den prüfgerechten strukturierten Entwurf sowie die Testsatzerzeugung. Ziel dieser Prüfvorbereitung ist die Steigerung der Produktqualität sowie die Senkung der Testkosten bei integrierten Schaltungen.

  121. Optimized Synthesis of Self-Testable Finite State Machines
    B. Eschermann, H.-J. Wunderlich
    Proc. of the 20th International Symposium on Fault-Tolerant Computing (FTCS), Newcastle, UK, June 26-28, 1990, pp. 390-397
    Abstract:
    In this paper a synthesis procedure for self-testable finite state machines is presented. Testability is already considered while transforming the behavioral description of the circiuit into a structural description. To this end a novel state encoding algorithm as well as a modified self-test architecture are developed. Experimental results show that this approach leads to a significant reduction of hardware overhead.

  122. The Effictiveness of Different Test Sets For PLAs
    P.C. Maxwell, H.-J. Wunderlich
    Proc. of the 1st European Design Automation Conference (EDAC), Glasgow, UK, March 1990, pp. 628-632
    Abstract:
    It has been theoretically demonstrated that the single stuck-at fault model for a PLA does not cover as many faults as the single crosspoint model. What has not been demonstrated is the real relative effectiveness of test sets generated using these models. This paper presents the results of a study involving presenting a number of test sets to fabricated PLAs to determine their effectiveness. The test sets included weighted random patterns, of particular interest owing to PLAs being random resistant. Details are given of a method to generate weights, taking into account a PLA's structure.

  123. Tools and Devices Supporting the Pseudo-Exhaustive Test
    S. Hellebrand, H.-J. Wunderlich
    Proc. of the 1st European Design Automation Conference (EDAC), Glasgow, UK, March 1990, pp. 13-17
    Abstract:
    In this paper logical cells and algorithms are presented supporting the design of pseudo-exhaustively testable circuits. The approach is based on real hardware segmentation, instead of path-sensitizing. The developed cells segment the entire circuits into exhaustively testable parts, and the presented algorithms place these cells, under the objective to minimize the hardware overhead.
    The approach is completely compatible with the usual LSSD-rules. The analysis of the well-known benchmark circuits shows only little additional hardware cost.
    ftp pdf? (66 KB)

  124. A Synthesis Approach to Reduce Test Overhead
    H.-J. Wunderlich, B. Eschermann
    Proc. of the 1st European Design Automation Conference (EDAC), Glasgow, UK, March 1990, p. 671
    Abstract:
    Today's logic design strategy is characterized by a division between synthesis, in which a functionally correct implementation is generated, and design for testability, in which the implementation is made testable. In this paper we propose to merge these two steps by utilizing a scan path structure to simplify the combinational logic of finite state machines. This results in a reduction of test overhead, because a part of the scan path is already incorporated during the synthesis process. Alternatively, it can be seen as using a new optimization potential in logic synthesis, since the circuit has to be made testable anyway and so the test hardware is provided "free".

  125. Multiple Distributions for Biased Random Test Patterns
    H.-J. Wunderlich
    IEEE Transactions on Computer-Aided Design, Vol. 9, No.6, June 1990, pp. 594-602
    Abstract:
    The test of integrated circuits by random patterns is very attractive, since no expensive test pattern generation is necessary and tests can be applied with a self-test technique or externally using linear feedback shift registers. Unfortunately, not all circuits are random testable, because either the fault coverage is too low or the required test length too large. In many cases the random test lengths can be reduced by orders of magnitude using weighted random patterns. However, there are also some circuits for which no single optimal set of weights exists. A set defines a distribution of the random patterns. In this paper, it is shown that the problem can be solved using several distributions instead of a single one. Furthermore, an efficient procedure for computing the optimized input probabilities is presented. If a sufficient number of distributions is applied, then all combinational circuits can be tested randomly with moderate test lengths. The patterns can be produced by an external chip, and an optimized test schedule for circuits with a scan path can be obtained. Moreover, formulas are described to determine strong bounds on the probability of detecting all faults. Fault simulation with weighted patterns shows a nearly complete coverage of all nonredundant faults.
    ftp pdf? (845 KB)

  126. An Analytical Approach to the Partial Scan Problem
    H.-J. Wunderlich, A. Kunzmann
    Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 1, No. 2, 1990, pp. 163-174
    Abstract:
    The scan design is the most widely used technique to ensure the testability of sequential circuits. In this article it is shown that testability is still guaranteed, even if only a small part of flipflops are integrated into a scan path. An algorithm is presented for selecting a minimal number of flipflops, which must be directly accessible. The direct accessibility ensures that, for each fault, the necessary test sequence is bounded linearly in the circuit size. Since the underlying problem is NP-complete, efficient heuristics are implemented to compute suboptimal solutions. Moreover, a new algorithm is presented to map a sequential circuit into a minimal combinational one, such that test pattern generation for both circuit representations is equivalent and the fast combinational ATPG methods can be applied. For all benchmark circuits investigated, the approach results in a significant reduction of the hardware overhead, and additionally a complete fault coverage is still obtained. Amazingly the overall test application time decreases in comparison with a complete scan path, since the width of the shifted patterns is shorter, and the number of patterns increase only to a small extent.
    ftp pdf? (885 KB)

  127. Methoden der Testvorbereitung
    H.-J. Wunderlich, M. H. Schulz
    Proc. of the ITG-Fachtagung Mikroelektronik für die Informationstechnik, Stuttgart, October 3-5, 1989, pp. 55-62
    Abstract:
    Neben der eigentlichen Testdurchführung umfasst eine Teststrategie die Auswahl eines geeigneten Fehlermodells, ein Verfahren für den prüfgerechten strukturierten Entwurf und die Testsatzerzeugung. Ziel dieser Prüfvorbereitung ist die Steigerung der Produktqualität und die Senkung der Kosten für die Testdurchführung.

  128. Automatische Synthese selbsttestbarer Moduln für hochkomplexe Schaltungen
    F. Kesel, H.-J. Wunderlich
    Proc. of the ITG-Fachtagung Mikroelektronik für die Informationstechnik, Stuttgart, October 3-5, 1989, pp. 63-68
    Abstract:
    Für den Test hochkomplexer digitaler Schaltungen bieten sich Selbsttestverfahren an, die auf multifunktionalen linear rückgekoppelten Schieberegistern beruhen. Diese erzeugen Pseudozufallsmuster und komprimieren die Testantworten zu einer Signatur. Durch einen automatischen Einbau der Selbsttestausstattung kann die Korrektheit des Entwurfs gewährleistet werden. Im vorliegenden Beitrag wird ein Verfahren vorgestellt, mit welchem sich multifunktionale Registerschaltungen automatisch synthetisieren lassen, welche gleich- und ungleichverteilte Pseudozufallsmuster erzeugen und die Testantworten durch Signaturanalyse komprimieren. Sie werden als Standardzellen erzeugt und können automatisch plaziert und verdrahtet werden.

  129. The Pseudo-Exhaustive Test of Sequential Circuits
    H.-J. Wunderlich, S. Hellebrand
    Proc. of the 20th IEEE International Test Conference (ITC), Washington, DC, 1989, pp. 19-27
    Abstract:
    The concept of a pseudo-exhaustive test for sequential circuits is introduced in a similar way as it is used for combinational networks. Instead of test sets one has to apply pseudo-exhaustive test sequences of a limited length, which provides well-known benefits as far as fault-coverage, self-test capability and simplicity of test generation are concerned. Design methods are presented for hardware segmentation which ensure that a pseudo-exhaustive test is feasible. Example circuits show that the presented test-strategy requires less additional silicon area than a complete scan path.
    ftp pdf? (845 KB)

  130. The Design of Random-Testable Sequential Circuits
    H.-J. Wunderlich
    Proc. of the 19th International Symposium on Fault-Tolerant Computing (FTCS), Chicago, June 21-23, 1989, pp. 110-117
    Abstract:
    In general, sequential circuits are considered not to be random-testable, since a required sequence may grow exponentially with the number of flipflops, and it is very unlikely that a certain sequence occurs at random. This problem can be solved by combining two tasks:
    1) A small part of the flipflops are directly accessible, for instance by a partial scan path or by a built-in self-test register.
    2) Weighted random patterns are applied to the modified sequential circuit.
    The paper describes a method to select a minimal set of flip-flops as mentioned in 1). Since this problem turns out to be NP-complete, suboptimal solutions can be derived using some heuristics. Furthermore, an algorithm is presented to compute the corresponding weights of the patterns, which are time-dependent in some cases. Finally the entire approach is validated with the help of examples. Only 10% - 40% of the flipflops have to be integrated into a partial scan path or into BIST-register in order to obtain nearly complete fault coverage by weighted random patterns.

  131. Parametrisierte Speicherzellen zur Unterstützung des Selbsttests mit optimierten und konventionellen Zufallsmustern
    H.-J. Wunderlich, F. Kesel
    GMD Berichte, 4. E.I.S.-Workshop, Bonn, February 1989, pp. 75-84
    Abstract:
    Viele Selbsttestverfahren für hochintegriete Schaltungen beruhen auf der Erzeugung von Zufallsmustern mit rückgekoppelten Schieberegistern. Oft wird jedoch für eine ausreichende Fehlererfassung eine unwirtschaftlich grosse Menge von Zufallsmustern benötigt, falls diese gleichverteilt erzeugt werden. Mit ungleichverteilten Zufallsmustern kann die Testlänge entscheidend reduziert werden, ein entsprechendes Selbsttestkonzept wurde als GURT (Generator of Unequiprobable Random Tests) in (Wund87b) vorgeschlagen. Im vorliegenden Beitrag werden Grundzellen zur Synthese von Registern nach dem GURT-Prinzip vorgestellt, die Probleme beim Entwurf eines entsprechenden Syntheseprogrammes diskutiert. Anhand eines Beispieles werden die Selbstkonzepte nach dem GURT-und nach dem BILBO-Prinzip verglichen.

  132. The Synthesis of Self-Test Control Logic
    O. Haberl, H.-J. Wunderlich
    Proc. of the COMPEURO 1989, Hamburg, May 8-12, 1989, pp. 5134-5136
    Abstract:
    In recent years, many built-in self-test techniques have been proposed based on feedback shift-registers for pattern generation and signature analysis. But in general, these test-registers cannot test several moduls of the chip concurrently, and they have to be controlled by an external automatic test equipment. The presented paper proposes a method to integrate the additional test control logic into the chip. Based on a register transfer description of the circuit, the test control is derived and an according finite automaton is synthesized. A hardware implementation is proposed, resulting in circuits, where the entire self-test only consists in activating the test mode, clocking and evaluating the overall signature.

  133. Automatisierung des Entwurfs vollständig testbarer Schaltungen
    S. Hellebrand, H.-J. Wunderlich
    Proc. of the 18. GI Jahrestagung II, Hamburg, Informatik-Fachberichte 188, Springer-Verlag, 1988, pp. 145-159
    Abstract:
    Die Kosten für die Testvorbereitung, Testerzeugung und Testdurchführung wachsen überproportional mit der Komplexität anwendungsspezifischer Schaltungen, und die Teststrategie sollte daher bereitsin einer sehr frühen Phase des Schaltungsentwurfs festgelegt und berücksichtigt werden. In diesem Artikel werden logische Grundzellen und Algorithmen zur Unterstützung des pseudo-erschöpfenden Tests vorgestellt. Diese Teststrategie hat den Vorteil, daß die äußerst rechenzeitaufwendige Testmustererzeugung entfällt und zugleich eine vollständige Fehlererfassung auf Gatterebene garantiert ist. Die vorgestellten Grundzellen dienen der Zerlegung der Gesamtschaltung in erschöpfend testbare Teile, die präsentierten Algorithmen sollen diese Segmentierungszellen so plazieren, daß der Mehraufwand an Silizium gering bleibt. Hierzu wurden Varianten sogenannter "Hill-Climbing" und "Simulated-Annealing"-Verfahren entwickelt.
    ftp pdf? (43 KB)

  134. Multiple Distributions for Biased Random Test Patterns
    H.-J. Wunderlich
    Proc. of the 19th IEEE International Test Conference (ITC), Washington, DC, September 12-14, 1988, pp. 236-244
    Abstract:
    The test of integrated circuits by random patterns is very attractive, since no expensive test pattern generation is necessary and the test application can be done by a self-test technique or externally using linear feedback shift-registers. Unfortunately not all circuits are random-testable, since the fault coverage would be too low or the necessary test length would be too large. In many cases the random test lengths can be reduced by orders of magnitude using weighted random patterns. But there are also some circuits where no single optimal weight exists. In this paper it is shown that the problem is solved using several distributions instead of a single one. Furthermore an efficient procedure is presented computing the optimized input probabilities. This way all combinational circuits can be made random-testable. Fault simulation with weighted patterns shows a complete coverage of all non-redundant faults. The patterns can be successively produced by an external chip and an optimized test scheme for circuits in a scan design can be established. As a result of its own formulas are derived determining sharp bounds of the probability that all faults are detected.

  135. Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits
    H.-J. Wunderlich, S. Hellebrand
    Proc. of the 18th International Symposium on Fault-Tolerant Computing (FTCS), Tokyo, Japan, June 27-30, 1988, pp. 36-45
    Abstract:
    In order to ensure a high product quality some authors propose pseudo-exhaustive or verification testing. This is applicable if each primary output of the combinational circuit only depends on a small set of primary inputs, where all possible patterns can be enumerated completely. But in CMOS-circuits even a single stuck-open fault may fail to be detected this way, and the already proposed additional test of each input transition is not sufficient either.
    In this paper a method based on linear feedback shift registers over finite fields is presented to generate for a natural number n a pattern sequence with minimal length detecting each m-multiple stuck-open fault for m <= n. A hardware architecture is discussed generating this sequence, and for n = 1 a built-in self-test approach is presented detecting all combinations of multiple combinational and single stuck-open faults.
    ftp pdf? (62 KB)

  136. Weighted Random Testing with Multiple Distributions
    Hans-Joachim Wunderlich
    Proc. of the 11th International Conference on Fault Tolerant Systems and Diagnostics, Akademie der Wissenschaften der DDR, Suhl, 1988, pp. 88-93

  137. Integrated Tools for Automatic Design for Testability
    D. Schmid, H.-J. Wunderlich and F. Feldbusch, S. Hellebrand, J. Holzinger,A. Kunzmann
    Tool Integration and Design Environments, F. J. Rammig (Editor), Amsterdam: Elsevier Science Publishers B. V. (North Holland), IFIP, 1988, pp. 233-258
    Abstract:
    An increasing part of the overall costs of custom and semicustom integrated circuits has to be spent for test purposes, and therefore the integration of test and design seems to be a key of cost reduction. At the University of Karlsruhe a program system is currently developed supporting the design of testable circuits. The program system under work essentially solves three tasks: 1. ) Selection of an economical test strategy. 2. ) Implementation of necessary circuit modifications in order to enhance testability, retaining the circuit function by construction. 3. ) Generation of the test program. A low cost test strategy is selected under constraints given by the user, who describes the intended application of the chip, its function and structure. These constraints include the number of produced chips, the desired dependability, the available test equipment, the chip size and architecture, technology, performance and many others. The surface of the program will be an expert system, asking the user for known parameters and proposing the test strategy.
    ftp pdf? (216 KB)

  138. Output-maximal control policies for cascaded production-inventory systems with control and state constraints
    J. Warschat, H.-J. Wunderlich
    Int. Journal of Systems Sci., Vol. 19, No. 6, 1988, pp. 1011-1020

  139. The Random Pattern Testability of Programmable Logic Arrays
    H.-J. Wunderlich
    Proc. of the IEEE International Conference on Computer Design (ICCD), New York, 1987, pp. 682-685

  140. On Computing Optimized Input Probabilities for Random Tests
    H.-J. Wunderlich
    Proc. of the IEEE/ACM 24th Design Automation Conference, Miami Beach, 1987, pp. 392-398
    ftp pdf? (650 KB)

  141. Self Test Using Unequiprobable Random Patterns
    H.-J. Wunderlich,
    Proc. of the 17th International Symposium on Fault-Tolerant Computing (FTCS), Pittsburgh, 1987, pp. 258-263

  142. The Integration of Test and High Level Synthesis in a General Design Environment
    D. Schmid, R. Camposano, A. Kunzmann, W. Rosenstiel, H.-J. Wunderlich,
    Proc. of the Integrated Circuits Technology Conference (ICTC), Limerick, Irland, pp. 317-331, 1986

  143. On Fault Modeling for Dynamic MOS Circuits
    H.-J. Wunderlich, W. Rosenstiel
    Proc. of the 23rd ACM/IEEE Design Automation Conference, Las Vegas, 1986, pp. 540-546
    ftp pdf? (555 KB)

  144. Design Automation of Random Testable Circuits,
    A. Kunzmann, H.-J. Wunderlich
    Proc. of the European Solid-State Circuits Conference (ESSCIRC), Toulouse, 1985, pp. 277-285

  145. PROTEST: A Tool for Probabilistic Testability Analysis
    H.-J. Wunderlich,
    Proc. of the 22nd ACM/IEEE Design Automation Conference, Las Vegas, 1985, pp. 204-211
    ftp pdf? (636 KB)

  146. Time-optimal control policies for cascaded production-inventory systems with control and state constraints
    J. Warschat, H.-J. Wunderlich
    Int. Journal of Systems Sci., Vol. 15, No. 5, 1984, pp. 513-524




  
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