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- Realistic gate model for efficient variation-aware timing analysis of very deep submicron CMOS circuits
- Parallel Aging Analysis
- Pattern Retargeting for IJTAG Scan Networks
- Evaluation of Software-based Control Flow Protection on GPGPU Architectures
- Micro Architecture for Fault Tolerant NoCs
- Fault Tolerant Routing Algorithm for fully- and partially-defective NoC switches
- Evaluation of Multiple Polynomials for Deterministic Self Test
- Fault Simulation for Reconfigurable Architectures
- Emulation of automotive complex systems-on-chips
- Machine Learning Methods for Fault Classification
- Simulation-based aging analysis
- Modeling of Design-for-test infrastructure in complex Systems-on-chips. (copy 1)
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