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Hans-Joachim Wunderlich
Rafal Baranowski
Claus Braun
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Atefe Dalirsani
Helmut Häfner
Nadereh Hatami
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Chang Liu
Michael Imhof
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Abdullah Mumtaz
Alexander Schoell
Dominik Ull
Marcus Wagner
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Realistic gate model for efficient variation-aware timing analysis of very deep submicron CMOS circuits
Parallel Aging Analysis
Pattern Retargeting for IJTAG Scan Networks
Evaluation of Software-based Control Flow Protection on GPGPU Architectures
Fault Tolerant Routing Algorithm for fully- and partially-defective NoC switches
Micro Architecture for Fault Tolerant NoCs
Using NoC as TAM for Online Switch Diagnosis
Evaluation of Multiple Polynomials for Deterministic Self Test
Fault Simulation for Reconfigurable Architectures
Emulation of automotive complex systems-on-chips
Machine Learning Methods for Fault Classification
Simulation-based aging analysis
Modeling of Design-for-test infrastructure in complex Systems-on-chips. (copy 1)
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A Gate-Level Aging Simulator
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Marcus Eggenberger
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