Adan Kohler

Project:

"Simulation hardware/software modelling and interfacing for NoC MPSoC Computers" within the cluster of "Simulation Technology" (SimTech)

Research interests:

• Many-core architectures with on-chip interconnection networks ("Network-on-Chip", NoC)
• Interfacing application software with NoC-based many-core architectures
• Optimizing communication patterns of high-performance computing applications
• Fault tolerance in NoCs
• Modelling and high-performance simulation of NoCs

Publications:

• A. Kohler and M. Radetzki, "Latency-optimized Collectives for High Performance on Intel's Single-chip Cloud Computer," in Proc. Many-core Applications Research Community (MARC) Symposium at RWTH Aachen University, S. Lankes and C. Clauss, Eds. Aachen, Germany, November 29-30, 2012, pp. 7-12, ISBN 978-3-00-039545-1.
  
  
• A. Kohler, M. Radetzki, P. Gschwandtner and T. Fahringer, "Low-Latency Collectives for the Intel SCC," in Proc. Conference on Cluster Computing (CLUSTER), Beijing, China, September 24-28, 2012, pp. 346-354.
  
  
• A. Kohler, J. M. Castillo-Sanchez, J. Gross and M. Radetzki, "Minimal MPI as Programming Interface for Multicore System-on-Chips," in Proc. Forum on Specification and Design Languages (FDL), Vienna, Austria, September 18-20, 2012, pp. 127-134.
  
  
• A. Kohler and M. Radetzki, "Optimized Reduce for Mesh-Based NoC Multiprocessors," in Proc. 26th IEEE International Parallel and Distributed Processing Symposium, Workshops & PhD Forum (IPDPSW), Shanghai, China, May 21-25, 2012, pp. 904-913.
  
  
• M. Radetzki and A. Kohler, "Cost-based Deflection Routing for Intelligent NoC Switches," in Solutions on Embedded Systems, Lecture Notes in Electrical Engineering, vol. 81, M. Conti, S. Orcioni, N. Martinez Madrid, and R.E.D. Seepold, Eds. Springer, 2011, pp. 77-90.
  
  
• G. Schley, M. Radetzki, and A. Kohler, "Degradability Enabled Routing for Network-on-Chip Switches," it - Information Technology, vol. 52, no. 4, August 2010, pp. 201-208.
  
  
• A. Kohler, G. Schley, and M. Radetzki, "Fault Tolerant Network on Chip Switching With Graceful Performance Degradation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 6, June 2010, pp. 883-896.
  
  
• A. Kohler and M. Radetzki, "A SystemC TLM2 Model of Communication in Wormhole Switched Networks-on-Chip," in Proc. 12th Forum on Specification and Design Languages (FDL), Sophia Antipolis, France, September 22-24, 2009.
  
  
• A. Kohler and M. Radetzki, "Degradierbare Switches für fehlertolerante Networks-on-Chip," in 3. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE), Stuttgart, Germany, September 21-23, 2009.
  
  
• M. Radetzki and A. Kohler, "An Intelligent Deflection Router for Networks-on-Chip," in Proc. 7th Workshop on Intelligent Solutions in Embedded Systems (WISES), Ancona, Italy, June 2009.
  
  
• A. Kohler and M. Radetzki, "Fault-Tolerant Architecture and Deflection Routing for Degradable NoC Switches," in Proc. 3rd ACM/IEEE International Symposium on Networks-on-Chip (NOCS), San Diego, CA, USA, May 10-13, 2009 (acceptance rate 18%), pp. 22-31.
  
  
• A. Kohler and M. Radetzki, "Modellierung und Simulation von Networks-on-Chip mit OSCI TLM2," in 12. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), C. Gremzow and N. Moser, Eds. Berlin, Germany, March 2-4, 2009, pp. 207-216, ISBN 978-3-7983-2118-2.

Teaching:

• SimTech Seminar: Parallel Programming (SS 11)
• Seminar: Advanced Topics in Embedded Systems (WS 10/11)
• Seminar: Reliable Networks-On-Chip in the Many-Core Era (SS 09)
• Exercises: Hardware-Software-Systementwurf (WS 08/09)

Theses (master, bachelor, diploma and study theses)

Please refer to our department-wide theses page.