Fault Tolerant Routing Algorithm for fully- and partially-defective NoC switches

In the recent years, Network-on-chip (NoC) has emerged as a new communication infrastructure to supersede the traditional bus structures and decrease the communication complexity of the current SoCs, which integrate hundred and thousands of cores into a single chip. Like any other digital system, NoC may become defect either during production due to process variations and electro-migration or after production due to material aging, soft errors, crosstalk, and mechanical or thermal stress.

Since NoC inherently carries structural redundancy, fault tolerant routing algorithms are proposed to efficiently deal with faulty conditions and utilize the non-faulty switch and interconnects of the NoC for communication.

In this thesis, the capabilities of available fault tolerant routing algorithms shall be examined to find out which routing algorithm is able to deal with partially defective switches and interconnects as well as faulty switches. Finally, an efficient deadlock and live-lock free fault tolerant routing algorithm is developed that has the following properties: a) avoids defective switches which are shut down, b) avoids defective switches or ports, c) avoids defective interconnects.

Prerequisites:
Lectures:
- Advanced Processor Architecture / Grundlagen der Rechnerarchitektur

Programming:
VHDL or Verilog (needed for hardware cost evaluation), C/systemC (any other programming language can be used if you are able to prepare the simulation platform for experimental results)

This thesis focuses on routing algorithms. Therefore, this is a good choice for people who are interested in algorithm development and network routing problems.

The thesis can be written in English or German.

Contact:

Atefe Dalirsani (Email: atefe.dalirsani@informatik.uni-stuttgart.de)

Hans-Joachim Wunderlich (Email: wu@informatik.uni-stuttgart.de)