Evaluation of Software-based Control Flow Protection on GPGPU Architectures

General-Purpose Graphics Processing Units (GPGPUs) are many-core architectures, which are increasingly used to accelerate sophisticated applications in scientific computing and simulation technology. These architectures gain their high computational performance through massive on-chip parallelism with hundreds of processing cores and very large numbers of concurrent threads. Although best performance can only be achieved when most threads follow the same control flow, each of the threads is in principle free to follow its own path. However, to reduce the design complexity, parts of the control logic in these architectures are shared by multiple processing cores.

In today's semiconductor technology nodes, soft errors are a growing concern, since they can have severe impact on the reliability of devices. Such soft errors can not only lead to erroneous computational values, they can also affect the control flow. This can lead to catastrophic failures.

Over the years, numerous techniques for the monitoring and protection of single control flows have been proposed. These approaches reach from signature-based methods to duplication- and assertion-based techniques. However, none of these monitoring and protection mechanisms have been evaluated in the context of many-threading GPGPU architectures.

In this thesis, a suitable control flow protection technique shall be extended and adapted to the needs of a modern many-threading GPGPU architecture.

Recommended Prerequisites:

Lectures:

- Advanced Processor Architecture / Grundlagen der Rechnerarchitektur

- Design and Test of Systems on a Chip / Hardware-based Fault Tolerance

Programming:

- Profound knowledge in C/C++ and Nvidia CUDA

This thesis can be written in English or German.

Contact:

Claus Braun (Email: claus.braun@informatik.uni-stuttgart.de)

Hans-Joachim Wunderlich (Email: wu@informatik.uni-stuttgart.de)