Project Partner

To the website of the University of Stuttgart

RM-BIST: Reliability Monitoring and Managing Built-In Self Test

Project Description

As CMOS VLSI technologies enter the nanometer scales, reliability is becoming one of the major challenges for successful downscaling. The increased sensitivity of VLSI circuits to environmental and external disturbances, process variations, radiation-induced errors, and aging factors exposes these systems to an elevated rate of transient, intermittent, and permanent errors during lifetime operation.

The main objective of the RM-BIST project is to extend Design for Test (DFT) circuitry, which is primarily used during manufacturing test of VLSI chips, to Design for Reliability (DFR) infrastructure. We take advantage of existing built-in self-test (BIST) circuitry and reuse it during lifetime operation to provide system monitoring and perform reliability prediction. Moreover, the modified BIST infrastructure is used to perform targeted reliability improvements. We identify, monitor, predict, and mitigate errors affecting the system reliability at different time scales to handle various reliability detractors (radiation-induced soft errors, intermittent faults due to process and runtime variations, transistor aging and electromigration). The goal is to provide runtime support for reliability screening and improvement by modifying and reusing existing DFT infrastructure with minimum costs.

 

Project Partner

 

Contact