Project page: Reliability Monitoring and Managing Built-In Self Test

The main objective of the RM-BIST project is to extend Design for Test (DFT) circuitry, which is primarily used during manufacturing test of VLSI chips, to Design for Reliability (DFR) infrastructure. We take advantage of existing built-in self-test (BIST) circuitry and reuse it during lifetime operation to provide system monitoring and perform reliability prediction. Moreover, the modified BIST infrastructure is used to perform targeted reliability improvements. We identify, monitor, predict, and mitigate errors affecting the system reliability at different time scales to handle various reliability detractors (radiation-induced soft errors, intermittent faults due to process and runtime variations, transistor aging and electromigration). The goal is to provide runtime support for reliability screening and improvement by modifying and reusing existing DFT infrastructure with minimum costs.

Projectpage: Robust Network On Chip Communication Through Hierarchical Online Diagnosis and Reconfiguration

The project ROCK targets the analysis and the prototypical development of robust architectures and associated design practices for Networks-on-Chips. Thereby, it meets the challenges of increased susceptibility of on-chip communication infrastructures against the massive influences caused by escalating integration density. ROCK pursues the strategy of conducting fault detection, online diagnosis und specific reconfiguration to tackle faults in a hierarchical manner throughout all network layers, aiming at selecting an optimal combination of activities over all layers. The quality of potential solutions is measured by their energy-minimal compliance to assurances made with respect to the performability of the network. For this purpose, performability will be defined for the research area of NoCs, incorporating communication performance and fault statistics. Any algorithms and architectures for controlling and performing diagnosis and reconfiguration shall themselves be designed as fault tolerant. Furthermore, their operation shall be transparent to the application processes and minimize interference with regular NoC communication. A wide range of architectures will be investigated based on the enabling technology of NoC fault models and high-level NoC fault simulation.

Projectpage: Online Failure Prediction for Microelectronic Circuits Using Aging Signatures

Microelectronic circuits suffer from life-time limiting aging. In this project, online in-field methods to assess circuit performance and remaining life-time will be developed to predict failures due to aging processes.
Sensors and monitoring infrastructure are used to analyze both operating conditions as well as aging indicators so that a system failure can be early indicated and prevented by technical measures. Novel maintenance concepts based on failure prediction allow for a substantial simplification of established structural fault tolerance measures (e.g. redundancy concepts) even in safety-critical applications since specific counter measures can be applied before an actual aging induced failure.
With the aid of such an on-line monitoring the effective life-time of a microelectronic product can be significantly increased at low cost.

Projectpage: Model-Based Test Generation for the Efficient Test of Hardware/Software Systems

Functionality in embedded systems is more and more realized by integrated hardware / software systems. Typically, these systems are strongly coupled with technical processes, as for instance the control of a vehicle, which show time-dependent, discrete-continuous dynamics. Testing for the correct functionality of their according design as well as of the final product contributes large sums to the production costs due to its complexity. An efficient method is required for the integrated test of hardware and software in these systems, which respects all the aspects of validation, debug, test and diadnosis.
Model-based development and test gains importance in research and also in industrial practice, as they support the systematic, stepwise refinement of requirements down to the implementation. By using models to describe the functionality of integrated hard- and software systems a higher efficiency of their test can be achieved. The central goal of this project is the generation of tests for the functionality and structure of an embedded hardware / software system from its system model along with an automatic evaluation and failure diagnosis.

Projectpage: Online Test Strategies for Reliable Reconfigurable Architectures

Dynamically reconfigurable architectures enable a major acceleration of diverse applications by changing and optimizing the structure of the system at runtime. Permanent and transient faults threaten the correct operation of such an architecture. This project aims to increase dependability of runtime reconfigurable systems by a novel system-level strategy for online tests and online adaptation to an impaired state. This will be achieved by (a) scheduling such that tests for reconfigurable resources are executed with minimal performance impact, (b) resource management such that partially faulty resources are used for components which do not require the faulty elements, and (c) online monitoring and error checking. To ensure reliable runtime reconfiguration, each reconfiguration process is thoroughly tested by a novel and efficient combination of online structural and functional tests. Compared to existing fault-tolerance approaches, our proposal avoids the large hardware overhead of structural redundancy schemes. The saved resources are available for further application acceleration. Still, the proposed scheme covers faults in the fabric, in the reconfigured application logic and errors in the process of reconfiguration. 

Project page: BMBF Project: End-to-End Diagnostic Capabilities for Automotive Electronics Systems

Together, AUDI AG, Continental AG, Infineon Technologies AG and ZMD AG are researching ways to improve the analytic and diagnostic capabilities of electronic control units (ECU) in motor vehicles. Through to 2013, the four partners, headed by Infineon, will work on ways to make error detection more precise and faults easier to rectify for automakers and repair shops. The project partners will be assisted by several research organizations and universities: the Fraunhofer Institute for Integrated Circuits in Dresden, the University of the Federal Armed Forces in Munich, and the Universities of Cottbus, Erlangen-Nuremberg, and Stuttgart.

Projectpage: Cluster of Excellence "Simulation-Technology": Mapping Simulation Algorithms to NoC MPSoC Computers

Technology scaling of nanoelectronic circuits currently introduces a fundamental paradigm shift of architectures for high-performance computing. Due to power and noise issues, single chip architectures have to gain increased performance by increased parallelism instead of increased frequency. Goal of this project is a methodology to map compute intensive portions of simulation algorithms to configurable Network-on-Chip Multi-Processor System on a Chip (NoC MPSoCs).

Projectpage: Test and Reliability of nanoelectronic Systems

In nanoelectronic circuit technology, circuits exhibit a high susceptibility to soft errors not only in memory arrays, but also in memory elements in random logic. Consequently, a goal of this project is the development of an efficient soft error protection scheme that uses both time and space redundancy.

Innovations in the automotive industry are driven by the advances in electronics and the widespread use of electronic control units. The goal of this project is to make semiconductor test and diagnosis mechanisms available at the system level, so that system failures caused by semiconductor defects can be analyzed without delay.

Project Partner: Audi AG

Projectpage: DFX

DFX is a logic synthesis tool and gate level simulator for circuit descriptions in VHDL and other hardware description languages. Besides that, DFX contains modern fault simulators and automatic test pattern generators for computer aided testing of integrated circuits.

Projectpage: Combining Fault Tolerance and Offline Test Strategies for Nanoscaled Electronics

Project Partner: Dipartimento di Automatica e Informatica, Politecnico di Torino

Projectpage: Eingebettete Diagnose- und Debugmethoden für VLSI Systeme in Nanometer-Technologie

Modern manufacturing processes are subject to high variations and a high sensitivity during operation. This project addresses the need for innovative embedded diagnosis solutions for such systems to reduce time-to-market with reasonable costs.

Projectpage: Concepts and Methods for Reliability Evaluation of Mechatronic Systems in Early Development Phases

Assuring a certain reliability level for mechatronic systems becomes more and more important as human life is affected by it. For a careful estimation of the system reliability not only the reliability of each individual component has to be taken into account but also the interaction among the components. In this project, tools and methodologies to improve reliability on the electronic layer of such systems are developed.

Projectpage: Improved Testing of VLSI Chips with Power Constraints

The elevated power dissipation during test has severe impact on test time, test reliability and product reliability, especially for high-performance processors like the Cell Processor.
In the course of this project, new methods for test planning that take advantage of clock gating and power gating are developed.

Project Partner: IBM Deutschland Entwicklung, IBM CAS

Projectpage: Neue Methoden für den Massiv-Parallel-Test im Hochvolumen, Yield Learning und beste Testqualität

High-end digital circuits need a very large amount of test vectors. Given such high data volumes, test cost is predicted to explode by a factor of 120.
This project addresses this challenge by developing and integrating innovative technology for generating and capturing data on-chip.

Project Partner: NXP Semiconductors, Hamburg

Projectpage: Power Conscious Online Test

This project tackles issues regarding power consumption during self-test of microprocessors. A new method is proposed which achieves high fault coverage, short test time with a small power/energy budget on the target system.

Projectpage: Extended Deterministic Logic Built-In Self-Test

Project Partner: Philips Semiconductors, Hamburg - Germany

Projectpage: Deterministic Built-In Self-Test

Project Partner: Philips Electronics, Netherlands

Projectpage: MMU for Leon

Project Partner: Gaisler Research, Sweden

Projectpage: Advanced Functional Built-In Self-Test Architectures for System-on-Chip

Partner: University of Turin

Projectpage: European Network for Initial and Continuing Education in VLSI/SoC Testing using remote ATE facilities

Partners: Universities of Montpellier, Barcelona, Turin, Lubljana and, as industrial partener, Agilent Technologies

Projektseite: Functional Built-In Self-Test

Partners: Universities of Tallin and Dresden