Laura Rodríguez Gómez
Name: | Dipl.-Inf. Laura Rodríguez Gómez | |
Address: | University of Stuttgart Institute of Computer Architecture and Computer Engineering Pfaffenwaldring 47 70569 Stuttgart | |
Room: | ||
Consultation Hour: | Wednesday, 10:00 - 11:00 | |
Phone: | +49 - 711 - 685 - 88276 | |
Fax: | +49 - 711 - 685 - 88288 | |
Mail: | laura.rodriguez@iti.uni-stuttgart.de |
Ongoing Projects
INTESYS: Model-Based Test Generation for the Efficient Test of Hardware/Software Systems
Projectpage: Model-Based Test Generation for the Efficient Test of Hardware/Software Systems Functionality in embedded systems is more and more realized by integrated hardware / software systems. Typically, these systems are strongly coupled with technical processes, as for instance the control of a vehicle, which show time-dependent, discrete-continuous dynamics. Testing for the correct functionality of their according design as well as of the final product contributes large sums to the production costs due to its complexity. An efficient method is required for the integrated test of hardware and software in these systems, which respects all the aspects of validation, debug, test and diadnosis. | |
Diana: BMBF Project: End-to-End Diagnostic Capabilities for Automotive Electronics Systems
Project page: BMBF Project: End-to-End Diagnostic Capabilities for Automotive Electronics Systems Together, AUDI AG, Continental AG, Infineon Technologies AG and ZMD AG are researching ways to improve the analytic and diagnostic capabilities of electronic control units (ECU) in motor vehicles. Through to 2013, the four partners, headed by Infineon, will work on ways to make error detection more precise and faults easier to rectify for automakers and repair shops. The project partners will be assisted by several research organizations and universities: the Fraunhofer Institute for Integrated Circuits in Dresden, the University of the Federal Armed Forces in Munich, and the Universities of Cottbus, Erlangen-Nuremberg, and Stuttgart. | |
Teaching
Lectures and Exercises
- Seminar:Formal Verification of Microprocessors (SS 13)
- Hardware Verification and Quality Assessment (SS 13)
- Elements of High-Performance RISC Processors: Design and Synthesis (WS 12/13)
- Design and Test of Systems on Chip (WS 12/13)
- Grundlagen der Rechnerarchitektur / Advanced Processor Architecture
in (SS 12) - Design and Test of Systems on Chip (WS 11/12)
- Grundlagen der Rechnerarchitektur/ Advanced Processor Architecture
in (SS 11)
Master / Diploma / Study Theses and Project Work
Proposed Topics
Finished Topics
- Master Thesis Nr.3304: Modeling of Design-for-test infrastructure in complex Systems-on-chips
David Prasetyo Buntoro
17.02.2012 - 18.08.2012

