Claus Braun
Name: | Dipl.-Inform. Claus Braun |
Address: | University of Stuttgart |
Room: | |
Telephone: | (+49) (0)711 / 685-88407 |
Telefax: | (+49) (0)711 / 685-88288 |
E-Mail: |
Projects
SimTech: Cluster of Excellence "Simulation-Technology": Mapping Simulation Algorithms to NoC MPSoC Computers
| Projectpage: Cluster of Excellence "Simulation-Technology": Mapping Simulation Algorithms to NoC MPSoC Computers Technology scaling of nanoelectronic circuits currently introduces a fundamental paradigm shift of architectures for high-performance computing. Due to power and noise issues, single chip architectures have to gain increased performance by increased parallelism instead of increased frequency. Goal of this project is a methodology to map compute intensive portions of simulation algorithms to configurable Network-on-Chip Multi-Processor System on a Chip (NoC MPSoCs). |
since 06.2008, SimTech Cluster of Excellence |
OTERA: Online Test Strategies for Reliable Reconfigurable Architectures
| Projectpage: Online Test Strategies for Reliable Reconfigurable Architectures Dynamically reconfigurable architectures enable a major acceleration of diverse applications by changing and optimizing the structure of the system at runtime. Permanent and transient faults threaten the correct operation of such an architecture. This project aims to increase dependability of runtime reconfigurable systems by a novel system-level strategy for online tests and online adaptation to an impaired state. This will be achieved by (a) scheduling such that tests for reconfigurable resources are executed with minimal performance impact, (b) resource management such that partially faulty resources are used for components which do not require the faulty elements, and (c) online monitoring and error checking. To ensure reliable runtime reconfiguration, each reconfiguration process is thoroughly tested by a novel and efficient combination of online structural and functional tests. Compared to existing fault-tolerance approaches, our proposal avoids the large hardware overhead of structural redundancy schemes. The saved resources are available for further application acceleration. Still, the proposed scheme covers faults in the fabric, in the reconfigured application logic and errors in the process of reconfiguration. | |
since 10.2010, DFG-Project: WU 245/10-1 | ||
Publications
- Module Diversification – A Design Method for Reliable Reconfigurable Architectures
H. Zhang, L. Bauer, M.A. Kochte, E. Schneider, C. Braun, M.E. Imhof, H.-J. Wunderlich and J. Henkel
to appear in IEEE International Test Conference (ITC) - Test Strategies for Reliable Runtime Reconfigurable Architectures
L. Bauer, C. Braun, M.E. Imhof, M.A. Kochte, E. Schneider, H. Zhang, J. Henkel, H.-J. Wunderlich
to appear in IEEE Transactions on Computers, 2013 - Acceleration of Monte-Carlo Molecular Simulations on Hybrid Computing Architectures
C. Braun, S. Holst, J.M. Castillo, J. Gross, and H.-J. Wunderlich
to appear in Proc. 30th IEEE International Conference on Computer Design, ICCD 2012, Montreal, Canada, 30.9-3.10., 2012 - Parallel Simulation of Apoptotic Receptor-Clustering on GPGPU Many-Core Architectures
C. Braun, M. Daub, A. Schöll, G. Schneider, and H.-J. Wunderlich
to appear in Proc. IEEE International Conference on Bioinformatics and Biomedicine, BIBM 2012, Philadelphia, USA, 4-7 October, 2012
- Transparent Structural Online Test for Reconfigurable Systems
M. S. Abdelfattah, L. Bauer, C. Braun, M. E. Imhof, M. A. Kochte, H. Zhang, J. Henkel, and H.-J. Wunderlich
Proc. 18th IEEE International On-Line Testing Symposium (IOLTS12), Sitges, Spain, June 27-29, 2012, pp. 37-42 - OTERA: Online Test Strategies for Reliable Reconfigurable Architectures
L. Bauer, C. Braun, M.E. Imhof, M.A. Kochte, H. Zhang, H.-J. Wunderlich, and J. Henkel
NASA/ESA Conference on Adaptive Hardware and Systems (AHS12), Nuremberg, Germany, June 25-28, 2012, pp. 38-45 - Reliable Simulations on Many-Core Architectures C. Braun, H.-J. Wunderlich
- Algorithmen-basierte Fehlertoleranz für Many-Core-Architekturen C. Braun, H.-J. Wunderlich
- Algorithm-based fault tolerance for many-core architectures C. Braun, H.-J. Wunderlich
International Conference on Simulation Technology (SimTech 2011), Stuttgart, Germany, June 14-17, 2011
it - Information Technology, Vol. 52, No. 4, August 2010
15th IEEE European Test Symposium (ETS), Praha, Czech Republic, May 24-28, 2010
Teaching
Lectures and Exercises
Seminars
SS 2012 | |
SS 2011 | |
Parallel Programming (SimTech GS Seminar) | |
WS 2009 | Grundlagen der Rechnerarchitektur, Advanced Processor Architecture |
SS 2009 | |
WS 2008 | Grundlagen der Rechnerarchitektur, Advanced Processor Architecture |
Master/Diploma Theses and Student Research Projects
SS2012 | Online Self-Test Wrapper for Runtime-Reconfigurable Systems |
WS2012 | Framework für beschleunigte Monte Carlo Molekularsimulationen auf hybriden Architekturen |
WS2012 | Effiziente mehrwertige Logiksimulation verzögerungsbehafteter Schaltungen auf datenparallelen Architekturen |
SS2012 | Ebenenübergreifende Simulation des HaPra-Prozessors |
WS2011 | Parallele Partikelsimulation auf GPGPU-Architekturen zur Evaluierung von Apoptose-Signalwegen |
SS2011 | Evaluation of Advanced Techniques for Structural FPGA Self-Test |
Implementing Density Functional Theory Methods on GPGPU Accelerators | |
WS2009 | Algorithmen-basierte Fehlertoleranz in Many-Core Systemen |
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