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On the Effectiveness of Simulation Parallelism on Data-Parallel Accelerators

Kategorie: Open Seminar - Rechnerarchitektur, SS 17

09:45 - 10:30, Haus der Kirche, Bad Herrenalb, Dipl.-Inf. Eric Schneider, Institut für Technische Informatik

The simulation of the functional and timing behavior is a crucial task during design and test validation of nano-scaled circuits.
Simulation algorithms need to become more and more accurate, which causes a drastic increase of the runtime complexity, quickly becoming inapplicable to designs with millions of gates.
In order to cope with this complexity, algorithms have been mapped in the past years for the execution on data-parallel Graphics Processing Units (GPUs) where a significant speedup over traditional compute architectures has been achieved, due to the inherent parallelism found in circuit simulation.

Parallelism can be exploited in many dimensions for a variety of different purposes.
This talk provides an overview of available dimensions of parallelism utilized in a recent state of the art GPU-accelerated timing simulator and discusses the impact as well as the scalability.