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Delay Fault detection in FinFET technology using parameter variation

Kategorie: Open Seminar - Rechnerarchitektur

09:00-09:45, external place, M. Sc. Zahra Paria Najafi Haghi, Institut für Technische Informatik

As devices can work properly in the beginning, weak structures must be identified by analyzing the non-functional circuit behavior with the help of appropriate observables. Besides power consumption, the circuit timing is one of the most important reliability indicators. In particular, small delay faults may indicate marginal hardware that can degrade further under stress and make a failure for a circuit when works in the field. However, these Small Delay Faults can be “hidden” at nominal test frequency. Therefore, conventional approaches for testing reach their limitations and new methods should be applied.

In this work, different defects in FinFET technology which cause extra delay to the circuit will be investigated and modeled. A FinFET circuit will be tested under different circumstances which can effect the duration of Delay Faults and therefore the possibility to detect them. These circumstances here mean giving different values to the Voltage and Temperature parameters and investigating their effect on Small Delay Faults. Therefore they will be used as a method to detect these Delay Faults


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