Test and Diagnosis of IJTAG Scan Networks
The increasing complexity of Systems-on-a-Chip (SoC) necessitates the use of a system-wide scan network to access on-chip instrumentation. Today's chips contain a multitude of instruments such as scan chains, debug circuitry, tuning equipment, Built-In-Self-Test (BIST) controllers, and physical sensors. The aim of the ongoing IEEE P1687 (IJTAG) standardization effort is to facilitate the use and reuse of such instruments by standardizing the system-wide network architecture and its access mechanisms.
The IJTAG infrastructure is primarily used for post-manufacture chip test and diagnosis. However, the infrastructure itself is prone to manufacturing defects: A broken gate in the scan network may render the corresponding hierarchical level of the chip inaccessible and hence impossible to test or diagnose.
The state-of-the-art techniques for test and diagnosis of scan networks are restricted to simple scan chain architectures. The goal of this thesis is to extend them to IJTAG scan networks which are reconfigurable, may have multiple hierarchical levels and contain multiplexers and derived control signals. The resulting test procedure should be able to cover faults in the IJTAG building blocks such as registers and multiplexers, while the diagnosis algorithm should be able to narrow down the defect location to a certain hierarchical level.
Recommended prerequisites:
- "Design and Test of Systems on a Chip" or
- Hardware Verification and Quality Assessment"
- C++
This thesis can be written in English or German
Contact:
Rafal Baranowski (Email: rafal.baranowski@informatik.uni-stuttgart.de)
Michael Kochte (Email: michael.kochte@informatik.uni-stuttgart.de)
Hans-Joachim Wunderlich (Email: wu@informatik.uni-stuttgart.de)