Test and Diagnosis of IJTAG Scan Networks

The increasing complexity of Systems-on-a-Chip (SoC) necessitates the use of a system-wide scan network to access on-chip instrumentation. Today's chips contain a multitude of instruments such as scan chains, debug circuitry, tuning equipment, Built-In-Self-Test (BIST) controllers, and physical sensors. The aim of the ongoing IEEE P1687 (IJTAG) standardization effort is to facilitate the reuse of such instruments by standardizing the system-wide network and its access mechanism.

IJTAG allows hierarchical and reconfigurable scan networks with fine-grained control over the access. To access an instrument in such a scan network, it is required to reconfigure the network in advance by accessing relevant control registers. Efficient generation of the necessary access patterns, also called pattern retargeting, is still an open problem in the EDA industry.

The existing state-of-the-art techniques for pattern retargeting are based on a mapping to Boolean satisfiability (SAT). Such techniques are robust but inefficient for scan networks with simple access dependencies. The goal of this thesis is to develop a dedicated pattern retargeting algorithm for irredundant scan networks represented at a register-transfer-level (RTL). Given the initial state of the network and a set of target instruments, the algorithm should generate the required access sequence. Access time optimization techniques can be explored optionally. The efficiency of the algorithm should be compared with state-of-the-art tools for pattern retargeting. The existing tools, benchmark scan networks, and a C++ software framework are provided.

Recommended prerequisites:

Contact:

Rafal Baranowski (Email: rafal.baranowski@informatik.uni-stuttgart.de)

Michael Kochte (Email: michael.kochte@informatik.uni-stuttgart.de)

Hans-Joachim Wunderlich (Email: wu@informatik.uni-stuttgart.de)