Modeling of Design-for-test infrastructure in complex Systems-on-chips

Every integrated circuit contains a piece of design-for-test (DFT) infrastructure in order to guarantee the chip quality after manufacture. The DFT resources are employed only once in the fab and are usually not available during regular system operation.

In order to assess the hardware integrity of a chip over its complete life-cycle, it is promising to reuse the DFT infrastructure as part of system-level test.

In this thesis, the provided system, a Tricore processor from Infineon,  must me partitioned and modified in order to enable the autonomous structural  test of every component of the system in the field without expensive external equipment .

This thesis is part of the research project “DIANA” in cooperation with Audi, Infineon, Continental and ZMD.

Prerequisites:

•    “Advanced Processor Architecture”
•    “Design and Test of Systems on a Chip”, or “Hardware Verification and Quality Assessment”.

The thesis can be written in English or German.

 
CONTACT  
Alejandro Cook (Email: alejandro.cook@informatik.uni-stuttgart.de)
Stefan Holst (Email: holst@informatik.uni-stuttgart.de)
Laura Rodríguez Gómez (Email: laura.rodriguez@informatik.uni-stuttgart.de)