Micro Programmable Architecture for Fault Tolerant NoC Switches

In the recent years, Network-on-chip (NoC) has emerged as a new communication infrastructure to supersede the traditional bus structures and decrease the communication complexity of the current SoCs, which integrate hundred and thousands of cores into a single chip. Like any other digital system, NoC may become defect either during production due to process variations and electro-migration or after production due to material aging, soft errors, crosstalk, and mechanical or thermal stress.

To deal with the defects in the NoC structures, a fault tolerant mechanism is needed to mask the faulty parts of the NoC and use the remaining non-faulty switches for communication. One way is to distribute the fault tolerant task among the switches. In this way, every switch must be able to find an alternative routing path in case of faulty condition in the NoC.

In this thesis, the micro-programmable architecture is suggested for the switches. Using the micro-programmable architecture make it possible to easily change the routing algorithm of the switches individually so that the faulty regions of the network can be masked. Although all of the switch architectures are identical, every switch may implement an individual routing algorithm which is especially needed for fault tolerant NoC structure.

Prerequisites:
Lectures:
- Advanced Processor Architecture / Grundlagen der Rechnerarchitektur

Programming:
strong VHDL or Verilog knowledge

This thesis focuses on design of a small switch in a hardware description language. Good knowledge of hardware design and computer architecture in addition to HDL skills is required.

The thesis can be written in English or German.

Contact:

Atefe Dalirsani (Email: atefe.dalirsani@informatik.uni-stuttgart.de)

Hans-Joachim Wunderlich (Email: wu@informatik.uni-stuttgart.de)