Fault Simulation for Reconfigurable Architectures

Reconfigurable gate arrays offer high flexibility for prototyping, but can also be employed for runtime adaptive hardware designs. The online reconfiguration of hardware allows for tremendous speed-ups at low power.

Current field-programmable gate arrays are already manufactured in latest technologies at 28 nm, raising concerns about the impact of aging-related failure mechanisms. To detect faults in reconfigurable gate arrays, dedicated on- and offline test methods must be employed which allow the test of the device in the field.

The scope of this thesis is to develop a fault simulation technique to assess the quality of different test strategies for reconfigurable gate arrays. This comprises the mapping of the reconfigurable components to a fault simulation framework and the automated conversion of the gate array structure to a fault simulation model. An extension to sequential behavior as well as delay fault simulation is possible.

Recommended Prerequisites:
Lectures:
- Advanced Processor Architecture / Grundlagen der Rechnerarchitektur
- Design and Test of Systems on a Chip
- Hardware Verification and Quality Assessment

Programming:
VHDL / Verilog, Java

The thesis can be written in English or German.

Contact:

Michael Kochte (Email: kochte@iti.uni-stuttgart.de)

Claus Braun (Email: claus.braun@informatik.uni-stuttgart.de)

Michael Imhof (Email: michael.imhof@informatik.uni-stuttgart.de)

Hans-Joachim Wunderlich (Email: wu@informatik.uni-stuttgart.de)