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74. Hardware/Software Co-Characterization for Approximate Computing
Schöll, A., Braun, C. and Wunderlich, H.-J.
Workshop on Approximate Computing, Pittsburgh, Pennsylvania, USA, 06 October 2016
2016
 
BibTeX:
@inproceedings{SchoeBW2016,
  author = {Schöll, Alexander and Braun, Claus and Wunderlich, Hans-Joachim},
  title = {{Hardware/Software Co-Characterization for Approximate Computing}},
  booktitle = {Workshop on Approximate Computing},
  year = {2016}
}
73. Autonomous Testing for 3D-ICs with IEEE Std. 1687
Ye, J.-C., Kochte, M.A., Lee, K.-J. and Wunderlich, H.-J.
First International Test Standards Application Workshop (TESTA), co-located with IEEE European Test Symposium, Amsterdam, The Netherlands, 26-27 May 2016
2016
 
BibTeX:
@inproceedings{YeKLW2016,
  author = {Ye, Jin-Cun and Kochte, Michael A. and Lee, Kuen-Jong and Wunderlich, Hans-Joachim},
  title = {{Autonomous Testing for 3D-ICs with IEEE Std. 1687}},
  booktitle = {First International Test Standards Application Workshop (TESTA), co-located with IEEE European Test Symposium},
  year = {2016}
}
72. ABFT with Probabilistic Error Bounds for Approximate and Adaptive-Precision Computing Applications
Braun, C. and Wunderlich, H.-J.
Workshop on Approximate Computing, Paderborn, Germany, 15-16 October 2015
2015
 
BibTeX:
@inproceedings{BraunW2015,
  author = {Braun, Claus and Wunderlich, Hans-Joachim},
  title = {{ABFT with Probabilistic Error Bounds for Approximate and Adaptive-Precision Computing Applications}},
  booktitle = {Workshop on Approximate Computing},
  year = {2015}
}
71. Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler
Hellebrand, S., Indlekofer, T., Kampmann, M., Kochte, M.A., Liu, C. and Wunderlich, H.-J.
27th GI/GMM/ITG Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'15), Bad Urach, Germany, 1-3 March 2015
2015
 
BibTeX:
@inproceedings{HelleIKKLW2015,
  author = {Hellebrand, Sybille and Indlekofer, Thomas and Kampmann, Matthias and Kochte, Michael A. and Liu, Chang and Wunderlich, Hans-Joachim},
  title = {{Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler}},
  booktitle = {27th GI/GMM/ITG Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'15)},
  year = {2015}
}
70. Hochbeschleunigte Simulation von Verzögerungsfehlern unter Prozessvariationen
Schneider, E., Kochte, M.A. and Wunderlich, H.-J.
27th GI/GMM/ITG Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'15), Bad Urach, Germany, 1-3 March 2015
2015
 
Abstract: Die Simulation kleiner Verzögerungsfehler ist ein wichtiger Bestandteil der Validierung nano-elektronischer Schaltungen. Prozessvariationen während der Herstellung haben großen Einfluss auf die Erkennung dieser Fehler und müssen bei der Simulation berücksichtigt werden. Die zeitgenaue Simulation von Verzögerungsfehlern ist verglichen mit traditioneller Logiksimulation oder statischer Zeitanalyse sehr aufwändig und die Rechenkomplexität steigt durch die Berücksichtigung von Variationen zusätzlich an. In dieser Arbeit wird ein hochparalleles Verfahren vorgestellt, welches Grafikprozessoren zur beschleunigten parallelen Simulation kleiner Verzögerungsfehler unter Variation anwendet. Das Verfahren berechnet akkurate Signalverläufe in der Schaltung und ermöglicht die Bestimmung einer Monte-Carlo-basierten statistischen Fehlererfassung für industrielle Schaltkreise unter zufälliger sowie systematischer Variation.
BibTeX:
@inproceedings{SchneKW2015,
  author = {Schneider, Eric and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Hochbeschleunigte Simulation von Verzögerungsfehlern unter Prozessvariationen}},
  booktitle = {27th GI/GMM/ITG Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'15)},
  year = {2015},
  abstract = {Die Simulation kleiner Verzögerungsfehler ist ein wichtiger Bestandteil der Validierung nano-elektronischer Schaltungen. Prozessvariationen während der Herstellung haben großen Einfluss auf die Erkennung dieser Fehler und müssen bei der Simulation berücksichtigt werden. Die zeitgenaue Simulation von Verzögerungsfehlern ist verglichen mit traditioneller Logiksimulation oder statischer Zeitanalyse sehr aufwändig und die Rechenkomplexität steigt durch die Berücksichtigung von Variationen zusätzlich an. In dieser Arbeit wird ein hochparalleles Verfahren vorgestellt, welches Grafikprozessoren zur beschleunigten parallelen Simulation kleiner Verzögerungsfehler unter Variation anwendet. Das Verfahren berechnet akkurate Signalverläufe in der Schaltung und ermöglicht die Bestimmung einer Monte-Carlo-basierten statistischen Fehlererfassung für industrielle Schaltkreise unter zufälliger sowie systematischer Variation.}
}
69. A-ABFT: Autonomous Algorithm-Based Fault Tolerance on GPUs
Braun, C., Halder, S. and Wunderlich, H.-J.
International Workshop on Dependable GPU Computing, in conjunction with the ACM/IEEE DATE'14 Conference, Dresden, Germany, 28 March 2014
2014
 
Keywords: Algorithm-Based Fault Tolerance, Graphics Processing Units, Scientific Computing, Simulation Technology, Floating-Point Arithmetic, Roundoff Error Analysis, Error Tolerance Determination
Abstract: General-purpose computations on graphics processing units (GPUs) enable large-scale scientific applications and simulations on the desktop. Such applications typically have high performance and reliability requirements. For GPUs, which are still designed for the graphics mass-market, hardware-based fault tolerance measures often do not have the highest priority, which makes the application of appropriate software-based fault tolerance mandatory.
Algorithm-based Fault Tolerance (ABFT) allows the efficient and effective protection of important kernels from scientific computing. Some ABFT schemes have already been adapted for GPU architectures. However, due to roundoff error introduced by floating-point arithmetic, ABFT requires the determination of tight error bounds for the error detection. The determination of such error bounds is a highly challenging task.
In this work, we introduce A-ABFT for GPUs, a new parallel ABFT scheme that determines appropriate error bounds for the checksum comparison step autonomously and which therefore enables the transparent operation of ABFT without any user interaction.
BibTeX:
@inproceedings{BraunHW2014,
  author = {Braun, Claus and Halder, Sebastian and Wunderlich, Hans-Joachim},
  title = {{A-ABFT: Autonomous Algorithm-Based Fault Tolerance on GPUs}},
  booktitle = {International Workshop on Dependable GPU Computing, in conjunction with the ACM/IEEE DATE'14 Conference},
  year = {2014},
  keywords = {Algorithm-Based Fault Tolerance, Graphics Processing Units, Scientific Computing, Simulation Technology, Floating-Point Arithmetic, Roundoff Error Analysis, Error Tolerance Determination},
  abstract = {General-purpose computations on graphics processing units (GPUs) enable large-scale scientific applications and simulations on the desktop. Such applications typically have high performance and reliability requirements. For GPUs, which are still designed for the graphics mass-market, hardware-based fault tolerance measures often do not have the highest priority, which makes the application of appropriate software-based fault tolerance mandatory.
Algorithm-based Fault Tolerance (ABFT) allows the efficient and effective protection of important kernels from scientific computing. Some ABFT schemes have already been adapted for GPU architectures. However, due to roundoff error introduced by floating-point arithmetic, ABFT requires the determination of tight error bounds for the error detection. The determination of such error bounds is a highly challenging task.
In this work, we introduce A-ABFT for GPUs, a new parallel ABFT scheme that determines appropriate error bounds for the checksum comparison step autonomously and which therefore enables the transparent operation of ABFT without any user interaction.} }
68. Adaptive Test and Diagnosis of Intermittent Faults
Cook, A., Rodriguez, L., Hellebrand, S., Indlekofer, T. and Wunderlich, H.-J.
14th Latin American Test Workshop (LATW'13), Cordoba, Argentina, 3-5 April 2013
2013
 
BibTeX:
@inproceedings{CookRHIW2013,
  author = {Cook, Alejandro and Rodriguez, Laura and Hellebrand, Sybille and Indlekofer, Thomas and Wunderlich, Hans-Joachim},
  title = {{Adaptive Test and Diagnosis of Intermittent Faults}},
  booktitle = {14th Latin American Test Workshop (LATW'13)},
  year = {2013}
}
67. Cross-Layer Dependability Modeling and Abstraction in Systems on Chip
Herkersdorf, A., Engel, M., Glaß, M., Henkel, J., Kleeberger, V.B., Kochte, M.A., Kühn, J.M., Nassif, S.R., Rauchfuss, H., Rosenstiel, W., Schlichtmann, U., Shafique, M., Tahoori, M.B., Teich, J., Wehn, N., Weis, C. and Wunderlich, H.-J.
Selse-9: The 9th Workshop on Silicon Errors in Logic - System Effects, Stanford, California, USA, 26-27 March 2013
2013
 
Keywords: Reliability Modeling, Cross-Layer
Abstract: The Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture level resilience methods.
BibTeX:
@inproceedings{HerkersdorfEGHKKKNRRSSTTWWW2013,
  author = {Herkersdorf, Andreas and Engel, Michael and Glaß, Michael and Henkel, Jörg and Kleeberger, Veit B. and Kochte, Michael A. and Kühn, Johannes M. and Nassif, Sani R. and Rauchfuss, Holm and Rosenstiel, Wolfgang and Schlichtmann, Ulf and Shafique, Muhammad and Tahoori, Mehdi B. and Teich, Jürgen and Wehn, Norbert and Weis, Christian and Wunderlich, Hans-Joachim},
  title = {{Cross-Layer Dependability Modeling and Abstraction in Systems on Chip}},
  booktitle = {Selse-9: The 9th Workshop on Silicon Errors in Logic - System Effects},
  year = {2013},
  keywords = {Reliability Modeling, Cross-Layer},
  abstract = {The Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture level resilience methods.}
}
66. Fault Modeling in Testing
Holst, S., Kochte, M.A. and Wunderlich, H.-J.
RAP Day Workshop, DFG SPP 1500, Munich, Germany, 21 December 2012
2012
 
Keywords: Fault modeling, generalized fault models, conditional fault models
BibTeX:
@inproceedings{HolstKW2012,
  author = {Holst, Stefan and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Fault Modeling in Testing}},
  booktitle = {RAP Day Workshop, DFG SPP 1500},
  year = {2012},
  keywords = {Fault modeling, generalized fault models, conditional fault models}
}
65. Structural In-Field Diagnosis for Random Logic Circuits
Cook, A., Elm, M., Wunderlich, H.-J. and Abelein, U.
23rd GI/GMM/ITG Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'11), Passau, Germany, 27 February-1 March 2011
2011
 
Keywords: In-field diagnosis; Built-In Self-Diagnosis
Abstract: In-field diagnosability of electronic components in larger systems such as automobiles becomes a necessity for both customers and system integrators. Traditionally, functional diagnosis is applied during integration and in workshops for infield failures or break-downs. However, functional diagnosis does not yield sufficient coverage to allow for short repair times and fast reaction on systematic failures in the production. Structural diagnosis could yield the desired coverage, yet recent builtin architectures which could be reused in the field either do not reveal diagnostic information or necessitate dedicated test schemes.
The paper at hand closes this gap with a new built-in test method for autonomous in-field testing and in-field diagnostic data collection. The proposed Built-In Self-Diagnosis method (BISD) is based on the standard BIST architecture and can seamlessly be integrated with recent, commercial DfT techniques. Experiments with industrial designs show that its overhead is marginal and its structural diagnostic capabilities are comparable to those of external diagnosis on high-end test equipment.
BibTeX:
@inproceedings{CookEWA2011,
  author = {Cook, Alejandro and Elm, Melanie and Wunderlich, Hans-Joachim and Abelein, Ulrich},
  title = {{Structural In-Field Diagnosis for Random Logic Circuits}},
  booktitle = {23rd GI/GMM/ITG Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'11)},
  year = {2011},
  keywords = {In-field diagnosis; Built-In Self-Diagnosis},
  abstract = {In-field diagnosability of electronic components in larger systems such as automobiles becomes a necessity for both customers and system integrators. Traditionally, functional diagnosis is applied during integration and in workshops for infield failures or break-downs. However, functional diagnosis does not yield sufficient coverage to allow for short repair times and fast reaction on systematic failures in the production. Structural diagnosis could yield the desired coverage, yet recent builtin architectures which could be reused in the field either do not reveal diagnostic information or necessitate dedicated test schemes.
The paper at hand closes this gap with a new built-in test method for autonomous in-field testing and in-field diagnostic data collection. The proposed Built-In Self-Diagnosis method (BISD) is based on the standard BIST architecture and can seamlessly be integrated with recent, commercial DfT techniques. Experiments with industrial designs show that its overhead is marginal and its structural diagnostic capabilities are comparable to those of external diagnosis on high-end test equipment.} }
64. Structural Test for Graceful Degradation of NoC Switches
Dalirsani, A., Holst, S., Elm, M. and Wunderlich, H.-J.
23rd GI/GMM/ITG Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'11), Passau, Germany, 27 February-1 March 2011
2011
 
Keywords: Network-on-Chip; Graceful Degradation; Performability; Logic Diagnosis
Abstract: Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is increased at the cost of reduced performability. In this paper, a new diagnosis method based on the standard flow of industrial volume testing is presented, which is able to identify the intact functions rather than providing only a pass/fail result for the complete switch.
The new method combines for the first time the precision of structural testing with information on the functional behavior in the presence of defects to determine the unaffected switch functions and use partially defective NoC switches. According to the experimental results, this improves the performability of NoCs as more than 61% of defects only impair one switch port. Unlike previous methods for implementing fault tolerant switches, the developed technique does not impose any additional area overhead and is compatible with any switch design.
BibTeX:
@inproceedings{DalirHEW2011,
  author = {Dalirsani, Atefe and Holst, Stefan and Elm, Melanie and Wunderlich, Hans-Joachim},
  title = {{Structural Test for Graceful Degradation of NoC Switches}},
  booktitle = {23rd GI/GMM/ITG Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'11)},
  year = {2011},
  keywords = {Network-on-Chip; Graceful Degradation; Performability; Logic Diagnosis},
  abstract = {Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is increased at the cost of reduced performability. In this paper, a new diagnosis method based on the standard flow of industrial volume testing is presented, which is able to identify the intact functions rather than providing only a pass/fail result for the complete switch.
The new method combines for the first time the precision of structural testing with information on the functional behavior in the presence of defects to determine the unaffected switch functions and use partially defective NoC switches. According to the experimental results, this improves the performability of NoCs as more than 61% of defects only impair one switch port. Unlike previous methods for implementing fault tolerant switches, the developed technique does not impose any additional area overhead and is compatible with any switch design.} }
63. Mixed-Mode-Mustererzeugung für hohe Defekterfassung beim Eingebetteten Test
Mumtaz, A., Imhof, M.E. and Wunderlich, H.-J.
23rd GI/GMM/ITG Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'11), Passau, Germany, 27 February-1 March 2011, pp. 55-58
2011
 
Keywords: BIST, Pseudo-Erschöpfender Test, Defekterfassung, N-Detect
Abstract: Die Mustererzeugung für den eingebetteten Test besteht häufig aus einer Phase zur Erzeugung von Zufallsmustern und einer Phase, in der deterministische Muster angelegt werden. Der vorliegende Beitrag stellt eine Methode vor, die erste Phase signifikant zu optimieren, um dadurch die Defekterfassung zu vergrößern und zugleich die Zahl der erforderlichen deterministischen Muster in der zweiten Phase zu reduzieren.
Die Methode beruht auf dem pseudo-erschöpfenden Test (PET), der als Verfahren zum fehlermodellunabhängigen Test mit hoher Defekterfassung vorgeschlagen wurde. Da seine Testzeit exponentiell mit der Schaltungsgröße wachsen kann, ist die Anwendung auf große Schaltungen in der Regel ausgeschlossen. In der vorliegenden Arbeit werden eingebaute Testregister für den partiellen pseudo-erschöpfenden Test (P-PET) vorgeschlagen, der mit aktueller Technologie skaliert und hinsichtlich Testkosten und Testzeit mit dem üblichen pseudo-zufälligen Test (PZT) vergleichbar ist. Die Vorteile bezüglich der Defekterfassung, N-Detektierbarkeit für Haftfehler und der Reduktion deterministischer Testlängen werden anhand aktueller industrieller Schaltungen nachgewiesen.
BibTeX:
@inproceedings{MumtaIW2011,
  author = {Mumtaz, Abdullah and Imhof, Michael E. and Wunderlich, Hans-Joachim},
  title = {{Mixed-Mode-Mustererzeugung für hohe Defekterfassung beim Eingebetteten Test}},
  booktitle = {23rd GI/GMM/ITG Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'11)},
  year = {2011},
  pages = {55--58},
  keywords = {BIST, Pseudo-Erschöpfender Test, Defekterfassung, N-Detect},
  abstract = {Die Mustererzeugung für den eingebetteten Test besteht häufig aus einer Phase zur Erzeugung von Zufallsmustern und einer Phase, in der deterministische Muster angelegt werden. Der vorliegende Beitrag stellt eine Methode vor, die erste Phase signifikant zu optimieren, um dadurch die Defekterfassung zu vergrößern und zugleich die Zahl der erforderlichen deterministischen Muster in der zweiten Phase zu reduzieren. 
Die Methode beruht auf dem pseudo-erschöpfenden Test (PET), der als Verfahren zum fehlermodellunabhängigen Test mit hoher Defekterfassung vorgeschlagen wurde. Da seine Testzeit exponentiell mit der Schaltungsgröße wachsen kann, ist die Anwendung auf große Schaltungen in der Regel ausgeschlossen. In der vorliegenden Arbeit werden eingebaute Testregister für den partiellen pseudo-erschöpfenden Test (P-PET) vorgeschlagen, der mit aktueller Technologie skaliert und hinsichtlich Testkosten und Testzeit mit dem üblichen pseudo-zufälligen Test (PZT) vergleichbar ist. Die Vorteile bezüglich der Defekterfassung, N-Detektierbarkeit für Haftfehler und der Reduktion deterministischer Testlängen werden anhand aktueller industrieller Schaltungen nachgewiesen.} }
62. SAT-Based Fault Coverage Evaluation in the Presence of Unknown Values
Kochte, M.A. and Wunderlich, H.-J.
Fault Tolerant Computing Workshop (FTC Kenkyuukai), Ena, Gifu, Japan, 20-22 January 2011
2011
 
Keywords: Unknown values; fault coverage; precise fault simulation
Abstract: Fault simulation of digital circuits must correctly compute fault coverage to assess test and product quality. In case of unknown values (X-values), fault simulation is pessimistic and underestimates actual fault coverage, resulting in increased test time and data volume, as well as higher overhead for design- for-test. This work proposes a novel algorithm to determine fault coverage with significantly increased accuracy, offering increased fault coverage at no cost, or the reduction of test costs for the targeted coverage. The algorithm is compared to related work and evaluated on benchmark and industrial circuits.
BibTeX:
@inproceedings{KochtW2011,
  author = {Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{SAT-Based Fault Coverage Evaluation in the Presence of Unknown Values}},
  booktitle = {Fault Tolerant Computing Workshop (FTC Kenkyuukai)},
  year = {2011},
  keywords = {Unknown values; fault coverage; precise fault simulation},
  abstract = {Fault simulation of digital circuits must correctly compute fault coverage to assess test and product quality. In case of unknown values (X-values), fault simulation is pessimistic and underestimates actual fault coverage, resulting in increased test time and data volume, as well as higher overhead for design- for-test. This work proposes a novel algorithm to determine fault coverage with significantly increased accuracy, offering increased fault coverage at no cost, or the reduction of test costs for the targeted coverage. The algorithm is compared to related work and evaluated on benchmark and industrial circuits.}
}
61. Low-Capture-Power Post-Processing of Test Vectors for Test Compression Using SAT Solver
Miyase, K., Kochte, M.A., Wen, X., Kajihara, S. and Wunderlich, H.-J.
IEEE International Workshop on Defect and Data-Driven Testing (D3T'10), Austin, Texas, USA, 4-5 November 2010
2010
 
Keywords: Low power testing, power-safe test
BibTeX:
@inproceedings{MiyaseKWKW2010a,
  author = {Miyase, K. and Kochte, Michael A. and Wen, X. and Kajihara, S. and Wunderlich, Hans-Joachim},
  title = {{Low-Capture-Power Post-Processing of Test Vectors for Test Compression Using SAT Solver}},
  booktitle = {IEEE International Workshop on Defect and Data-Driven Testing (D3T'10)},
  year = {2010},
  keywords = {Low power testing, power-safe test}
}
60. On Determining the Real Output Xs by SAT-Based Reasoning
Elm, M., Kochte, M.A. and Wunderlich, H.-J.
Fault Tolerant Computing Workshop (FTC Kenkyuukai), Chichibu, Japan, 15-17 July 2010
2010
 
Keywords: X-Masking
Abstract: Embedded testing, built-in self-test and methods for test compression rely on efficient test response compaction. Often, a circuit under test contains sources of unknown values (X), uninitialized memories for instance. These X values propagate through the circuit and may spoil the response signatures. The standard way to overcome this problem is X-masking.
Outputs which carry an X value are usually determined by logic simulation. In this paper, we show that the amount of Xs is significantly overestimated, and in consequence outputs are overmasked, too. An efficient way for the exact computation of output Xs is presented for the first time. The resulting X-masking promises significant gains with respect to test time, test volume and fault coverage.
BibTeX:
@inproceedings{ElmKW2010,
  author = {Elm, Melanie and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{On Determining the Real Output Xs by SAT-Based Reasoning}},
  booktitle = {Fault Tolerant Computing Workshop (FTC Kenkyuukai)},
  year = {2010},
  keywords = {X-Masking},
  abstract = {Embedded testing, built-in self-test and methods for test compression rely on efficient test response compaction. Often, a circuit under test contains sources of unknown values (X), uninitialized memories for instance. These X values propagate through the circuit and may spoil the response signatures. The standard way to overcome this problem is X-masking.
Outputs which carry an X value are usually determined by logic simulation. In this paper, we show that the amount of Xs is significantly overestimated, and in consequence outputs are overmasked, too. An efficient way for the exact computation of output Xs is presented for the first time. The resulting X-masking promises significant gains with respect to test time, test volume and fault coverage.} }
59. Application Dependent Vulnerability of Combinational Circuits
Baranowski, R. and Wunderlich, H.-J.
22nd ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'10), Paderborn, Germany, 28 February-2 March 2010
2010
 
BibTeX:
@inproceedings{BaranW2010,
  author = {Baranowski, Rafal and Wunderlich, Hans-Joachim},
  title = {{Application Dependent Vulnerability of Combinational Circuits}},
  booktitle = {22nd ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'10)},
  year = {2010}
}
58. Effiziente Fehlersimulation auf Many-Core-Architekturen
Kochte, M.A., Schaal, M., Wunderlich, H.-J. and Zöllin, C.
22nd ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'10), Paderborn, Germany, 28 February-2 March 2010
2010
 
BibTeX:
@inproceedings{KochtSWZ2010,
  author = {Kochte, Michael A. and Schaal, Marcel and Wunderlich, Hans-Joachim and Zöllin, Christian},
  title = {{Effiziente Fehlersimulation auf Many-Core-Architekturen}},
  booktitle = {22nd ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'10)},
  year = {2010}
}
57. Diagnose mit extrem kompaktierten Fehlerdaten
Holst, S. and Wunderlich, H.-J.
21. ITG/GI/GMM Workshop "Testmethoden und Zuverlaessigkeit von Schaltungen und Systemen" (TuZ'09), Bremen, Germany, 15-17 February 2009, pp. 15-20
2009
 
Keywords: Reliability; Testing; Fault-Tolerance; CR B.8.1; Diagnose; eingebettete Diagnose; Multi–site–Test; Kompaktierung; Design-for-Test
Abstract: Im Hochvolumentest sind Testzeit, Testdatenvolumen und hochperformante Tester die entscheidenden Kostenfaktoren. Techniken des eingebetteten Tests wie ”Built–in Self–test“ (BIST) und ”Multi–site“–Testen senken effizient die Testkosten, machen die Diagnose aber schwerer. Diese Arbeit stellt ein Verfahren zur Antwortkompaktierung und ein entsprechendes Diagnoseverfahren vor, das sich besonders für BIST und den ”Multi–site“–Test eignet. Die experimentellen Ergebnisse an industriellen Schaltungen zeigen, dass sich mit diesem Ansatz
gleichzeitig die Testzeit verk¨ urzt, das Antwortvolumen reduziert und die diagnostische Auflösung verbessert. Ein Vergleich mit X-Compact zeigt, dass einfache Paritäts–Informationen höhere
diagnostische Auflösungen pro Antwortbit ermöglichen als komplexere Signaturen.
BibTeX:
@inproceedings{HolstW2009,
  author = {Holst, Stefan and Wunderlich, Hans-Joachim},
  title = {{Diagnose mit extrem kompaktierten Fehlerdaten}},
  booktitle = {21. ITG/GI/GMM Workshop "Testmethoden und Zuverlaessigkeit von Schaltungen und Systemen" (TuZ'09)},
  year = {2009},
  pages = {15--20},
  keywords = {Reliability; Testing; Fault-Tolerance; CR B.8.1; Diagnose; eingebettete Diagnose; Multi–site–Test; Kompaktierung; Design-for-Test},
  abstract = {Im Hochvolumentest sind Testzeit, Testdatenvolumen und hochperformante Tester die entscheidenden Kostenfaktoren. Techniken des eingebetteten Tests wie ”Built–in Self–test“ (BIST) und ”Multi–site“–Testen senken effizient die Testkosten, machen die Diagnose aber schwerer. Diese Arbeit stellt ein Verfahren zur Antwortkompaktierung und ein entsprechendes Diagnoseverfahren vor, das sich besonders für BIST und den ”Multi–site“–Test eignet. Die experimentellen Ergebnisse an industriellen Schaltungen zeigen, dass sich mit diesem Ansatz
gleichzeitig die Testzeit verk¨ urzt, das Antwortvolumen reduziert und die diagnostische Auflösung verbessert. Ein Vergleich mit X-Compact zeigt, dass einfache Paritäts–Informationen höhere
diagnostische Auflösungen pro Antwortbit ermöglichen als komplexere Signaturen.} }
56. Modellierung der Testinfrastruktur auf der Transaktionsebene
Kochte, M.A., Zöllin, C., Imhof, M.E., Salimi Khaligh, R., Radetzki, M., Wunderlich, H.-J., Di Carlo, S. and Prinetto, P.
21th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'09), Bremen, Germany, 15-17 February 2009, pp. 61-66
2009
 
Keywords: Reliability; Testing; Fault-Tolerance; CR B.8.1
Abstract: Dieser Artikel stellt eine Methode vor, den Entwurfsraum beim prüfgerechten Entwurf (engl. Design-for-Test, DfT) zu untersuchen und Teststrategien und Testschedules zu validieren. Alle Teile der Testinfrastruktur, wie etwa die Testeranbindung (Test Access Mechanisms), die Testwrapper, die Testdatenkompression sowie die entsprechenden Steuerwerke werden auf Transaktionsebenenmodelle (TLMs) abgebildet. Die kommunikationsbezogene Sicht der TLMs eignet sich besonders, da viele Aspekte des Tests die Übertragung großer Mengen an Teststimuli und -antworten erfordern. An einer Fallstudie wird der Einsatz von TLMs in frühen Entwurfsphasen erläutert. Der vorgestellte Ansatz hat wesentlich höhere Simulationseffizienz als Ansätze auf Register-Transfer- und Gatterebene.
BibTeX:
@inproceedings{KochtZISRWDP2009,
  author = {Kochte, Michael A. and Zöllin, Christian and Imhof, Michael E. and Salimi Khaligh, Rauf and Radetzki, Martin and Wunderlich, Hans-Joachim and Di Carlo, Stefano and Prinetto, Paolo},
  title = {{Modellierung der Testinfrastruktur auf der Transaktionsebene}},
  booktitle = {21th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'09)},
  year = {2009},
  pages = {61--66},
  keywords = {Reliability; Testing; Fault-Tolerance; CR B.8.1},
  abstract = {Dieser Artikel stellt eine Methode vor, den Entwurfsraum beim prüfgerechten Entwurf (engl. Design-for-Test, DfT) zu untersuchen und Teststrategien und Testschedules zu validieren. Alle Teile der Testinfrastruktur, wie etwa die Testeranbindung (Test Access Mechanisms), die Testwrapper, die Testdatenkompression sowie die entsprechenden Steuerwerke werden auf Transaktionsebenenmodelle (TLMs) abgebildet. Die kommunikationsbezogene Sicht der TLMs eignet sich besonders, da viele Aspekte des Tests die Übertragung großer Mengen an Teststimuli und -antworten erfordern. An einer Fallstudie wird der Einsatz von TLMs in frühen Entwurfsphasen erläutert. Der vorgestellte Ansatz hat wesentlich höhere Simulationseffizienz als Ansätze auf Register-Transfer- und Gatterebene.}
}
55. On the Reliability Modeling of Embedded Hardware-Software Systems
Kochte, M.A., Baranowski, R. and Wunderlich, H.-J.
1st IEEE Workshop on Design for Reliability and Variability (DRV'08), Santa Clara, California, USA, 30-31 October 2008
2008
 
Keywords: Reliability; Testing; Fault-Tolerance; CR B.8.1
BibTeX:
@inproceedings{KochtBW2008,
  author = {Kochte, Michael A. and Baranowski, Rafal and Wunderlich, Hans-Joachim},
  title = {{On the Reliability Modeling of Embedded Hardware-Software Systems}},
  booktitle = {1st IEEE Workshop on Design for Reliability and Variability (DRV'08)},
  year = {2008},
  keywords = {Reliability; Testing; Fault-Tolerance; CR B.8.1}
}
54. Integrating Scan Design and Soft Error Correction in Low-Power Applications
Imhof, M.E., Wunderlich, H.-J. and Zöllin, C.
1st International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR'08), Verbania, Italy, 25-29 May 2008
2008
 
Keywords: Reliability; Testing; Fault-Tolerance; CR B.8.1; Robust design; fault tolerance; latch; low power; register; single event effects
Abstract: In many modern circuits, the number of memory elements in the random logic is in the order of the number of SRAM cells on chips only a few years ago. In arrays, error correcting coding is the dominant technique to achieve acceptable soft-error rates. For low power applications, often latches are clock gated and have to retain their states during longer periods while miniaturization has led to elevated susceptibility and further increases the need for protection.
This paper presents a fault-tolerant register latch organization that is able to detect single-bit errors while it is clock gated. With small addition, single and multiple errors are detected in the clocked mode, too. The registers can be efficiently integrated similar to the scan design flow, and error detecting or locating information can be collected at module level. The resulting structure can be efficiently reused for offline and general online testing.
BibTeX:
@inproceedings{ImhofWZ2008,
  author = {Imhof, Michael E. and Wunderlich, Hans-Joachim and Zöllin, Christian},
  title = {{Integrating Scan Design and Soft Error Correction in Low-Power Applications}},
  booktitle = {1st International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR'08)},
  year = {2008},
  keywords = {Reliability; Testing; Fault-Tolerance; CR B.8.1; Robust design; fault tolerance; latch; low power; register; single event effects},
  abstract = {In many modern circuits, the number of memory elements in the random logic is in the order of the number of SRAM cells on chips only a few years ago. In arrays, error correcting coding is the dominant technique to achieve acceptable soft-error rates. For low power applications, often latches are clock gated and have to retain their states during longer periods while miniaturization has led to elevated susceptibility and further increases the need for protection.
This paper presents a fault-tolerant register latch organization that is able to detect single-bit errors while it is clock gated. With small addition, single and multiple errors are detected in the clocked mode, too. The registers can be efficiently integrated similar to the scan design flow, and error detecting or locating information can be collected at module level. The resulting structure can be efficiently reused for offline and general online testing.} }
53. Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen
Amgalan, U., Hachmann, C., Hellebrand, S. and Wunderlich, H.-J.
20th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'08), Wien, Austria, 24-26 February 2008
2008
 
BibTeX:
@inproceedings{AmgalHHW2008,
  author = {Amgalan, Uranmandakh and Hachmann, Christian and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
  title = {{Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen}},
  booktitle = {20th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'08)},
  year = {2008}
}
52. Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit
Coym, T., Hellebrand, S., Ludwig, S., Straube, B., Wunderlich, H.-J. and Zöllin, C.
20th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'08), Wien, Austria, 24-26 February 2008, pp. 153-157
2008
 
Keywords: Reliability; Testing; Fault-Tolerance; CR B.8.1
BibTeX:
@inproceedings{CoymHLSWZ2008,
  author = {Coym, Torsten and Hellebrand, Sybille and Ludwig, Stefan and Straube, Bernd and Wunderlich, Hans-Joachim and Zöllin, Christian},
  title = {{Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit}},
  booktitle = {20th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'08)},
  year = {2008},
  pages = {153--157},
  keywords = {Reliability; Testing; Fault-Tolerance; CR B.8.1}
}
51. Prüfpfad Konfigurationen zur Optimierung der diagnostischen Auflösung
Elm, M. and Wunderlich, H.-J.
20th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'08), Wien, Austria, 24-26 February 2008, pp. 7-11
2008
 
Keywords: Reliability; Testing; Fault-Tolerance; CR B.8.1
BibTeX:
@inproceedings{ElmW2008,
  author = {Elm, Melanie and Wunderlich, Hans-Joachim},
  title = {{Prüfpfad Konfigurationen zur Optimierung der diagnostischen Auflösung}},
  booktitle = {20th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'08)},
  year = {2008},
  pages = {7--11},
  keywords = {Reliability; Testing; Fault-Tolerance; CR B.8.1}
}
50. Reduktion der Verlustleistung beim Selbsttest durch Verwendung testmengenspezifischer Information
Imhof, M.E., Wunderlich, H.-J., Zöllin, C., Leenstra, J. and Maeding, N.
20th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'08), Wien, Austria, 24-26 February 2008, pp. 137-141
2008
 
Keywords: Reliability; Testing; Fault-Tolerance; CR B.8.1
Abstract: Der während des Selbsttests von Schaltungen mit deaktivierbaren Prüfpfaden verwendete Testplan entscheidet über die Verlustleistung während des Tests. Bestehende Verfahren zur Erzeugung des Testplans verwenden überwiegend topologische Information, zum Beispiel den Ausgangskegel eines Fehlers. Aufgrund der implizit gegebenen Verknüpfung zwischen Testplan und Mustermenge ergeben sich weitreichende Synergieeffekte durch die Ausschöpfung mustermengenabhängiger Informationen. Die Verwendung von testmengenspezifischer Information im vorgestellten Algorithmus zeigt bei gleichbleibender Fehlererfassungsrate und Testdauer deutliche Einsparungen in der benötigten Verlustleistung. Das Verfahren wird an industriellen und Benchmark-Schaltungen mit bestehenden, überwiegend topologisch arbeitenden Verfahren verglichen.
BibTeX:
@inproceedings{ImhofWZLM2008,
  author = {Imhof, Michael E. and Wunderlich, Hans-Joachim and Zöllin, Christian and Leenstra, Jens and Maeding, Nicolas},
  title = {{Reduktion der Verlustleistung beim Selbsttest durch Verwendung testmengenspezifischer Information}},
  booktitle = {20th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'08)},
  year = {2008},
  pages = {137--141},
  keywords = {Reliability; Testing; Fault-Tolerance; CR B.8.1},
  abstract = {Der während des Selbsttests von Schaltungen mit deaktivierbaren Prüfpfaden verwendete Testplan entscheidet über die Verlustleistung während des Tests. Bestehende Verfahren zur Erzeugung des Testplans verwenden überwiegend topologische Information, zum Beispiel den Ausgangskegel eines Fehlers. Aufgrund der implizit gegebenen Verknüpfung zwischen Testplan und Mustermenge ergeben sich weitreichende Synergieeffekte durch die Ausschöpfung mustermengenabhängiger Informationen. Die Verwendung von testmengenspezifischer Information im vorgestellten Algorithmus zeigt bei gleichbleibender Fehlererfassungsrate und Testdauer deutliche Einsparungen in der benötigten Verlustleistung. Das Verfahren wird an industriellen und Benchmark-Schaltungen mit bestehenden, überwiegend topologisch arbeitenden Verfahren verglichen.}
}
49. Programmable Deterministic Built-in Self-test
Hakmi, A.-W., Wunderlich, H.-J., Zöllin, C., Glowatz, A., Schlöffel, J. and Hapke, F.
19th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'07), Erlangen, Germany, 11-13 March 2007, pp. 61-65
2007
 
Keywords: Reliability; Testing; Fault-Tolerance; CR B.8.1; Deterministic BIST; test data compression; reseeding
Abstract: In this paper, we propose a new programmable deterministic Built-In Self-Test (BIST) method that requires significantly lower storage for deterministric patterns than existing programmable methods and provides high flexibilily for test engineering in bolh internal and external test. Theoretical analysis suggests that significanlly more care bits can be encoded in the seed or a Linear Feedback Shift Register (LFSR) if a limited number of conflicting equations are ignored in the employed linear equation system. The ignored care bits are separately embedded into the LFSR pattern, but in contrast to bit-flipping BIST, the test set is not embedded by a synthesized logic function. Instead, this information is stored in memory using a special compression architecture. Experiments for benchmark circuits industrial designs demonstrate that the approach has considerably higher overall coding efficency than the existing methods.
BibTeX:
@inproceedings{HakmiWZGSH2007,
  author = {Hakmi, Abdul-Wahid and Wunderlich, Hans-Joachim and Zöllin, Christian and Glowatz, Andreas and Schlöffel, Jürgen and Hapke, Friedrich},
  title = {{Programmable Deterministic Built-in Self-test}},
  booktitle = {19th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'07)},
  year = {2007},
  pages = {61--65},
  keywords = {Reliability; Testing; Fault-Tolerance; CR B.8.1; Deterministic BIST; test data compression; reseeding},
  abstract = {In this paper, we propose a new programmable deterministic Built-In Self-Test (BIST) method that requires significantly lower storage for deterministric patterns than existing programmable methods and provides high flexibilily for test engineering in bolh internal and external test. Theoretical analysis suggests that significanlly more care bits can be encoded in the seed or a Linear Feedback Shift Register (LFSR) if a limited number of conflicting equations are ignored in the employed linear equation system. The ignored care bits are separately embedded into the LFSR pattern, but in contrast to bit-flipping BIST, the test set is not embedded by a synthesized logic function. Instead, this information is stored in memory using a special compression architecture. Experiments for benchmark circuits industrial designs demonstrate that the approach has considerably higher overall coding efficency than the existing methods.}
}
48. Adaptive Debug and Diagnosis Without Fault Dictionaries
Holst, S. and Wunderlich, H.-J.
19th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'07), Erlangen, Germany, 11-13 March 2007, pp. 82-86
2007
 
Keywords: Reliability; Testing; Fault-Tolerance; CR B.8.1
BibTeX:
@inproceedings{HolstW2007,
  author = {Holst, Stefan and Wunderlich, Hans-Joachim},
  title = {{Adaptive Debug and Diagnosis Without Fault Dictionaries}},
  booktitle = {19th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'07)},
  year = {2007},
  pages = {82--86},
  keywords = {Reliability; Testing; Fault-Tolerance; CR B.8.1}
}
47. An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy
Öhler, P., Hellebrand, S. and Wunderlich, H.-J.
19th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'07), Erlangen, Germany, 11-13 March 2007, pp. 56-60
2007
 
Keywords: Reliability; Testing; Fault-Tolerance; CR B.8.1
BibTeX:
@inproceedings{OehlerHW2007,
  author = {Öhler, Phillip and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
  title = {{An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy}},
  booktitle = {19th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'07)},
  year = {2007},
  pages = {56--60},
  keywords = {Reliability; Testing; Fault-Tolerance; CR B.8.1}
}
46. Software-basierender Selbsttest von Prozessoren bei beschränkter Verlustleistung
Zhou, J. and Wunderlich, H.-J.
18th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'06), Titisee, Germany, 12-14 March 2006, pp. 95-100
2006
 
Keywords: Reliability; Testing; Fault-Tolerance; CR B.8.1
Abstract: Der softwarebasierende Selbsttest von Prozessoren (SBST) bietet zahlreiche Vorteile wie den Verzicht auf teure Testautomaten, die autonome Testdurchführung während der Wartung oder die Möglichkeit, einen Initialisierungstest für das Gesamtsystem zu implementieren. In dieser Arbeit wird eine strukturbasierte SBST Methode vorgestellt, die bezüglich Energieaufnahme, durchschnittlicher Verlustleistung, Testlänge und Fehlerüberdeckung gleichzeitig optimiert.
BibTeX:
@inproceedings{ZhouW2006a,
  author = {Zhou, Jun and Wunderlich, Hans-Joachim},
  title = {{Software-basierender Selbsttest von Prozessoren bei beschränkter Verlustleistung}},
  booktitle = {18th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'06)},
  year = {2006},
  pages = {95--100},
  keywords = {Reliability; Testing; Fault-Tolerance; CR B.8.1},
  abstract = {Der softwarebasierende Selbsttest von Prozessoren (SBST) bietet zahlreiche Vorteile wie den Verzicht auf teure Testautomaten, die autonome Testdurchführung während der Wartung oder die Möglichkeit, einen Initialisierungstest für das Gesamtsystem zu implementieren. In dieser Arbeit wird eine strukturbasierte SBST Methode vorgestellt, die bezüglich Energieaufnahme, durchschnittlicher Verlustleistung, Testlänge und Fehlerüberdeckung gleichzeitig optimiert.}
}
45. BIST Power Reduction Using Scan-Chain Disable in the Cell Processor
Zöllin, C., Wunderlich, H.-J., Maeding, N. and Leenstra, J.
18th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'06), Titisee, Germany, 12-14 March 2006, pp. 101-103
2006
 
Keywords: Reliability; Testing; Fault-Tolerance; CR B.8.1
Abstract: Built-in self test is a major part of the manufacturing test procedure for the Cell Processor. However, pseudo random patterns cause a high switching activity which is not effectively reduced by dynamic clock gating.

Therefore, the test power envelope is expected to be so high, that the scan-speed has to be reduced significantly, thus extending test time.

We propose a test power reduction method that uses scan-gating with Logic BIST.
In LBIST, except for the first dozens of patterns, patterns that detect additional faults (effective patterns) are very scarce and often less than one pattern in a hundred detects new faults. In most cases, such an effective pattern even requires only a reduced set of the available scan chains to detect the fault and all don't-care scan chains can be disabled, therefore significantly reducing test power.

BibTeX:
@inproceedings{ZoellWML2006a,
  author = {Zöllin, Christian and Wunderlich, Hans-Joachim and Maeding, Nicolas and Leenstra, Jens},
  title = {{BIST Power Reduction Using Scan-Chain Disable in the Cell Processor}},
  booktitle = {18th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'06)},
  year = {2006},
  pages = {101--103},
  keywords = {Reliability; Testing; Fault-Tolerance; CR B.8.1},
  abstract = {Built-in self test is a major part of the manufacturing test procedure for the Cell Processor. However, pseudo random patterns cause a high switching activity which is not effectively reduced by dynamic clock gating.

Therefore, the test power envelope is expected to be so high, that the scan-speed has to be reduced significantly, thus extending test time.

We propose a test power reduction method that uses scan-gating with Logic BIST.
In LBIST, except for the first dozens of patterns, patterns that detect additional faults (effective patterns) are very scarce and often less than one pattern in a hundred detects new faults. In most cases, such an effective pattern even requires only a reduced set of the available scan chains to detect the fault and all don't-care scan chains can be disabled, therefore significantly reducing test power.} }

44. Software-basierender Selbsttest von Prozessorkernen unter Verlustleistungsbeschränkung
Zhou, J. and Wunderlich, H.-J.
INFORMATIK 2005 - Informatik LIVE! Band 1, Beiträge der 35. Jahrestagung der Gesellschaft für Informatik e.V. (GI), Bonn, Germany, 19-22 September 2005, pp. 441-441
2005
 
Abstract: Software-basierender Selbsttest (SBST) von Prozessoren wird schon seit Jahrzehnten
verwendet, da er erhebliche Vorteile bietet, wie z. B. die Wiederverwendbarkeit in allen
Stadien des Lebenszykluses des Systems, der Verzicht auf kostspielige Tester und
geringe oder sogar gar kein Aufwand für „Design for Test“. Die größten Nachteile sind
die unzureichende strukturelle Fehlerabdeckung sowie relativ lange
Testanwendungszeiten. In jüngster Zeit wurden große Fortschritte bei der Kombination
der Erzeugung von strukturellen Testmustern und SBST gemacht. Dieser Ansatz macht
das „Peak Power Problem” weniger dringend, da der Test im Systemmodus und nicht in
einem speziellen Testmodus durchgeführt wird, der zu einer erhöhten Schaltaktivität
führt. Der durchschnittliche Energiebedarf muss jedoch immer noch optimiert werden.
Geringer Speicherbedarf, kurze Ausführungzeiten sowie eine hohen Fehlerabdeckung
sind für den effizienten Einsatz der SBST Methode unerlässlich.

In diesem Beitrag wird eine strukturelle SBST Methode präsentiert, welche diese drei
Parameter gleichzeitig optimiert. Zuerst stellen wir einen Algorithmus vor, mit dem ein
effektives Testprogramm mit minimalem menschlichem Eingreifen synthetisiert werden
kann. Die konventionellen Techniken zur Energieoptimierung der Software können an
dieser Stelle nicht angewandt werden, da mit ihnen das Ziel verfolgt wird, die Semantik
eines Programms beizubehalten, während bei SBST hingegen die strukturelle
Fehlerabdeckung beibehalten werden muss. Um dieser speziellen Anforderung gerecht
zu werden, stellen wir anschließend unseren Optimierungsprozess vor, der das Verhalten
des eingebetteten Tests analysiert, um dieselbe Fehlerüberdeckung zu erhalten, und
dabei Freiheitsgrade bei der Befehlsreihenfolge und Don’t Cares verwendet , um Energie
zu sparen. Schließlich wird die Methode auf Gatterebene validiert. Den Ergebnissen
zufolge kann die Energie um 40% und die Testdauer um 30% reduziert werden ohne an
Fehlerabdeckung einzubüßen.

BibTeX:
@inproceedings{ZhouW2005,
  author = {Zhou, Jun and Wunderlich, Hans-Joachim},
  title = {{Software-basierender Selbsttest von Prozessorkernen unter Verlustleistungsbeschränkung}},
  booktitle = {INFORMATIK 2005 - Informatik LIVE! Band 1, Beiträge der 35. Jahrestagung der Gesellschaft für Informatik e.V. (GI)},
  publisher = {Köllen Druck+Verlag GmbH},
  year = {2005},
  volume = {P-67},
  pages = {441--441},
  abstract = {Software-basierender Selbsttest (SBST) von Prozessoren wird schon seit Jahrzehnten
verwendet, da er erhebliche Vorteile bietet, wie z. B. die Wiederverwendbarkeit in allen
Stadien des Lebenszykluses des Systems, der Verzicht auf kostspielige Tester und
geringe oder sogar gar kein Aufwand für „Design for Test“. Die größten Nachteile sind
die unzureichende strukturelle Fehlerabdeckung sowie relativ lange
Testanwendungszeiten. In jüngster Zeit wurden große Fortschritte bei der Kombination
der Erzeugung von strukturellen Testmustern und SBST gemacht. Dieser Ansatz macht
das „Peak Power Problem” weniger dringend, da der Test im Systemmodus und nicht in
einem speziellen Testmodus durchgeführt wird, der zu einer erhöhten Schaltaktivität
führt. Der durchschnittliche Energiebedarf muss jedoch immer noch optimiert werden.
Geringer Speicherbedarf, kurze Ausführungzeiten sowie eine hohen Fehlerabdeckung
sind für den effizienten Einsatz der SBST Methode unerlässlich.

In diesem Beitrag wird eine strukturelle SBST Methode präsentiert, welche diese drei
Parameter gleichzeitig optimiert. Zuerst stellen wir einen Algorithmus vor, mit dem ein
effektives Testprogramm mit minimalem menschlichem Eingreifen synthetisiert werden
kann. Die konventionellen Techniken zur Energieoptimierung der Software können an
dieser Stelle nicht angewandt werden, da mit ihnen das Ziel verfolgt wird, die Semantik
eines Programms beizubehalten, während bei SBST hingegen die strukturelle
Fehlerabdeckung beibehalten werden muss. Um dieser speziellen Anforderung gerecht
zu werden, stellen wir anschließend unseren Optimierungsprozess vor, der das Verhalten
des eingebetteten Tests analysiert, um dieselbe Fehlerüberdeckung zu erhalten, und
dabei Freiheitsgrade bei der Befehlsreihenfolge und Don’t Cares verwendet , um Energie
zu sparen. Schließlich wird die Methode auf Gatterebene validiert. Den Ergebnissen
zufolge kann die Energie um 40% und die Testdauer um 30% reduziert werden ohne an
Fehlerabdeckung einzubüßen.} }

43. Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST
Engelke, P., Gherman, V., Polian, I., Tang, Y., Wunderlich, H.-J. and Becker, B.
17th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'05), Innsbruck, Austria, 27 February-1 March 2005, pp. 16-20
2005
 
Keywords: Reliability; Testing; Fault-Tolerance; CR B.8.1; Test Tradeoffs; Logic BIST; Defect Coverage; Resistive Bridging Faults
Abstract: For the first time, we study the coverage of non-target defects for Deterministic Logic BIST (DLBIST) architecture. We consider several DLBIST implementation options that result in test sequences of different lengths. Resistive bridging faults are used as a surrogate of non-target defects. Experimental data obtained for largest ISCAS benchmarks suggests that, although DLBIST always guarantees complete stuck-at coverage, test sequence length does influence the non-target defect detection capabilities. For circuits with a large fraction of random-pattern resistant faults, the embedded deterministic patterns as well as a sufficient amount of random patterns are both demonstrated to be essential for non-target defect detection. It turns out, moreover, that area cost is lower for DLBIST solutions with longer test sequences, due to additional degrees of freedom for the embedding procedure and a lower number of faults undetected by pseudorandom patterns. This implies that DLBIST is particularly effective in covering non-target defects.
BibTeX:
@inproceedings{EngelGPTWB2005a,
  author = {Engelke, Piet and Gherman, Valentin and Polian, Ilian and Tang, Yuyi and Wunderlich, Hans-Joachim and Becker, Bernd},
  title = {{Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST}},
  booktitle = {17th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'05)},
  year = {2005},
  pages = {16--20},
  keywords = {Reliability; Testing; Fault-Tolerance; CR B.8.1; Test Tradeoffs; Logic BIST; Defect Coverage; Resistive Bridging Faults},
  abstract = {For the first time, we study the coverage of non-target defects for Deterministic Logic BIST (DLBIST) architecture. We consider several DLBIST implementation options that result in test sequences of different lengths. Resistive bridging faults are used as a surrogate of non-target defects. Experimental data obtained for largest ISCAS benchmarks suggests that, although DLBIST always guarantees complete stuck-at coverage, test sequence length does influence the non-target defect detection capabilities. For circuits with a large fraction of random-pattern resistant faults, the embedded deterministic patterns as well as a sufficient amount of random patterns are both demonstrated to be essential for non-target defect detection. It turns out, moreover, that area cost is lower for DLBIST solutions with longer test sequences, due to additional degrees of freedom for the embedding procedure and a lower number of faults undetected by pseudorandom patterns. This implies that DLBIST is particularly effective in covering non-target defects.}
}
42. DLBIST for Delay Testing
Garbers, M., Schlöffel, J., Gherman, V. and Wunderlich, H.-J.
17th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'05), Innsbruck, Austria, 27 February-1 March 2005, pp. 39-43
2005
 
Keywords: Reliability; Testing; Fault-Tolerance; CR B.8.1; Deterministic logic BIST; delay test
Abstract: Due to its inherent support for at-speed test, BIST is an attractive approach to test delay faults. Deterministic logic BIST (DLBIST) is a technique which was successfully applied to enhance the quality of BIST in the case of stuck-at test. The test of delay faults requires the application of pattern pairs. Consequently, delay faults have a lower random pattern testability than stuck-at faults and this increases the need for a DLBIST scheme. On the other hand, a DLBIST solution is expected to require a larger mapping effort and logic overhead than in the case of stuck-at test.

In this paper, we present the extension of a DLBIST scheme which becomes available for the test of both delay (transition) faults and stuck-at faults. Functional justification is used to generate the pattern pairs required by the target delay faults. We investigate the efficiency of the extended scheme in the case of some industrial benchmarks.

BibTeX:
@inproceedings{GarbeSGW2005,
  author = {Garbers, Michael and Schlöffel, Jürgen and Gherman, Valentin and Wunderlich, Hans-Joachim},
  title = {{DLBIST for Delay Testing}},
  booktitle = {17th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'05)},
  year = {2005},
  pages = {39--43},
  keywords = {Reliability; Testing; Fault-Tolerance; CR B.8.1; Deterministic logic BIST; delay test},
  abstract = {Due to its inherent support for at-speed test, BIST is an attractive approach to test delay faults. Deterministic logic BIST (DLBIST) is a technique which was successfully applied to enhance the quality of BIST in the case of stuck-at test. The test of delay faults requires the application of pattern pairs. Consequently, delay faults have a lower random pattern testability than stuck-at faults and this increases the need for a DLBIST scheme. On the other hand, a DLBIST solution is expected to require a larger mapping effort and logic overhead than in the case of stuck-at test.

In this paper, we present the extension of a DLBIST scheme which becomes available for the test of both delay (transition) faults and stuck-at faults. Functional justification is used to generate the pattern pairs required by the target delay faults. We investigate the efficiency of the extended scheme in the case of some industrial benchmarks.} }

41. Implementing a Scheme for External Deterministic Self-Test
Hakmi, A.-W., Wunderlich, H.-J., Gherman, V., Garbers, M. and Schlöffel, J.
17th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'05), Innsbruck, Austria, 27 February-1 March 2005, pp. 27-31
2005
 
Keywords: Reliability; Testing; Fault-Tolerance; CR B.8.1; Deterministic self-test; external BIST; test resource partitioning; test data compression
Abstract: A new method for test resource partitioning is introduced which keeps the design-for-test logic independent of the test set and moves the test pattern dependent information to an external, programmable chip. The scheme includes a new decompression method for a fast and efficient communication between the external test chip and the circuit under test. The
hardware costs on chip are significantly lower compared with a deterministic BIST scheme while the test application time is still in the same range. The proposed scheme is fully programmable, flexible and can be reused at board level for testing in the field.
BibTeX:
@inproceedings{HakmiWGGS2005a,
  author = {Hakmi, Abdul-Wahid and Wunderlich, Hans-Joachim and Gherman, Valentin and Garbers, Michael and Schlöffel, Jürgen},
  title = {{Implementing a Scheme for External Deterministic Self-Test}},
  booktitle = {17th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'05)},
  year = {2005},
  pages = {27--31},
  keywords = {Reliability; Testing; Fault-Tolerance; CR B.8.1; Deterministic self-test; external BIST; test resource partitioning; test data compression},
  abstract = {A new method for test resource partitioning is introduced which keeps the design-for-test logic independent of the test set and moves the test pattern dependent information to an external, programmable chip. The scheme includes a new decompression method for a fast and efficient communication between the external test chip and the circuit under test. The
hardware costs on chip are significantly lower compared with a deterministic BIST scheme while the test application time is still in the same range. The proposed scheme is fully programmable, flexible and can be reused at board level for testing in the field.} }
40. X-Masking During Logic BIST and its Impact on Defect Coverage
Tang, Y., Wunderlich, H.-J., Vranken, H., Hapke, F., Wittke, M., Engelke, P., Polian, I. and Becker, B.
5th IEEE International Workshop on Test Resource Partitioning (TRP'04), Napa Valley, California, USA, 28-29 April 2004, pp. 442-451
2004
 
Keywords: Reliability; Testing; Fault-Tolerance; CR B.8.1; X-Masking; Logic BIST; Defect Coverage; Resistive Bridging Faults
Abstract: We present a technique for making a circuit ready for Logic BIST by masking unknown values at its outputs. In order to keep the area overhead low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.
BibTeX:
@inproceedings{TangWVHWEPB2004,
  author = {Tang, Yuyi and Wunderlich, Hans-Joachim and Vranken, Harald and Hapke, Friedrich and Wittke, Michael and Engelke, Piet and Polian, Ilian and Becker, Bernd},
  title = {{X-Masking During Logic BIST and its Impact on Defect Coverage}},
  booktitle = {5th IEEE International Workshop on Test Resource Partitioning (TRP'04)},
  year = {2004},
  pages = {442--451},
  keywords = {Reliability; Testing; Fault-Tolerance; CR B.8.1; X-Masking; Logic BIST; Defect Coverage; Resistive Bridging Faults},
  abstract = {We present a technique for making a circuit ready for Logic BIST by masking unknown values at its outputs. In order to keep the area overhead low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.}
}
39. EuNICE-Test: European network for test education
Novak, F., Biasizzo, A., Bertrand, Y., Flottes, M.-L., Balado, L., Figueras, J., Di Carlo, S., Prinetto, P., Pricopi, N. and Wunderlich, H.-J.
IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'04), Tatranska Lomnica, Slovakia, 18-21 April 2004
2004
 
Abstract: The paper deals with a European experience of education in industrial test of ICs and SoCs using remote testing facilities. The project addresses the problem of the shortage in microelectronics engineers aware with the new challenge of testing mixed-signal SoCs for multimedia/telecom market. It aims at providing test training facilities at a European scale in both initial and continuing education contexts. This is done by allowing the academic and industrial partners of the consortium to train engineers using the common test resources center (CRTC)
hosted by LIRMM (Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, France). CRTC test tools include up-to-date/high-tech testers that are fully representative of real industrial testers as used on production testfloors. At the end of the project, it is aimed at reaching a cruising speed of about 16 trainees per year per center. Each trainee will have attend at least one one-week training using the remote test facilities of CRTC.
BibTeX:
@inproceedings{NovakBBFBFDPPW2004,
  author = {Novak, Frank and Biasizzo, Anton and Bertrand, Yves and Flottes, Marie-Lise and Balado, Luz and Figueras, Joan and Di Carlo, Stefano and Prinetto, Paolo and Pricopi, Nicoleta and Wunderlich, Hans-Joachim},
  title = {{EuNICE-Test: European network for test education}},
  booktitle = {IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'04)},
  year = {2004},
  abstract = {The paper deals with a European experience of education in industrial test of ICs and SoCs using remote testing facilities. The project addresses the problem of the shortage in microelectronics engineers aware with the new challenge of testing mixed-signal SoCs for multimedia/telecom market. It aims at providing test training facilities at a European scale in both initial and continuing education contexts. This is done by allowing the academic and industrial partners of the consortium to train engineers using the common test resources center (CRTC)
hosted by LIRMM (Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, France). CRTC test tools include up-to-date/high-tech testers that are fully representative of real industrial testers as used on production testfloors. At the end of the project, it is aimed at reaching a cruising speed of about 16 trainees per year per center. Each trainee will have attend at least one one-week training using the remote test facilities of CRTC.} }
38. Masking X-Responses During Deterministic Self-Test
Tang, Y., Wunderlich, H.-J., Vranken, H., Hapke, F., Garbers, M. and Schlöffel, J.
16th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'04), Dresden, Germany, 29 February-2 March 2004, pp. 13-19
2004
 
Keywords: Reliability; Testing; Fault-Tolerance; CR B.8.1
BibTeX:
@inproceedings{TangWVHGS2004,
  author = {Tang, Yuyi and Wunderlich, Hans-Joachim and Vranken, Harald and Hapke, Friedrich and Garbers, Michael and Schlöffel, Jürgen},
  title = {{Masking X-Responses During Deterministic Self-Test}},
  booktitle = {16th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'04)},
  year = {2004},
  pages = {13--19},
  keywords = {Reliability; Testing; Fault-Tolerance; CR B.8.1}
}
37. Digital, Memory and Mixed-Signal Test Engineering Education: 5 centers of competence in Europe
Novak, F., Biasizzo, A., Bertrand, Y., Flottes, M.-L., Figueras, J., Di Carlo, S., Prinetto, P., Pricopi, N. and Wunderlich, H.-J.
IEEE International Workshop on Electronic Design, Test and Applications (DELTA'04), Perth, Australia, 28-30 January 2004, pp. 135-140
2004
 
Abstract: The launching of the EuNICE-Test project was announced two years ago at the first DELTA Conference [1]. This project is now completed and it is the objective of the present paper to describe the project actions and outcomes. The original idea was to build a long-lasting European Network for test engineering education using both test resource mutualisation and
remote experiment. This objective is fully fulfilled and we have now in Europe five centres of competence that are able to deliver high-level and high-specialized training courses in the field of test engineering using a high-performing industrial ATE. All the centres propose training courses on digital testing, three of them propose mixed-signal trainings and three of them propose
memory trainings. Taking into account the demand in test engineering, the network is planned to continue in a stand alone mode after project end. Nevertheless a new European proposal with several new partners and new test lessons is under construction.
BibTeX:
@inproceedings{NovakBBFFDPPW2004,
  author = {Novak, Frank and Biasizzo, Anton and Bertrand, Yves and Flottes, Marie-Lise and Figueras, Joan and Di Carlo, Stefano and Prinetto, Paolo and Pricopi, Nicoleta and Wunderlich, Hans-Joachim},
  title = {{Digital, Memory and Mixed-Signal Test Engineering Education: 5 centers of competence in Europe}},
  booktitle = {IEEE International Workshop on Electronic Design, Test and Applications (DELTA'04)},
  year = {2004},
  pages = {135--140},
  abstract = {The launching of the EuNICE-Test project was announced two years ago at the first DELTA Conference [1]. This project is now completed and it is the objective of the present paper to describe the project actions and outcomes. The original idea was to build a long-lasting European Network for test engineering education using both test resource mutualisation and
remote experiment. This objective is fully fulfilled and we have now in Europe five centres of competence that are able to deliver high-level and high-specialized training courses in the field of test engineering using a high-performing industrial ATE. All the centres propose training courses on digital testing, three of them propose mixed-signal trainings and three of them propose
memory trainings. Taking into account the demand in test engineering, the network is planned to continue in a stand alone mode after project end. Nevertheless a new European proposal with several new partners and new test lessons is under construction.} }
36. Implementation of Test Engineering Training using Remote ATE: A First Experience at European Level
Bertrand, Y., Flottes, M.-L., Pricopi, N. and Wunderlich, H.-J.
15th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'03), Timmendorfer Strand, Germany, 23-25 March 2003
2003
 
Keywords: Reliability; Testing; Fault-Tolerance; CR B.8.1
BibTeX:
@inproceedings{BertrFPW2003,
  author = {Bertrand, Yves and Flottes, Marie-Lise and Pricopi, Nicoleta and Wunderlich, Hans-Joachim},
  title = {{Implementation of Test Engineering Training using Remote ATE: A First Experience at European Level}},
  booktitle = {15th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'03)},
  year = {2003},
  keywords = {Reliability; Testing; Fault-Tolerance; CR B.8.1}
}
35. Power Conscious BIST Approaches
Virazel, A. and Wunderlich, H.-J.
3. VIVA Schwerpunkt-Kolloquium, Chemnitz, Germany, 18-19 March 2002, pp. 128-135
2002
 
Abstract: The System-On-Chip (SOC) revolution has brought some new challenges to both design and test engineers. The most important challenges of today’s VLSI systems testing are linked to test cost, defect coverage and power dissipation. Implementing a self-testable system may reduce test costs as expensive external high performance test equipment is not required and it may increase defect coverage as testing is performed at system speed. Unfortunately, the classic BIST approaches lead to a significant increase of power consumption compared to the system mode and even compared to external testing. The paper will review required changes to be applied to classic BIST techniques for power reduction. A recently developed new BIST approach called functional BIST is introduced and its consequences for power dissipation are discussed.
BibTeX:
@inproceedings{VirazW2002,
  author = {Virazel, Arnaud and Wunderlich, Hans-Joachim},
  title = {{Power Conscious BIST Approaches}},
  booktitle = {3. VIVA Schwerpunkt-Kolloquium},
  publisher = {n.n.},
  year = {2002},
  pages = {128--135},
  abstract = {The System-On-Chip (SOC) revolution has brought some new challenges to both design and test engineers. The most important challenges of today’s VLSI systems testing are linked to test cost, defect coverage and power dissipation. Implementing a self-testable system may reduce test costs as expensive external high performance test equipment is not required and it may increase defect coverage as testing is performed at system speed. Unfortunately, the classic BIST approaches lead to a significant increase of power consumption compared to the system mode and even compared to external testing. The paper will review required changes to be applied to classic BIST techniques for power reduction. A recently developed new BIST approach called functional BIST is introduced and its consequences for power dissipation are discussed.}
}
34. Reusing Scan Chains for Test Pattern Decompression
Dorsch, R. and Wunderlich, H.-J.
European Test Workshop (ETW'01), Stockholm, Sweden, 29 May-1 June 2001, pp. 307-315
2001
 
Keywords: System-on-a-Chip; Embedded Test; BIST
Abstract: The paper presents a method for testing a system-on-achip by using a compressed representation of the patterns on an external tester. The patterns for a certain core under
test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper, while the mission logic is untouched.
Storage and bandwidth requirements for the ATE are reduced significantly.
BibTeX:
@inproceedings{DorscW2001b,
  author = {Dorsch, Rainer and Wunderlich, Hans-Joachim},
  title = {{Reusing Scan Chains for Test Pattern Decompression}},
  booktitle = {European Test Workshop (ETW'01)},
  year = {2001},
  pages = {307--315},
  keywords = {System-on-a-Chip; Embedded Test; BIST},
  abstract = {The paper presents a method for testing a system-on-achip by using a compressed representation of the patterns on an external tester. The patterns for a certain core under
test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper, while the mission logic is untouched.
Storage and bandwidth requirements for the ATE are reduced significantly.} }
33. Using Mission Logic for Embedded Testing
Dorsch, R. and Wunderlich, H.-J.
1st IEEE International Workshop on Test Resource Partitioning (TRP'00), Atlantic City, New Jersey, USA, 5-6 October 2000
2000
 
Abstract: Testing logic cores of a system-on-a-chip causes a high test data volume which has to be stored on the external automatic test equipement (ATE), a high bandwidth requirement between ATE and the chip under test implying the need for high-speed ATE. This paper reduces these requirements by reusing embedded cores during test mode as embedded testers. Hard, firm, and soft cores may be reused, since only the functionality of the core in system mode is used.
BibTeX:
@inproceedings{DorscW2000b,
  author = {Dorsch, Rainer and Wunderlich, Hans-Joachim},
  title = {{Using Mission Logic for Embedded Testing}},
  booktitle = {1st IEEE International Workshop on Test Resource Partitioning (TRP'00)},
  year = {2000},
  abstract = {Testing logic cores of a system-on-a-chip causes a high test data volume which has to be stored on the external automatic test equipement (ATE), a high bandwidth requirement between ATE and the chip under test implying the need for high-speed ATE. This paper reduces these requirements by reusing embedded cores during test mode as embedded testers. Hard, firm, and soft cores may be reused, since only the functionality of the core in system mode is used.}
}
32. Application of Deterministic Logic BIST on Industrial Circuits
Kiefer, G., Vranken, H., Marinissen, E.J. and Wunderlich, H.-J.
IEEE European Test Workshop (ETW'00), Informal digest, Cascais, Portugal, 23-26 May 2000, pp. 99-104
2000
 
Abstract: We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5%-15%. It is demonstrated that a tradeoff is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized.
BibTeX:
@inproceedings{KiefeVMW2000a,
  author = {Kiefer, Gundolf and Vranken, Harald and Marinissen, Erik Jan and Wunderlich, Hans-Joachim},
  title = {{Application of Deterministic Logic BIST on Industrial Circuits}},
  booktitle = {IEEE European Test Workshop (ETW'00), Informal digest},
  year = {2000},
  pages = {99--104},
  abstract = {We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5%-15%. It is demonstrated that a tradeoff is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized.}
}
31. Synthese effizienter Testmustergeneratoren für den deterministischen funktionalen Selbsttest
Dorsch, R. and Wunderlich, H.-J.
12th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'00), Grassau, Germany, 19-21 March 2000, pp. 1-7
2000
 
Abstract: Der deterministische funktionale Selbsttest vereint die Vorteile des funktionalen und des deterministischen strukturellen Tests. Der deterministische funktionale Selbsttest wird wie der funktionale Test mit Systemgeschwindigkeit durchgeführt, beeinflußt die Geschwindigkeit im Systembetrieb nicht und erkennt Verzögerungsfehler. Zudem besitzt er die hohe Fehlerüberdeckung des deterministischen strukturellen Tests. Dies wird erreicht, indem funktionale Einheiten auf dem System so gesteuert werden, daß berechnete deterministische Testvektoren erzeugt werden. Wir stellen eine neue Methode zur Steuerung der funktionalen Einheiten vor, die einen deterministischen Mustersatz stärker komprimiert als bisher bekannte Verfahren.
BibTeX:
@inproceedings{DorscW2000a,
  author = {Dorsch, Rainer and Wunderlich, Hans-Joachim},
  title = {{Synthese effizienter Testmustergeneratoren für den deterministischen funktionalen Selbsttest}},
  booktitle = {12th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'00)},
  year = {2000},
  volume = {4},
  pages = {1--7},
  abstract = {Der deterministische funktionale Selbsttest vereint die Vorteile des funktionalen und des deterministischen strukturellen Tests. Der deterministische funktionale Selbsttest wird wie der funktionale Test mit Systemgeschwindigkeit durchgeführt, beeinflußt die Geschwindigkeit im Systembetrieb nicht und erkennt Verzögerungsfehler. Zudem besitzt er die hohe Fehlerüberdeckung des deterministischen strukturellen Tests. Dies wird erreicht, indem funktionale Einheiten auf dem System so gesteuert werden, daß berechnete deterministische Testvektoren erzeugt werden. Wir stellen eine neue Methode zur Steuerung der funktionalen Einheiten vor, die einen deterministischen Mustersatz stärker komprimiert als bisher bekannte Verfahren.}
}
30. Synthesis of Efficient Test Pattern Generators for Deterministic Functional BIST
Dorsch, R. and Wunderlich, H.-J.
7th IEEE International Test Synthesis Workshop, Santa Barbara, California, USA March 2000
2000
 
Abstract: Der deterministische funktionale Selbsttest vereint die Vorteile des funktionalen und des deterministischen strukturellen Tests. Der deterministische funktionale Selbsttest wird wie der funktionale Test mit Systemgeschwindigkeit durchgeführt, beeinflußt die Geschwindigkeit im Systembetrieb nicht und erkennt Verzögerungsfehler. Zudem besitzt er die hohe Fehlerüberdeckung des deterministischen strukturellen Tests. Dies wird erreicht, indem funktionale Einheiten auf dem System so gesteuert werden, daß berechnete deterministische Testvektoren erzeugt werden. Wir stellen eine neue Methode zur Steuerung der funktionalen Einheiten vor, die einen deterministischen Mustersatz stärker komprimiert als bisher bekannte Verfahren.
BibTeX:
@inproceedings{DorscW2000,
  author = {Dorsch, Rainer and Wunderlich, Hans-Joachim},
  title = {{Synthesis of Efficient Test Pattern Generators for Deterministic Functional BIST}},
  booktitle = {7th IEEE International Test Synthesis Workshop},
  year = {2000},
  abstract = {Der deterministische funktionale Selbsttest vereint die Vorteile des funktionalen und des deterministischen strukturellen Tests. Der deterministische funktionale Selbsttest wird wie der funktionale Test mit Systemgeschwindigkeit durchgeführt, beeinflußt die Geschwindigkeit im Systembetrieb nicht und erkennt Verzögerungsfehler. Zudem besitzt er die hohe Fehlerüberdeckung des deterministischen strukturellen Tests. Dies wird erreicht, indem funktionale Einheiten auf dem System so gesteuert werden, daß berechnete deterministische Testvektoren erzeugt werden. Wir stellen eine neue Methode zur Steuerung der funktionalen Einheiten vor, die einen deterministischen Mustersatz stärker komprimiert als bisher bekannte Verfahren.}
}
29. Deterministic BIST with Partial Scan
Kiefer, G. and Wunderlich, H.-J.
IEEE European Test Workshop (ETW'99), Constance, Germany, 25-28 May 1999, pp. 110-116
1999
 
Abstract: An efficient deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum number of flipflops to be scannable so that the remaining circuit has a pipeline-like structure. Experiments show that scanning less flipflops may even decrease the hardware overhead for the on-chip pattern generator besides the classical advantages of partial scan such as less impact on the system performance and less hardware overhead.
BibTeX:
@inproceedings{KiefeW1999b,
  author = {Kiefer, Gundolf and Wunderlich, Hans-Joachim},
  title = {{Deterministic BIST with Partial Scan}},
  booktitle = {IEEE European Test Workshop (ETW'99)},
  year = {1999},
  pages = {110--116},
  abstract = {An efficient deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum number of flipflops to be scannable so that the remaining circuit has a pipeline-like structure. Experiments show that scanning less flipflops may even decrease the hardware overhead for the on-chip pattern generator besides the classical advantages of partial scan such as less impact on the system performance and less hardware overhead.}
}
28. Exploiting Symmetries to Speed Up Transparent BIST
Hellebrand, S., Wunderlich, H.-J. and Yarmolik, V.N.
11th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'99), Potsdam, Germany, 28 February-3 March 1999, pp. 12-15
1999
 
BibTeX:
@inproceedings{HelleWY1999,
  author = {Hellebrand, Sybille and Wunderlich, Hans-Joachim and Yarmolik, Vyacheslav N.},
  title = {{Exploiting Symmetries to Speed Up Transparent BIST}},
  booktitle = {11th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'99)},
  year = {1999},
  pages = {12--15}
}
27. Minimum Scan Insertion for Generating Pipeline-Structured Modules
Kiefer, G. and Wunderlich, H.-J.
11th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'99), Potsdam, Germany, 28 February-3 March 1999, pp. 30-33
1999
 
BibTeX:
@inproceedings{KiefeW1999,
  author = {Kiefer, Gundolf and Wunderlich, Hans-Joachim},
  title = {{Minimum Scan Insertion for Generating Pipeline-Structured Modules}},
  booktitle = {11th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'99)},
  year = {1999},
  pages = {30--33}
}
26. Low-Power Serial Built-In Self Test
Hertwig, A. and Wunderlich, H.-J.
IEEE European Test Workshop (ETW'98), Sitges, Barcelona, Spain, 27-29 May 1998, pp. 51
1998
 
BibTeX:
@inproceedings{HertwW1998,
  author = {Hertwig, Andre and Wunderlich, Hans-Joachim},
  title = {{Low-Power Serial Built-In Self Test}},
  booktitle = {IEEE European Test Workshop (ETW'98)},
  year = {1998},
  pages = {51}
}
25. Deterministic BIST with Multiple Scan Chains
Kiefer, G. and Wunderlich, H.-J.
IEEE European Test Workshop (ETW'98), Sitges, Barcelona, Spain, 27-29 May 1998, pp. 39-43
1998
 
Keywords: deterministic scan-based BIST; multiple scan paths; parallel scan
Abstract: A deterministic BIST scheme for circuits with multiple scan paths is presented. A procedure is described for synthesizing a pattern generator which stimulates all scan chains simultaneously and guarantees complete fault coverage.
The new scheme may require less chip area than a classical LFSR-based approach while better or even complete fault coverage is obtained at the same time.
BibTeX:
@inproceedings{KiefeW1998a,
  author = {Kiefer, Gundolf and Wunderlich, Hans-Joachim},
  title = {{Deterministic BIST with Multiple Scan Chains}},
  booktitle = {IEEE European Test Workshop (ETW'98)},
  year = {1998},
  pages = {39--43},
  keywords = {deterministic scan-based BIST; multiple scan paths; parallel scan},
  abstract = {A deterministic BIST scheme for circuits with multiple scan paths is presented. A procedure is described for synthesizing a pattern generator which stimulates all scan chains simultaneously and guarantees complete fault coverage.
The new scheme may require less chip area than a classical LFSR-based approach while better or even complete fault coverage is obtained at the same time.} }
24. Efficient Consistency Checking for Embedded Memories
Yarmolik, V.N., Hellebrand, S. and Wunderlich, H.-J.
5th IEEE International Test Synthesis Workshop, Santa Barbara, California, USA March 1998
1998
 
BibTeX:
@inproceedings{YarmoHW1998,
  author = {Yarmolik, Vyacheslav N. and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
  title = {{Efficient Consistency Checking for Embedded Memories}},
  booktitle = {5th IEEE International Test Synthesis Workshop},
  year = {1998}
}
23. Efficient Consistency Checking for Embedded Memories
Yarmolik, V.N., Hellebrand, S. and Wunderlich, H.-J.
10th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'98), Herrenberg, Germany March 1998
1998
 
BibTeX:
@inproceedings{YarmoHW1998a,
  author = {Yarmolik, Vyacheslav N. and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
  title = {{Efficient Consistency Checking for Embedded Memories}},
  booktitle = {10th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'98)},
  year = {1998},
  volume = {4},
  number = {3}
}
22. Pattern Selection for Low-Power Serial Built-In Self Test
Zelleröhr, M., Hertwig, A. and Wunderlich, H.-J.
5th IEEE International Test Synthesis Workshop, Santa Barbara, California, USA March 1998
1998
 
BibTeX:
@inproceedings{ZelleHW1998,
  author = {Zelleröhr, M. and Hertwig, Andre and Wunderlich, Hans-Joachim},
  title = {{Pattern Selection for Low-Power Serial Built-In Self Test}},
  booktitle = {5th IEEE International Test Synthesis Workshop},
  year = {1998}
}
21. Scan Path Design for Low-Power Serial Built-In Self Test
Zelleröhr, M., Hertwig, A. and Wunderlich, H.-J.
10th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'98), Herrenberg, Germany March 1998
1998
 
BibTeX:
@inproceedings{ZelleHW1998a,
  author = {Zelleröhr, M. and Hertwig, Andre and Wunderlich, Hans-Joachim},
  title = {{Scan Path Design for Low-Power Serial Built-In Self Test}},
  booktitle = {10th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'98)},
  year = {1998},
  volume = {1},
  number = {3}
}
20. Synthesis of Fast On-line Testable Controllers for Data-Dominated Applications
Hertwig, A., Hellebrand, S. and Wunderlich, H.-J.
3rd IEEE International On-Line Testing Workshop, Crete, Greece July 1997
1997
 
Keywords: synthesis of on-line testable FSMs; performance driven synthesis; FSM synthesis
Abstract: A target structure for implementing fast on-line testable control units for data-dominated applications is presented. In many cases, the proposed controller structure leads to a performance improvement of more than 30% for a standard benchmark set whereas the area overhead is less than 15% compared with conventional on-line testable finite state machines (FSM). The proposed approach is compatible with the state-of-the-art methods for FSM decomposition, state encoding and logic synthesis.
BibTeX:
@inproceedings{HertwHW1997,
  author = {Hertwig, Andre and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
  title = {{Synthesis of Fast On-line Testable Controllers for Data-Dominated Applications}},
  booktitle = {3rd IEEE International On-Line Testing Workshop},
  year = {1997},
  keywords = {synthesis of on-line testable FSMs; performance driven synthesis; FSM synthesis},
  abstract = {A target structure for implementing fast on-line testable control units for data-dominated applications is presented. In many cases, the proposed controller structure leads to a performance improvement of more than 30% for a standard benchmark set whereas the area overhead is less than 15% compared with conventional on-line testable finite state machines (FSM). The proposed approach is compatible with the state-of-the-art methods for FSM decomposition, state encoding and logic synthesis.}
}
19. Using BIST Control for Pattern Generation
Kiefer, G. and Wunderlich, H.-J.
IEEE European Test Workshop, Cagliari, Italy May 1997
1997
 
Keywords: deterministic BIST; scan-based BIST
Abstract: A deterministic BIST scheme is presented which requires less hardware overhead than pseudo-random BIST but obtains better or even complete fault coverage at the same time. It takes advantage of the fact that any autonomous BIST scheme needs a BIST control unit for indicating the completion of the self-test at least.
Hence, pattern counters and bit counters are always available, and they provide information to be bused for deterministic pattern generation by some additional circuitry. This paper presents a systematic way for synthesizing a pattern generator which needs less area than a 32-bit LFSR for random pattern generation for all the benchmark circuits.
BibTeX:
@inproceedings{KiefeW1997a,
  author = {Kiefer, Gundolf and Wunderlich, Hans-Joachim},
  title = {{Using BIST Control for Pattern Generation}},
  booktitle = {IEEE European Test Workshop},
  year = {1997},
  volume = {5},
  number = {2},
  keywords = {deterministic BIST; scan-based BIST},
  abstract = {A deterministic BIST scheme is presented which requires less hardware overhead than pseudo-random BIST but obtains better or even complete fault coverage at the same time. It takes advantage of the fact that any autonomous BIST scheme needs a BIST control unit for indicating the completion of the self-test at least.
Hence, pattern counters and bit counters are always available, and they provide information to be bused for deterministic pattern generation by some additional circuitry. This paper presents a systematic way for synthesizing a pattern generator which needs less area than a 32-bit LFSR for random pattern generation for all the benchmark circuits.} }
18. STARBIST: Scan Autocorrelated Random Pattern Generation
Tsai, K.-H., Hellebrand, S., Rajski, J. and Marek-Sadowska, M.
4th IEEE International Test Synthesis Workshop, Santa Barbara, California, USA May 1997
1997
 
Abstract: This paper presents a new scan-based BIST scheme which achieves very high fault coverage without the deficiencies of previously proposed schemes. This approach utilizes scan order
and polarity in scan synthesis, effectively converting the scan chain into a ROM capable of storing some “center” patterns from which the other vectors are derived by randomly complementing
some of their coordinates. Experimental results demonstrate that a very high fault coverage can be obtained without any modification of the mission logic, no test data to store and very simple BIST hardware which does not depend on the size of the circuit.
BibTeX:
@inproceedings{TsaiHRM1997,
  author = {Tsai, Kun-Han and Hellebrand, Sybille and Rajski, Janusz and Marek-Sadowska, Malgorzata},
  title = {{STARBIST: Scan Autocorrelated Random Pattern Generation}},
  booktitle = {4th IEEE International Test Synthesis Workshop},
  year = {1997},
  abstract = {This paper presents a new scan-based BIST scheme which achieves very high fault coverage without the deficiencies of previously proposed schemes. This approach utilizes scan order
and polarity in scan synthesis, effectively converting the scan chain into a ROM capable of storing some “center” patterns from which the other vectors are derived by randomly complementing
some of their coordinates. Experimental results demonstrate that a very high fault coverage can be obtained without any modification of the mission logic, no test data to store and very simple BIST hardware which does not depend on the size of the circuit.} }
17. Prüfpfadbasierter Selbsttest mit vollständiger Fehlererfassung und niedrigem Hardware-Aufwand
Kiefer, G. and Wunderlich, H.-J.
9th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'97), Bremen, Germany March 1997, pp. 49-52
1997
 
BibTeX:
@inproceedings{KiefeW1997,
  author = {Kiefer, Gundolf and Wunderlich, Hans-Joachim},
  title = {{Prüfpfadbasierter Selbsttest mit vollständiger Fehlererfassung und niedrigem Hardware-Aufwand}},
  booktitle = {9th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'97)},
  year = {1997},
  pages = {49--52}
}
16. Mixed-Mode BIST Using Embedded Processors
Hellebrand, S., Wunderlich, H.-J. and Hertwig, A.
2nd IEEE International On-Line Testing Workshop, Biarritz, France July 1996
1996
 
BibTeX:
@inproceedings{HelleWH1996,
  author = {Hellebrand, Sybille and Wunderlich, Hans-Joachim and Hertwig, Andre},
  title = {{Mixed-Mode BIST Using Embedded Processors}},
  booktitle = {2nd IEEE International On-Line Testing Workshop},
  year = {1996}
}
15. Scan-based BIST with Complete Fault Coverage and Low Hardware Overhead
Wunderlich, H.-J. and Kiefer, G.
IEEE European Test Workshop, Montpellier, France June 1996, pp. 60-64
1996
 
BibTeX:
@inproceedings{WundeK1996,
  author = {Wunderlich, Hans-Joachim and Kiefer, Gundolf},
  title = {{Scan-based BIST with Complete Fault Coverage and Low Hardware Overhead}},
  booktitle = {IEEE European Test Workshop},
  year = {1996},
  pages = {60--64}
}
14. Using Embedded Processors for BIST
Hellebrand, S. and Wunderlich, H.-J.
3rd IEEE International Test Synthesis Workshop, Santa Barbara, California, USA May 1996
1996
 
BibTeX:
@inproceedings{HelleW1996,
  author = {Hellebrand, Sybille and Wunderlich, Hans-Joachim},
  title = {{Using Embedded Processors for BIST}},
  booktitle = {3rd IEEE International Test Synthesis Workshop},
  year = {1996}
}
13. Pattern Generation for a Deterministic BIST Scheme
Hellebrand, S., Reeb, B., Tarnick, S. and Wunderlich, H.-J.
2nd IEEE International Test Synthesis Workshop, Santa Barbara, California, USA May 1995
1995
 
Abstract: Recently a deterministic built-in self-test scheme has been presented based on reseeding of multiple-polynomial linear feedback shift registers. This scheme encodes deterministic
test sets at distinctly lower costs than previously known approaches. In this paper it is shown how this scheme can be supported during test pattern generation. The presented ATPG algorithm generates test sets which can be encoded very efficiently. Experiments show that the area required for synthesizing a BIST scheme that encodes these patterns is significantly less than the area needed for storing a compact test set. Furthermore, it is demonstrated that the proposed approach of combining ATPG and BIST synthesis leads to a considerably reduced
hardware overhead compared to encoding a conventionally generated test set.
BibTeX:
@inproceedings{HelleRTW1995a,
  author = {Hellebrand, Sybille and Reeb, Birgit and Tarnick, Steffen and Wunderlich, Hans-Joachim},
  title = {{Pattern Generation for a Deterministic BIST Scheme}},
  booktitle = {2nd IEEE International Test Synthesis Workshop},
  year = {1995},
  abstract = {Recently a deterministic built-in self-test scheme has been presented based on reseeding of multiple-polynomial linear feedback shift registers. This scheme encodes deterministic
test sets at distinctly lower costs than previously known approaches. In this paper it is shown how this scheme can be supported during test pattern generation. The presented ATPG algorithm generates test sets which can be encoded very efficiently. Experiments show that the area required for synthesizing a BIST scheme that encodes these patterns is significantly less than the area needed for storing a compact test set. Furthermore, it is demonstrated that the proposed approach of combining ATPG and BIST synthesis leads to a considerably reduced
hardware overhead compared to encoding a conventionally generated test set.} }
12. Erfassung realistischer Fehler durch kombinierten IDDQ- und Logiktest
Stern, O. and Wunderlich, H.-J.
7th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'95), Hannover, Germany March 1995
1995
 
BibTeX:
@inproceedings{SternW1995,
  author = {Stern, Olaf and and Wunderlich, Hans-Joachim},
  title = {{Erfassung realistischer Fehler durch kombinierten IDDQ- und Logiktest}},
  booktitle = {7th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'95)},
  year = {1995},
  volume = {2},
  number = {3}
}
11. Synthese schneller selbsttestbarer Steuerwerke
Hellebrand, S. and Wunderlich, H.-J.
Tagungsband der GI/GME/ITG-Fachtagung "Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme", Oberwiesenthal, Germany, 16-17 May 1994, pp. 3-11
1994
 
Abstract: Es wird ein Verfahren vorgestellt, Steuerwerke als Pipelinestruktur zu synthetisieren. Dadurch kann ein Selbsttest ohne Integration zusätzlicher Testregister implementiert
werden, so daß die durch den Selbsttest verursachten Laufzeitverzögerungen reduziert, die Fehlererfassung verbessert und in vielen Fällen die Gesamtfläche der testbaren Schaltungen
verringert werden können. Eine selbsttestbare Struktur für einen vorgegebenen endlichen Automaten kann aus einer geeigneten Realisierung der Maschine erzeugt werden, es wird gezeigt,
daß solche Realisierungen stets konstruierbar sind. Ein Algorithmus zur Bestimmung optimaler Realisierungen wird vorgestellt, und die Ergebnisse werden an Hand von Benchmarkschaltungen validiert.
BibTeX:
@inproceedings{HelleW1994b,
  author = {Hellebrand, Sybille and and Wunderlich, Hans-Joachim},
  title = {{Synthese schneller selbsttestbarer Steuerwerke}},
  booktitle = {Tagungsband der GI/GME/ITG-Fachtagung "Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme"},
  publisher = {Springer-Verlag},
  year = {1994},
  pages = {3--11},
  abstract = {Es wird ein Verfahren vorgestellt, Steuerwerke als Pipelinestruktur zu synthetisieren. Dadurch kann ein Selbsttest ohne Integration zusätzlicher Testregister implementiert
werden, so daß die durch den Selbsttest verursachten Laufzeitverzögerungen reduziert, die Fehlererfassung verbessert und in vielen Fällen die Gesamtfläche der testbaren Schaltungen
verringert werden können. Eine selbsttestbare Struktur für einen vorgegebenen endlichen Automaten kann aus einer geeigneten Realisierung der Maschine erzeugt werden, es wird gezeigt,
daß solche Realisierungen stets konstruierbar sind. Ein Algorithmus zur Bestimmung optimaler Realisierungen wird vorgestellt, und die Ergebnisse werden an Hand von Benchmarkschaltungen validiert.} }
10. Testsynthese für Datenpfade
Ströle, A.P. and Wunderlich, H.-J.
Tagungsband der GI/GME/ITG-Fachtagung "Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme", Oberwiesenthal, Germany, 16-17 May 1994, pp. 162-171
1994
 
BibTeX:
@inproceedings{StroelW1994,
  author = {Ströle, Albrecht P. and and Wunderlich, Hans-Joachim},
  title = {{Testsynthese für Datenpfade}},
  booktitle = {Tagungsband der GI/GME/ITG-Fachtagung "Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme"},
  publisher = {Springer-Verlag},
  year = {1994},
  pages = {162--171}
}
9. Synthesis for Testability - the ARCHIMEDES Approach
Hellebrand, S., Teixeira, J.P. and Wunderlich, H.-J.
1st IEEE International Test Synthesis Workshop, Santa Barbara, California, USA May 1994
1994
 
BibTeX:
@inproceedings{HelleTW1994,
  author = {Hellebrand, Sybille and Teixeira, J. P. and and Wunderlich, Hans-Joachim},
  title = {{Synthesis for Testability - the ARCHIMEDES Approach}},
  booktitle = {1st IEEE International Test Synthesis Workshop},
  year = {1994}
}
8. Analyse und Simulation realistischer Fehler
Stern, O., Wu and Wunderlich, H.-J.
6th ITG/GI/GME Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'94), Vaals, Netherlands March 1994
1994
 
BibTeX:
@inproceedings{SternWW1994,
  author = {Stern, Olaf and Wu and Wunderlich, Hans-Joachim},
  title = {{Analyse und Simulation realistischer Fehler}},
  booktitle = {6th ITG/GI/GME Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'94)},
  year = {1994}
}
7. Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen
Venkataraman, S., Rajski, J., Hellebrand, S. and Tarnick, S.
6th ITG/GI/GME Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'94), Vaals, Netherlands March 1994
1994
 
BibTeX:
@inproceedings{VenkaRHT1994,
  author = {Venkataraman, Srikanth and and Rajski, Janusz and and Hellebrand, Sybille and and Tarnick, Steffen},
  title = {{Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen}},
  booktitle = {6th ITG/GI/GME Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'94)},
  year = {1994}
}
6. Ein Verfahren zur testfreundlichen Steuerwerkssynthese
Hellebrand, S. and Wunderlich, H.-J.
6th ITG/GI/GME Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'94), Vaals, Netherlands March 1994
1994
 
BibTeX:
@inproceedings{HelleW1994,
  author = {Hellebrand, Sybille and and Wunderlich, Hans-Joachim},
  title = {{Ein Verfahren zur testfreundlichen Steuerwerkssynthese}},
  booktitle = {6th ITG/GI/GME Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'94)},
  year = {1994}
}
5. Synthesis of Self-Testable Controllers
Hellebrand, S. and Wunderlich, H.-J.
ARCHIMEDES Open Workshop on "Synthesis - Architectural Testability Support", Montpellier, France July 1993
1993
 
Abstract: The paper presents a synthesis approach for pipelinelike controller structures. These structures allow to implement a built-in self-test in two sessions without any extra test registers. Hence the additional delay imposed by the test circuitry is reduced, the fault coverage is increased, and in many cases the overall area is minimal, too. The self-testable structure for a given finite state machine specification is derived from an appropriate realization of the machine. A theorem is proven that such realizations can be constructed by means of partition pairs. An algorithm
to determine optimal realizations is developed and benchmark experiments are presented to demonstrate the applicability of the presented approach .
Review: The paper presents a synthesis approach for pipelinelike controller structures. These structures allow to implement a built-in self-test in two sessions without any extra test registers. Hence the additional delay imposed by the test circuitry is reduced, the fault coverage is increased, and in many cases the overall area is minimal, too. The self-testable structure for a given finite state machine specification is derived from an appropriate realization of the machine. A theorem is proven that such realizations can be constructed by means of partition pairs. An algorithm
to determine optimal realizations is developed and benchmark experiments are presented to demonstrate the applicability of the presented approach .
BibTeX:
@inproceedings{HelleW1993,
  author = {Hellebrand, Sybille and Wunderlich, Hans-Joachim},
  title = {{Synthesis of Self-Testable Controllers}},
  booktitle = {ARCHIMEDES Open Workshop on "Synthesis - Architectural Testability Support"},
  year = {1993},
  abstract = {The paper presents a synthesis approach for pipelinelike controller structures. These structures allow to implement a built-in self-test in two sessions without any extra test registers. Hence the additional delay imposed by the test circuitry is reduced, the fault coverage is increased, and in many cases the overall area is minimal, too. The self-testable structure for a given finite state machine specification is derived from an appropriate realization of the machine. A theorem is proven that such realizations can be constructed by means of partition pairs. An algorithm
to determine optimal realizations is developed and benchmark experiments are presented to demonstrate the applicability of the presented approach .} }
4. Effiziente Erzeugung deterministischer Muster im Selbsttest
Hellebrand, S., Tarnick, S., Rajski, J. and Courtois, B.
5th ITG/GI/GME Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'93), Holzhau, Germany March 1993
1993
 
BibTeX:
@inproceedings{HelleTRC1993,
  author = {Hellebrand, Sybille and Tarnick, Steffen and Rajski, Janusz and Courtois, Bernard},
  title = {{Effiziente Erzeugung deterministischer Muster im Selbsttest}},
  booktitle = {5th ITG/GI/GME Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'93)},
  year = {1993}
}
3. Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs
Hellebrand, S., Tarnick, S., Rajski, J. and Courtois, B.
Workshop on New Directions for Testing, Montreal, Canada May 1992
1992
 
BibTeX:
@inproceedings{HelleTRC1992a,
  author = {Hellebrand, Sybille and Tarnick, Steffen and Rajski, Janusz and Courtois, Bernard},
  title = {{Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs}},
  booktitle = {Workshop on New Directions for Testing},
  year = {1992}
}
2. Generation of Test Patterns through Reseeding of Multiple-Polynomial LFSRs
Hellebrand, S., Tarnick, S., Rajski, J. and Courtois, B.
IEEE Design for Testability Workshop, Vail, Colorado, USA April 1992
1992
 
BibTeX:
@inproceedings{HelleTRC1992,
  author = {Hellebrand, Sybille and Tarnick, Steffen and Rajski, Janusz and Courtois, Bernard},
  title = {{Generation of Test Patterns through Reseeding of Multiple-Polynomial LFSRs}},
  booktitle = {IEEE Design for Testability Workshop},
  year = {1992}
}
1. Generating Pseudo-Exhaustive Vectors for External Testing
Hellebrand, S., Wunderlich, H.-J. and Haberl, O.F.
IEEE Design for Testability Workshop, Vail, Colorado, USA April 1990
1990
 
Abstract: In the past years special chips for external test have been successfully used for random pattern testing. In this paper a technique is presented to combine the advantages of such a low cost
test with the advantages of pseudo-exhaustive testing, which are an enhanced fault coverage and a simplified test pattern generation.

To achieve this goal two tasks are solved. Firstly, an algorithm is developed for pseudo-exhaustive test pattern generation, which ensures a feasible test length. Secondly, a chip design for
applying these test patterns to a device under test is presented. The chip is programmed by the output of the presented algorithm and controls the entire test. The technique is first applied to
devices with a scan path and then extended to sequential circuits. A large number of benchmark circuits have been investigated, and the results are presented.

BibTeX:
@inproceedings{HelleWH1990a,
  author = {Hellebrand, Sybille and Wunderlich, Hans-Joachim and Haberl, Oliver F.},
  title = {{Generating Pseudo-Exhaustive Vectors for External Testing}},
  booktitle = {IEEE Design for Testability Workshop},
  year = {1990},
  abstract = {In the past years special chips for external test have been successfully used for random pattern testing. In this paper a technique is presented to combine the advantages of such a low cost
test with the advantages of pseudo-exhaustive testing, which are an enhanced fault coverage and a simplified test pattern generation.

To achieve this goal two tasks are solved. Firstly, an algorithm is developed for pseudo-exhaustive test pattern generation, which ensures a feasible test length. Secondly, a chip design for
applying these test patterns to a device under test is presented. The chip is programmed by the output of the presented algorithm and controls the entire test. The technique is first applied to
devices with a scan path and then extended to sequential circuits. A large number of benchmark circuits have been investigated, and the results are presented.} }

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