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VIVA: Leistungs- und Energiebeschränkung im Selbsttest

03.2003 - 10.2005, DFG-Project: WU 245/2-2    


What is VIVA?

With the popularity of embedded applications and portable devices, power consumption of systems receives higher attention throughout all design levels. The programme of "Grundlagen und Verfahren verlustarmer Informationsverarbeitung (VIVA), sponsored by Deutsche Forschungsgemeinschaft (DFG), studies fundamentals and methods for low-power information processing.

More information regarding all projects of the VIVA programme is provided here.


Project: Self-test under Power and Energy Constraints

Software-based self-test (SBST) is viewed as a promising alternative as traditional hardware-based test methods for microprocessors due to its benefits of at-speed test, dispense with expensive test equipments and low design-for-testability (DfT) overhead. Its principle is illustrated in the following figure which involves generation, storage and execution of test programs.

Fig.: Principle of the SBST


Test quality is maximized under the consideration of the structure of the core under test (CUT) during test program synthesis. The SBST operates under the functional mode so that it meets the peak power specification of the system; nevertheless, it is of great significance for reliability reasons to optimize programs causing above-average switching activities. It is particularly true when such a test is deployed autonomously where both average power and energy consumption play a crucial role. This project proposed a novel method that tackles fault coverage, test length, energy and average power consumption at the same time.


Publications

    1. Conference and Workshop Contributions:
  • Software-Based Self-Test of Processors under Power Constraints (pdf)
    J. Zhou, H.-J. Wunderlich
    Proc. of the 9th Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, pp. 430 - 436, March 06 - 10, 2006
  • Software-basierender Selbsttest von Prozessoren bei beschränkter Verlustleistung (pdf)
    J. Zhou, H.-J. Wunderlich
    ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Titisee, Germany, pp. 95 - 100, March 12-14, 2006
  • Software-basierender Selbsttest von Prozessorkernen unter Verlustleistungsbeschränkung (pdf)
    J. Zhou, H.-J. Wunderlich
    Jahrestagung der Gesellschaft für Informatik, DFG-Workshop Grundlagen und Verfahren verlustarmer Informationsverarbeitung (VIVA), Bonn, Germany, Vol. 1, p. 441, September 19, 2005
  • Power Conscious BIST Approaches
    A. Virazel, H.-J. Wunderlich
    3. VIVA Schwerpunkt-Kolloquium, Chemnitz, Germany, ISBN 3-00-008 995-0, p. 128 - 135, 18. -19. March 2002
    2. Thesis:
  • Prüfgerechter Entwurf und Testerzeugung für den Leon2-Prozessor
    X. Yang, ITI, Universität Stuttgart, Winter semester 2005/2006
  • Untersuchung der Schaltaktivität von RISC-Prozessoren am Beispiel des Leon Prozessors
    M. Schuller, ITI, Universität Stuttgart, Summer semester 2002

 


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