Project Partner

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Online Failure Prediction for Microelectronic Circuits Using Aging Signatures (OASIS)

03.2011 - 12.2014, DFG-Project: WU 245/11-1    

Microelectronic circuits suffer from life-time limiting aging. In this project, online in-field methods to assess circuit performance and remaining life-time will be developed to predict failures due to aging processes.

Sensors and monitoring infrastructure are used to analyze both operating conditions as well as aging indicators so that a system failure can be early indicated and prevented by technical measures. Novel maintenance concepts based on failure prediction allow for a substantial simplification of established structural fault tolerance measures (e.g. redundancy concepts) even in safety-critical applications since specific counter measures can be applied before an actual aging induced failure.

With the aid of such an on-line monitoring the effective life-time of a microelectronic product can be significantly increased at low cost.

Project Partner

  • Institut für Mikroelektronik Stuttgart
    IMS

Publications

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14. Test Pattern Generation in Presence of Unknown Values Based on Restricted Symbolic Logic
Erb, D., Scheibler, K., Kochte, M.A., Sauer, M., Wunderlich, H.-J. and Becker, B.
Proceedings of the IEEE International Test Conference (ITC'14), Seattle, Washington, USA, 20-23 October 2014, pp. 1-10
2014
DOI PDF 
Keywords: SAT, QBF, test generation, ATPG, Unknown values, Restricted symbolic logic
Abstract: Test generation algorithms based on standard n-valued logic algebras are pessimistic in presence of unknown (X) values, overestimate the number of signals with X-values and underestimate fault coverage. Recently, an ATPG algorithm based on quantified Boolean formula (QBF) has been presented, which is accurate in presence of X-values but has limits with respect to runtime, scalability and robustness. In this paper, we consider ATPG based on restricted symbolic logic (RSL) and demonstrate its potential. We introduce a complete RSL ATPG exploiting the full potential of RSL in ATPG. Experimental results demonstrate that RSL ATPG significantly increases fault coverage over classical algorithms and provides results very close to the accurate QBF-based algorithm. An optimized version of RSL ATPG (together with accurate fault simulation) is up to 618× faster than the QBF-based solution, more scalable and more robust.
BibTeX:
@inproceedings{ErbSKSWB2014,
  author = {Erb, Dominik and Scheibler, Karsten and Kochte, Michael A. and Sauer, Matthias and Wunderlich, Hans-Joachim and Becker, Bernd},
  title = {{Test Pattern Generation in Presence of Unknown Values Based on Restricted Symbolic Logic}},
  booktitle = {Proceedings of the IEEE International Test Conference (ITC'14)},
  year = {2014},
  pages = {1--10},
  keywords = {SAT, QBF, test generation, ATPG, Unknown values, Restricted symbolic logic},
  abstract = {Test generation algorithms based on standard n-valued logic algebras are pessimistic in presence of unknown (X) values, overestimate the number of signals with X-values and underestimate fault coverage. Recently, an ATPG algorithm based on quantified Boolean formula (QBF) has been presented, which is accurate in presence of X-values but has limits with respect to runtime, scalability and robustness. In this paper, we consider ATPG based on restricted symbolic logic (RSL) and demonstrate its potential. We introduce a complete RSL ATPG exploiting the full potential of RSL in ATPG. Experimental results demonstrate that RSL ATPG significantly increases fault coverage over classical algorithms and provides results very close to the accurate QBF-based algorithm. An optimized version of RSL ATPG (together with accurate fault simulation) is up to 618× faster than the QBF-based solution, more scalable and more robust.},
  doi = {http://dx.doi.org/10.1109/TEST.2014.7035350},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ITC_ErbSKSWB2014.pdf}
}
13. FAST-BIST: Faster-than-At-Speed BIST Targeting Hidden Delay Defects
Hellebrand, S., Indlekofer, T., Kampmann, M., Kochte, M.A., Liu, C. and Wunderlich, H.-J.
Proceedings of the IEEE International Test Conference (ITC'14), Seattle, Washington, USA, 20-23 October 2014, pp. 1-8
2014
DOI PDF 
Abstract: Small delay faults may be an indicator of a reliability threat, even if they do not affect the system functionality yet. In recent years, Faster-than-at-Speed-Test (FAST) has become a feasible method to detect faults, which are hidden by the timing slack or by long critical paths in the combinational logic. FAST poses severe challenges to the automatic test equipment with respect to timing, performance, and resolution. In this paper, it is shown how logic built-in self-test (BIST) or embedded deterministic test can be used for an efficient FAST application. Running BIST just at a higher frequency is not an option, as outputs of long paths will receive undefined values due to set time violations and destroy the content of the signature registers. Instead, for a given test pattern sequence, faults are classified according to the optimal detection frequency. For each class, a MISR-based compaction scheme is adapted, such that the critical bits to be observed can be determined by algebraic computations. Experiments show that rather a small number of inter-mediate signatures have to be evaluated to observe a large fraction of hidden delay faults testable by the given test sequence.
BibTeX:
@inproceedings{HelleIKKLW2014,
  author = {Hellebrand, Sybille and Indlekofer, Thomas and Kampmann, Matthias and Kochte, Michael A. and Liu, Chang and Wunderlich, Hans-Joachim},
  title = {{FAST-BIST: Faster-than-At-Speed BIST Targeting Hidden Delay Defects}},
  booktitle = {Proceedings of the IEEE International Test Conference (ITC'14)},
  year = {2014},
  pages = {1--8},
  abstract = {Small delay faults may be an indicator of a reliability threat, even if they do not affect the system functionality yet. In recent years, Faster-than-at-Speed-Test (FAST) has become a feasible method to detect faults, which are hidden by the timing slack or by long critical paths in the combinational logic. FAST poses severe challenges to the automatic test equipment with respect to timing, performance, and resolution. In this paper, it is shown how logic built-in self-test (BIST) or embedded deterministic test can be used for an efficient FAST application. Running BIST just at a higher frequency is not an option, as outputs of long paths will receive undefined values due to set time violations and destroy the content of the signature registers. Instead, for a given test pattern sequence, faults are classified according to the optimal detection frequency. For each class, a MISR-based compaction scheme is adapted, such that the critical bits to be observed can be determined by algebraic computations. Experiments show that rather a small number of inter-mediate signatures have to be evaluated to observe a large fraction of hidden delay faults testable by the given test sequence.},
  doi = {http://dx.doi.org/10.1109/TEST.2014.7035360},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ITC_HelleIKKLW2014.pdf}
}
12. Multi-Level Simulation of Non-Functional Properties by Piecewise Evaluation
Hatami, N., Baranowski, R., Prinetto, P. and Wunderlich, H.-J.
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Vol. 19(4), August 2014, pp. 37:1-37:21
2014
DOI PDF 
Keywords: Design, Verification, Reliability
Abstract: As the technology shrinks, nonfunctional properties (NFPs) such as reliability, vulnerability, power consumption, or heat dissipation become as important as system functionality. As NFPs often influence each other, depend on the application and workload of a system, and exhibit nonlinear behavior, NFP simulation over long periods of system operation is computationally expensive, if feasible at all. This article presents a piecewise evaluation method for efficient NFP simulation. Simulation time is divided into intervals called evaluation windows, within which the NFP models are partially linearized. High-speed functional system simulation is achieved by parallel execution of models at different levels of abstraction. A trade-off between simulation speed and accuracy is met by adjusting the size of the evaluation window. As an example, the piecewise evaluation technique is applied to analyze aging caused by two mechanisms, namely Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), in order to identify reliability hotspots. Experiments show that the proposed technique yields considerable simulation speedup at a marginal loss of accuracy.
BibTeX:
@article{HatamBPW2014,
  author = {Hatami, Nadereh and Baranowski, Rafal and Prinetto, Paolo and Wunderlich, Hans-Joachim},
  title = {{Multi-Level Simulation of Non-Functional Properties by Piecewise Evaluation}},
  journal = {ACM Transactions on Design Automation of Electronic Systems (TODAES)},
  year = {2014},
  volume = {19},
  number = {4},
  pages = {37:1--37:21},
  keywords = {Design, Verification, Reliability},
  abstract = {As the technology shrinks, nonfunctional properties (NFPs) such as reliability, vulnerability, power consumption, or heat dissipation become as important as system functionality. As NFPs often influence each other, depend on the application and workload of a system, and exhibit nonlinear behavior, NFP simulation over long periods of system operation is computationally expensive, if feasible at all. This article presents a piecewise evaluation method for efficient NFP simulation. Simulation time is divided into intervals called evaluation windows, within which the NFP models are partially linearized. High-speed functional system simulation is achieved by parallel execution of models at different levels of abstraction. A trade-off between simulation speed and accuracy is met by adjusting the size of the evaluation window. As an example, the piecewise evaluation technique is applied to analyze aging caused by two mechanisms, namely Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), in order to identify reliability hotspots. Experiments show that the proposed technique yields considerable simulation speedup at a marginal loss of accuracy.},
  doi = {http://dx.doi.org/10.1145/2647955},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/TODAES_HatamBPW2014.pdf}
}
11. Exact Logic and Fault Simulation in Presence of Unknowns
Erb, D., Kochte, M.A., Sauer, M., Hillebrecht, S., Schubert, T., Wunderlich, H.-J. and Becker, B.
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Vol. 19(3), June 2014, pp. 28:1-28:17
2014
DOI PDF 
Keywords: Algorithms, Reliability, Unknown values, simulation pessimism, exact logic simulation, exact fault simulation, SAT
Abstract: Logic and fault simulation are essential techniques in electronic design automation. The accuracy of standard simulation algorithms is compromised by unknown or X-values. This results in a pessimistic overestimation of X-valued signals in the circuit and a pessimistic underestimation of fault coverage.
This work proposes efficient algorithms for combinational and sequential logic as well as for stuck-at and transition-delay fault simulation that are free of any simulation pessimism in presence of unknowns. The SAT-based algorithms exactly classifiy all signal states. During fault simulation, each fault is accurately classified as either undetected, definitely detected, or possibly detected.
The pessimism with respect to unknowns present in classic algorithms is thoroughly investigated in the experimental results on benchmark circuits. The applicability of the proposed algorithms is demonstrated on larger industrial circuits. The results show that, by accurate analysis, the number of detected faults can be significantly increased without increasing the test-set size.
BibTeX:
@article{ErbKSHSWB2014,
  author = {Erb, Dominik and Kochte, Michael A. and Sauer, Matthias and Hillebrecht, Stefan and Schubert, Tobias and Wunderlich, Hans-Joachim and Becker, Bernd},
  title = {{Exact Logic and Fault Simulation in Presence of Unknowns}},
  journal = {ACM Transactions on Design Automation of Electronic Systems (TODAES)},
  year = {2014},
  volume = {19},
  number = {3},
  pages = {28:1--28:17},
  keywords = {Algorithms, Reliability, Unknown values, simulation pessimism, exact logic simulation, exact fault simulation, SAT},
  abstract = {Logic and fault simulation are essential techniques in electronic design automation. The accuracy of standard simulation algorithms is compromised by unknown or X-values. This results in a pessimistic overestimation of X-valued signals in the circuit and a pessimistic underestimation of fault coverage.
This work proposes efficient algorithms for combinational and sequential logic as well as for stuck-at and transition-delay fault simulation that are free of any simulation pessimism in presence of unknowns. The SAT-based algorithms exactly classifiy all signal states. During fault simulation, each fault is accurately classified as either undetected, definitely detected, or possibly detected.
The pessimism with respect to unknowns present in classic algorithms is thoroughly investigated in the experimental results on benchmark circuits. The applicability of the proposed algorithms is demonstrated on larger industrial circuits. The results show that, by accurate analysis, the number of detected faults can be significantly increased without increasing the test-set size.}, doi = {http://dx.doi.org/10.1145/2611760}, file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/TODAES_ErbKSHSWB2014.pdf} }
10. Variation-Aware Deterministic ATPG
Sauer, M., Polian, I., Imhof, M.E., Mumtaz, A., Schneider, E., Czutro, A., Wunderlich, H.-J. and Becker, B.
Proceedings of the 19th IEEE European Test Symposium (ETS'14), Paderborn, Germany, 26-30 May 2014, pp. 87-92
Best paper award
2014
DOI URL PDF 
Keywords: Variation-aware test, fault efficiency, ATPG
Abstract: In technologies affected by variability, the detection status of a small-delay fault may vary among manufactured circuit instances. The same fault may be detected, missed or provably undetectable in different circuit instances. We introduce the first complete flow to accurately evaluate and systematically maximize the test quality under variability. As the number of possible circuit instances is infinite, we employ statistical analysis to obtain a test set that achieves a fault-efficiency target with an user-defined confidence level. The algorithm combines a classical path-oriented test-generation procedure with a novel waveformaccurate engine that can formally prove that a small-delay fault is not detectable and does not count towards fault efficiency. Extensive simulation results demonstrate the performance of the generated test sets for industrial circuits affected by uncorrelated and correlated variations.
BibTeX:
@inproceedings{SauerPIMSCWB2014,
  author = {Sauer, Matthias and Polian, Ilia and Imhof, Michael E. and Mumtaz, Abdullah and Schneider, Eric and Czutro, Alexander and Wunderlich, Hans-Joachim and Becker, Bernd},
  title = {{Variation-Aware Deterministic ATPG}},
  booktitle = {Proceedings of the 19th IEEE European Test Symposium (ETS'14)},
  year = {2014},
  pages = {87--92},
  keywords = {Variation-aware test, fault efficiency, ATPG},
  abstract = {In technologies affected by variability, the detection status of a small-delay fault may vary among manufactured circuit instances. The same fault may be detected, missed or provably undetectable in different circuit instances. We introduce the first complete flow to accurately evaluate and systematically maximize the test quality under variability. As the number of possible circuit instances is infinite, we employ statistical analysis to obtain a test set that achieves a fault-efficiency target with an user-defined confidence level. The algorithm combines a classical path-oriented test-generation procedure with a novel waveformaccurate engine that can formally prove that a small-delay fault is not detectable and does not count towards fault efficiency. Extensive simulation results demonstrate the performance of the generated test sets for industrial circuits affected by uncorrelated and correlated variations.},
  url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6847806},
  doi = {http://dx.doi.org/10.1109/ETS.2014.6847806},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ETS_SauerPIMSCWB2014.pdf}
}
9. Verifikation Rekonfigurierbarer Scan-Netze
Baranowski, R., Kochte, M.A. and Wunderlich, H.-J.
Proceedings of the 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'14), Böblingen, Germany, 10-12 March 2014, pp. 137-146
2014
URL PDF 
Keywords: Verification, debug and diagnosis, reconfigurable scan network, IJTAG, IEEE P1687, design for test
Abstract: Rekonfigurierbare Scan-Netze, z. B. entsprechend IEEE Std. P1687 oder 1149.1-2013, ermöglichen den effizienten Zugriff auf On-Chip-Infrastruktur für Bringup, Debug, Post-Silicon-Validierung und Diagnose. Diese Scan-Netze sind oft hierarchisch und können komplexe strukturelle und funktionale Abhängigkeiten aufweisen. Bekannte Verfahren zur Verifikation von Scan-Ketten, basierend auf Simulation und struktureller Analyse, sind nicht geeignet, Korrektheitseigenschaften von komplexen Scan-Netzen zu verifizieren. Diese Arbeit stellt ein formales Modell für rekonfigurierbare Scan-Netze vor, welches die strukturellen und funktionalen Abhängigkeiten abbildet und anwendbar ist für Architekturen nach IEEE P1687. Das Modell dient als Grundlage für effizientes Bounded Model Checking von Eigenschaften, wie z. B. der Erreichbarkeit von Scan-Registern.
BibTeX:
@inproceedings{BaranKW2014,
  author = {Baranowski, Rafal and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Verifikation Rekonfigurierbarer Scan-Netze}},
  booktitle = {Proceedings of the 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'14)},
  year = {2014},
  pages = {137--146},
  keywords = {Verification, debug and diagnosis, reconfigurable scan network, IJTAG, IEEE P1687, design for test},
  abstract = {Rekonfigurierbare Scan-Netze, z. B. entsprechend IEEE Std. P1687 oder 1149.1-2013, ermöglichen den effizienten Zugriff auf On-Chip-Infrastruktur für Bringup, Debug, Post-Silicon-Validierung und Diagnose. Diese Scan-Netze sind oft hierarchisch und können komplexe strukturelle und funktionale Abhängigkeiten aufweisen. Bekannte Verfahren zur Verifikation von Scan-Ketten, basierend auf Simulation und struktureller Analyse, sind nicht geeignet, Korrektheitseigenschaften von komplexen Scan-Netzen zu verifizieren. Diese Arbeit stellt ein formales Modell für rekonfigurierbare Scan-Netze vor, welches die strukturellen und funktionalen Abhängigkeiten abbildet und anwendbar ist für Architekturen nach IEEE P1687. Das Modell dient als Grundlage für effizientes Bounded Model Checking von Eigenschaften, wie z. B. der Erreichbarkeit von Scan-Registern.},
  url = {https://cuvillier.de/de/shop/publications/6629-mbmv-2014},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/MBMV_BaranKW2014.pdf}
}
8. Securing Access to Reconfigurable Scan Networks
Baranowski, R., Kochte, M.A. and Wunderlich, H.-J.
Proceedings of the 22nd IEEE Asian Test Symposium (ATS'13), Yilan, Taiwan, 18-21 November 2013
2013
DOI PDF 
Keywords: Debug and diagnosis, reconfigurable scan network, IJTAG, IEEE P1687, secure DFT, hardware security
Abstract: The accessibility of on-chip embedded infrastructure for test, reconfiguration, and debug poses a serious safety and security problem. Special care is required in the design and development of scan architectures based on IEEE Std. 1149.1 (JTAG), IEEE Std. 1500, and especially reconfigurable scan networks, as allowed by the upcoming IEEE P1687 (IJTAG). Traditionally, the scan infrastructure is secured after manufacturing test using fuses that disable the test access port (TAP) completely or partially. The fuse-based approach is efficient if some scan chains or instructions of the TAP controller are to be permanently blocked. However, this approach becomes costly if fine-grained access management is required, and it faces scalability issues in reconfigurable scan networks. In this paper, we propose a scalable solution for multi-level access management in reconfigurable scan networks. The access to protected registers is restricted locally at TAP-level by a sequence filter which allows only a precomputed set of scan-in access sequences. Our approach does not require any modification of the scan architecture and causes no access time penalty. Experimental results for complex reconfigurable scan networks show that the area overhead depends primarily on the number of allowed accesses, and is marginal even if this number exceeds the count of network’s registers.
BibTeX:
@inproceedings{BaranKW2013a,
  author = {Baranowski, Rafal and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Securing Access to Reconfigurable Scan Networks}},
  booktitle = {Proceedings of the 22nd IEEE Asian Test Symposium (ATS'13)},
  year = {2013},
  keywords = {Debug and diagnosis, reconfigurable scan network, IJTAG, IEEE P1687, secure DFT, hardware security},
  abstract = {The accessibility of on-chip embedded infrastructure for test, reconfiguration, and debug poses a serious safety and security problem. Special care is required in the design and development of scan architectures based on IEEE Std. 1149.1 (JTAG), IEEE Std. 1500, and especially reconfigurable scan networks, as allowed by the upcoming IEEE P1687 (IJTAG). Traditionally, the scan infrastructure is secured after manufacturing test using fuses that disable the test access port (TAP) completely or partially. The fuse-based approach is efficient if some scan chains or instructions of the TAP controller are to be permanently blocked. However, this approach becomes costly if fine-grained access management is required, and it faces scalability issues in reconfigurable scan networks. In this paper, we propose a scalable solution for multi-level access management in reconfigurable scan networks. The access to protected registers is restricted locally at TAP-level by a sequence filter which allows only a precomputed set of scan-in access sequences. Our approach does not require any modification of the scan architecture and causes no access time penalty. Experimental results for complex reconfigurable scan networks show that the area overhead depends primarily on the number of allowed accesses, and is marginal even if this number exceeds the count of network’s registers.},
  doi = {http://dx.doi.org/10.1109/ATS.2013.61},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2013/ATS_BaranKW2013.pdf}
}
7. Accurate Multi-Cycle ATPG in Presence of X-Values
Erb, D., Kochte, M.A., Sauer, M., Wunderlich, H.-J. and Becker, B.
Proceedings of the 22nd IEEE Asian Test Symposium (ATS'13), Yilan, Taiwan, 18-21 November 2013
2013
DOI PDF 
Keywords: Unknown values, test generation, ATPG, QBF, multi-cycle, partial scan
Abstract: Unknown (X) values in a circuit impair test quality and increase test costs. Classical n-valued algorithms for fault simulation and ATPG, which typically use a three- or four-valued logic for the good and faulty circuit, are in principle pessimistic in presence of X-values and cannot accurately compute the achievable fault coverage.
In partial scan or pipelined circuits, X-values originate in non-scan flip-flops. These circuits are tested using multi-cycle tests. Here we present multi-cycle test generation techniques for circuits with X-values due to partial scan or other X-sources. The proposed techniques have been integrated into a multi-cycle ATPG framework which employs formal Boolean and quantified Boolean (QBF) satisfiability techniques to compute the possible signal states in the circuit accurately. Efficient encoding of the problem instance ensures reasonable runtimes.
We show that in presence of X-values, the detection of stuck-at faults requires not only exact formal reasoning in a single cycle, but especially the consideration of multiple cycles for excitation of the fault site as well as propagation and controlled reconvergence of fault effects.
For the first time, accurate deterministic ATPG for multi-cycle test application is supported for stuck-at faults. Experiments on ISCAS'89 and industrial circuits with X-sources show that this new approach increases the fault coverage considerably.
BibTeX:
@inproceedings{ErbKSWB2013,
  author = {Erb, Dominik and Kochte, Michael A. and Sauer, Matthias and Wunderlich, Hans-Joachim and Becker, Bernd},
  title = {{Accurate Multi-Cycle ATPG in Presence of X-Values}},
  booktitle = {Proceedings of the 22nd IEEE Asian Test Symposium (ATS'13)},
  year = {2013},
  keywords = {Unknown values, test generation, ATPG, QBF, multi-cycle, partial scan},
  abstract = { Unknown (X) values in a circuit impair test quality and increase test costs. Classical n-valued algorithms for fault simulation and ATPG, which typically use a three- or four-valued logic for the good and faulty circuit, are in principle pessimistic in presence of X-values and cannot accurately compute the achievable fault coverage.
In partial scan or pipelined circuits, X-values originate in non-scan flip-flops. These circuits are tested using multi-cycle tests. Here we present multi-cycle test generation techniques for circuits with X-values due to partial scan or other X-sources. The proposed techniques have been integrated into a multi-cycle ATPG framework which employs formal Boolean and quantified Boolean (QBF) satisfiability techniques to compute the possible signal states in the circuit accurately. Efficient encoding of the problem instance ensures reasonable runtimes.
We show that in presence of X-values, the detection of stuck-at faults requires not only exact formal reasoning in a single cycle, but especially the consideration of multiple cycles for excitation of the fault site as well as propagation and controlled reconvergence of fault effects.
For the first time, accurate deterministic ATPG for multi-cycle test application is supported for stuck-at faults. Experiments on ISCAS'89 and industrial circuits with X-sources show that this new approach increases the fault coverage considerably. }, doi = {http://dx.doi.org/10.1109/ATS.2013.53}, file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2013/ATS_ErbKSWB2013.pdf} }
6. Synthesis of Workload Monitors for On-Line Stress Prediction
Baranowski, R., Cook, A., Imhof, M.E., Liu, C. and Wunderlich, H.-J.
Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'13), New York City, New York, USA, 2-4 October 2013, pp. 137-142
2013
DOI URL PDF 
Keywords: Reliability estimation, workload monitoring, aging prediction, NBTI
Abstract: Stringent reliability requirements call for monitoring mechanisms to account for circuit degradation throughout the complete system lifetime. In this work, we efficiently monitor the stress experienced by the system as a result of its current workload. To achieve this goal, we construct workload monitors that observe the most relevant subset of the circuit’s primary and pseudo-primary inputs and produce an accurate stress approximation. The proposed approach enables the timely adoption of
suitable countermeasures to reduce or prevent any deviation from the intended circuit behavior. The relation between monitoring accuracy and hardware cost can be adjusted according to design requirements. Experimental results show the efficiency of the proposed approach for the prediction of stress induced by Negative Bias Temperature Instability (NBTI) in critical and near-critical paths of a digital circuit.
BibTeX:
@inproceedings{BaranCILW2013,
  author = {Baranowski, Rafal and Cook, Alejandro and Imhof, Michael E. and Liu, Chang and Wunderlich, Hans-Joachim},
  title = {{Synthesis of Workload Monitors for On-Line Stress Prediction}},
  booktitle = {Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'13)},
  year = {2013},
  pages = {137--142},
  keywords = {Reliability estimation, workload monitoring, aging prediction, NBTI},
  abstract = {Stringent reliability requirements call for monitoring mechanisms to account for circuit degradation throughout the complete system lifetime. In this work, we efficiently monitor the stress experienced by the system as a result of its current workload. To achieve this goal, we construct workload monitors that observe the most relevant subset of the circuit’s primary and pseudo-primary inputs and produce an accurate stress approximation. The proposed approach enables the timely adoption of
suitable countermeasures to reduce or prevent any deviation from the intended circuit behavior. The relation between monitoring accuracy and hardware cost can be adjusted according to design requirements. Experimental results show the efficiency of the proposed approach for the prediction of stress induced by Negative Bias Temperature Instability (NBTI) in critical and near-critical paths of a digital circuit.}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6653596}, doi = {http://dx.doi.org/10.1109/DFT.2013.6653596}, file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2013/DFTS_BaranCILW2013.pdf} }
5. Scan Pattern Retargeting and Merging with Reduced Access Time
Baranowski, R., Kochte, M.A. and Wunderlich, H.-J.
Proceedings of the IEEE European Test Symposium (ETS'13), Avignon, France, 27-30 May 2013, pp. 39-45
2013
DOI PDF 
Keywords: Design for debug & diagnosis, optimal pattern retargeting, scan pattern generation, reconfigurable scan network, IJTAG, P1687
Abstract: Efficient access to on-chip instrumentation is a key enabler for post-silicon validation, debug, bringup or diagnosis. Re- configurable scan networks, as proposed by e.g. the IEEE Std. P1687, emerge as an effective and affordable means to cope with the increasing complexity of on-chip infrastructure. To access an element in a reconfigurable scan network, a scan- in bit sequence must be generated according to the current state and structure of the network. Due to sequential and combinational dependencies, the scan pattern generation process (pattern retargeting) poses a complex decision and optimization problem. This work presents a method for scan pattern generation with reduced access time. We map the access time reduction to a pseudo- Boolean optimization problem, which enables the use of efficient solvers to exhaustively explore the search space of valid scan-in sequences. This is the first automated method for efficient pattern retargeting in complex reconfigurable scan architectures such as P1687- based networks. It supports the concurrent access to multiple target scan registers (access merging) and generates reduced (short) scan-in sequences, considering all sequential and combinational dependencies. The proposed method achieves an access time reduction by up to 88x or 2.4x in average w.r.t. unoptimized satisfying solutions.
BibTeX:
@inproceedings{BaranKW2013,
  author = {Baranowski, Rafal and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Scan Pattern Retargeting and Merging with Reduced Access Time}},
  booktitle = {Proceedings of the IEEE European Test Symposium (ETS'13)},
  publisher = {IEEE Computer Society},
  year = {2013},
  pages = {39--45},
  keywords = {Design for debug & diagnosis, optimal pattern retargeting, scan pattern generation, reconfigurable scan network, IJTAG, P1687},
  abstract = {Efficient access to on-chip instrumentation is a key enabler for post-silicon validation, debug, bringup or diagnosis. Re- configurable scan networks, as proposed by e.g. the IEEE Std. P1687, emerge as an effective and affordable means to cope with the increasing complexity of on-chip infrastructure. To access an element in a reconfigurable scan network, a scan- in bit sequence must be generated according to the current state and structure of the network. Due to sequential and combinational dependencies, the scan pattern generation process (pattern retargeting) poses a complex decision and optimization problem. This work presents a method for scan pattern generation with reduced access time. We map the access time reduction to a pseudo- Boolean optimization problem, which enables the use of efficient solvers to exhaustively explore the search space of valid scan-in sequences. This is the first automated method for efficient pattern retargeting in complex reconfigurable scan architectures such as P1687- based networks. It supports the concurrent access to multiple target scan registers (access merging) and generates reduced (short) scan-in sequences, considering all sequential and combinational dependencies. The proposed method achieves an access time reduction by up to 88x or 2.4x in average w.r.t. unoptimized satisfying solutions.},
  doi = {http://dx.doi.org/10.1109/ETS.2013.6569354},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2013/ETS_BaranKW2013.pdf}
}
4. Accurate QBF-based Test Pattern Generation in Presence of Unknown Values
Hillebrecht, S., Kochte, M.A., Erb, D., Wunderlich, H.-J. and Becker, B.
Proceedings of the Conference on Design, Automation and Test in Europe (DATE'13), Grenoble, France, 18-22 March 2013, pp. 436-441
2013
DOI PDF 
Keywords: Unknown values, test generation, ATPG, QBF
Abstract: Unknown (X) values may emerge during the design process as well as during system operation and test application. Sources of X-values are for example black boxes, clockdomain boundaries, analog-to-digital converters, or uncontrolled or uninitialized sequential elements. To compute a detecting pattern for a given stuck-at fault, well defined logic values are required both for fault activation as well as for fault effect propagation to observing outputs. In presence of X-values, classical test generation algorithms, based on topological algorithms or formal Boolean satisfiability (SAT) or BDD-based reasoning, may fail to generate testing patterns or to prove faults untestable. This work proposes the first efficient stuck-at fault ATPG algorithm able to prove testability or untestability of faults in presence of X-values. It overcomes the principal inaccuracy and pessimism of classical algorithms when X-values are considered. This accuracy is achieved by mapping the test generation problem to an instance of quantified Boolean formula (QBF) satisfiability. The resulting fault coverage improvement is shown by experimental results on ISCAS benchmark and larger industrial circuits.
BibTeX:
@inproceedings{HilleKEWB2013,
  author = {Hillebrecht, Stefan and Kochte, Michael A. and Erb, Dominik and Wunderlich, Hans-Joachim and Becker, Bernd},
  title = {{Accurate QBF-based Test Pattern Generation in Presence of Unknown Values}},
  booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe (DATE'13)},
  publisher = {IEEE Computer Society},
  year = {2013},
  pages = {436--441},
  keywords = {Unknown values, test generation, ATPG, QBF},
  abstract = {Unknown (X) values may emerge during the design process as well as during system operation and test application. Sources of X-values are for example black boxes, clockdomain boundaries, analog-to-digital converters, or uncontrolled or uninitialized sequential elements. To compute a detecting pattern for a given stuck-at fault, well defined logic values are required both for fault activation as well as for fault effect propagation to observing outputs. In presence of X-values, classical test generation algorithms, based on topological algorithms or formal Boolean satisfiability (SAT) or BDD-based reasoning, may fail to generate testing patterns or to prove faults untestable. This work proposes the first efficient stuck-at fault ATPG algorithm able to prove testability or untestability of faults in presence of X-values. It overcomes the principal inaccuracy and pessimism of classical algorithms when X-values are considered. This accuracy is achieved by mapping the test generation problem to an instance of quantified Boolean formula (QBF) satisfiability. The resulting fault coverage improvement is shown by experimental results on ISCAS benchmark and larger industrial circuits.},
  doi = {http://dx.doi.org/10.7873/DATE.2013.098},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2013/DATE_HilleKEWB2013.pdf}
}
3. Accurate X-Propagation for Test Applications by SAT-Based Reasoning
Kochte, M.A., Elm, M. and Wunderlich, H.-J.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
Vol. 31(12), December 2012, pp. 1908-1919
2012
DOI PDF 
Keywords: Unknown values; stuck-at fault coverage; accurate fault simulation; simulation pessimism
Abstract: Unknown or X-values during test application may originate from uncontrolled sequential cells or macros, from clock or A/D boundaries or from tri-state logic. The exact identification of X-value propagation paths in logic circuits is crucial in logic simulation and fault simulation. In the first case, it enables the proper assessment of expected responses and the effective and efficient handling of X-values during test response compaction. In the second case, it is important for a proper assessment of fault coverage of a given test set and consequently influences the efficiency of test pattern generation. The commonly employed n-valued logic simulation evaluates the propagation of X-values only pessimistically, i.e. the X-propagation paths found by n- valued logic simulation are a superset of the actual propagation paths. This paper presents an efficient method to overcome this pessimism and to determine accurately the set of signals which carry an X-value for an input pattern. As examples, it investigates the influence of this pessimism on the two applications X-masking and stuck-at fault coverage assessment. The experimental results on benchmark and industrial circuits assess the pessimism of classic algorithms and show that these algorithms significantly overestimate the signals with X-values. The experiments show that overmasking of test data during test compression can be reduced by an accurate analysis. In stuck-at fault simulation, the coverage of the test set is increased by the proposed algorithm without incurring any overhead.
BibTeX:
@article{KochtEW2012,
  author = {Kochte, Michael A. and Elm, Melanie and Wunderlich, Hans-Joachim},
  title = {{Accurate X-Propagation for Test Applications by SAT-Based Reasoning}},
  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)},
  publisher = {IEEE Computer Society},
  year = {2012},
  volume = {31},
  number = {12},
  pages = {1908--1919},
  keywords = {Unknown values; stuck-at fault coverage; accurate fault simulation; simulation pessimism},
  abstract = {Unknown or X-values during test application may originate from uncontrolled sequential cells or macros, from clock or A/D boundaries or from tri-state logic. The exact identification of X-value propagation paths in logic circuits is crucial in logic simulation and fault simulation. In the first case, it enables the proper assessment of expected responses and the effective and efficient handling of X-values during test response compaction. In the second case, it is important for a proper assessment of fault coverage of a given test set and consequently influences the efficiency of test pattern generation. The commonly employed n-valued logic simulation evaluates the propagation of X-values only pessimistically, i.e. the X-propagation paths found by n- valued logic simulation are a superset of the actual propagation paths. This paper presents an efficient method to overcome this pessimism and to determine accurately the set of signals which carry an X-value for an input pattern. As examples, it investigates the influence of this pessimism on the two applications X-masking and stuck-at fault coverage assessment. The experimental results on benchmark and industrial circuits assess the pessimism of classic algorithms and show that these algorithms significantly overestimate the signals with X-values. The experiments show that overmasking of test data during test compression can be reduced by an accurate analysis. In stuck-at fault simulation, the coverage of the test set is increased by the proposed algorithm without incurring any overhead.},
  doi = {http://dx.doi.org/10.1109/TCAD.2012.2210422},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2012/TCAD_KochtEW2012.pdf}
}
2. Modeling, Verification and Pattern Generation for Reconfigurable Scan Networks
Baranowski, R., Kochte, M.A. and Wunderlich, H.-J.
Proceedings of the IEEE International Test Conference (ITC'12), Anaheim, California, USA, 5-8 November 2012, pp. 1-9
2012
DOI PDF 
Keywords: Reconfigurable scan network, Pattern generation, Pattern retargeting, DFT, IJTAG, P1687
Abstract: Reconfigurable scan architectures allow flexible integration and efficient access to infrastructure in SoCs, e.g. for test, diagnosis, repair or debug. Such scan networks are often hierarchical and have complex structural and functional dependencies. For instance, the IEEE P1687 proposal, known as IJTAG, allows integration of multiplexed scan networks with arbitrary internal control signals. Common approaches for scan verification based on static structural analysis and functional simulation are not sufficient to ensure correct operation of these types of architectures. Hierarchy and flexibility may result in complex or even contradicting configuration requirements to access single elements. Sequential logic justification is therefore mandatory both to verify the validity of a scan network, and to generate the required access sequences. This work presents a formal method for verification of reconfigurable scan architectures, as well as pattern retargeting, i.e. generation of required scan-in data. The method is based on a formal model of structural and functional dependencies. Network verification and pattern retargeting is mapped to a Boolean satisfiability problem, which enables the use of efficient SAT solvers to exhaustively explore the search space of valid scan configurations.
BibTeX:
@inproceedings{BaranKW2012,
  author = {Baranowski, Rafal and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Modeling, Verification and Pattern Generation for Reconfigurable Scan Networks}},
  booktitle = {Proceedings of the IEEE International Test Conference (ITC'12)},
  publisher = {IEEE Computer Society},
  year = {2012},
  pages = {1--9},
  keywords = {Reconfigurable scan network, Pattern generation, Pattern retargeting, DFT, IJTAG, P1687},
  abstract = {Reconfigurable scan architectures allow flexible integration and efficient access to infrastructure in SoCs, e.g. for test, diagnosis, repair or debug. Such scan networks are often hierarchical and have complex structural and functional dependencies. For instance, the IEEE P1687 proposal, known as IJTAG, allows integration of multiplexed scan networks with arbitrary internal control signals. Common approaches for scan verification based on static structural analysis and functional simulation are not sufficient to ensure correct operation of these types of architectures. Hierarchy and flexibility may result in complex or even contradicting configuration requirements to access single elements. Sequential logic justification is therefore mandatory both to verify the validity of a scan network, and to generate the required access sequences. This work presents a formal method for verification of reconfigurable scan architectures, as well as pattern retargeting, i.e. generation of required scan-in data. The method is based on a formal model of structural and functional dependencies. Network verification and pattern retargeting is mapped to a Boolean satisfiability problem, which enables the use of efficient SAT solvers to exhaustively explore the search space of valid scan configurations.},
  doi = {http://dx.doi.org/10.1109/TEST.2012.6401555},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2012/ITC_BaranKW2012.pdf}
}
1. Efficient System-Level Aging Prediction
Hatami, N., Baranowski, R., Prinetto, P. and Wunderlich, H.-J.
Proceedings of the 17th IEEE European Test Symposium (ETS'12), Annecy, France, 28 May-1 June 2012, pp. 164-169
2012
DOI PDF 
Keywords: Non-functional properties; Transaction Level Modeling (TLM); mixed-level simulation; aging analysis; Negative Bias Temperature Instability (NBTI)
Abstract: Non-functional properties (NFPs) of integrated circuits include reliability, vulnerability, power consumption or heat dissipation. Accurate NFP prediction over long periods of system operation poses a great challenge due to prohibitive simulation costs. For instance, in case of aging estimation, the existing low-level models are accurate but not efficient enough for simulation of complex designs. On the other hand, existing techniques for fast high-level simulation do not provide enough details for NFP analysis. The goal of this paper is to bridge this gap by combining the accuracy of low-level models with high-level simulation speed. We introduce an efficient mixed-level NFP prediction methodology that considers both the structure and application of a system. The system is modeled at transaction-level to enable high simulation speed. To maintain accuracy, NFP assessment for cores under analysis is conducted at gate-level by cycle-accurate simulation. We propose effective techniques for cross-level synchronization and idle simulation speed-up. As an example, we apply the technique to analyze aging caused by Negative Bias Temperature Instability in order to identify reliability hot spots. As case studies, several applications on an SoC platform are analyzed. Compared to conventional approaches, the proposed method is from 7 up to 400 times faster with mean error below 0.006%.
BibTeX:
@inproceedings{HatamBPW2012,
  author = {Hatami, Nadereh and Baranowski, Rafal and Prinetto, Paolo and Wunderlich, Hans-Joachim},
  title = {{Efficient System-Level Aging Prediction}},
  booktitle = {Proceedings of the 17th IEEE European Test Symposium (ETS'12)},
  publisher = {IEEE Computer Society},
  year = {2012},
  pages = {164--169},
  keywords = {Non-functional properties; Transaction Level Modeling (TLM); mixed-level simulation; aging analysis; Negative Bias Temperature Instability (NBTI)},
  abstract = {Non-functional properties (NFPs) of integrated circuits include reliability, vulnerability, power consumption or heat dissipation. Accurate NFP prediction over long periods of system operation poses a great challenge due to prohibitive simulation costs. For instance, in case of aging estimation, the existing low-level models are accurate but not efficient enough for simulation of complex designs. On the other hand, existing techniques for fast high-level simulation do not provide enough details for NFP analysis. The goal of this paper is to bridge this gap by combining the accuracy of low-level models with high-level simulation speed. We introduce an efficient mixed-level NFP prediction methodology that considers both the structure and application of a system. The system is modeled at transaction-level to enable high simulation speed. To maintain accuracy, NFP assessment for cores under analysis is conducted at gate-level by cycle-accurate simulation. We propose effective techniques for cross-level synchronization and idle simulation speed-up. As an example, we apply the technique to analyze aging caused by Negative Bias Temperature Instability in order to identify reliability hot spots. As case studies, several applications on an SoC platform are analyzed. Compared to conventional approaches, the proposed method is from 7 up to 400 times faster with mean error below 0.006%.},
  doi = {http://dx.doi.org/10.1109/ETS.2012.6233028},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2012/ETS_HatamBPW2012.pdf}
}
Created by JabRef on 29/11/2016.

Student Theses

  • Simulation-based aging analysis, Z. Georgiev, Dez. 2012 - 21. Juni 2013
  • Test von Rekonfigurierbaren Scan-Netzwerken, M. Schaal, Aug. 2012- Jan. 2012

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