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Model-Based Test Generation for the Efficient Test of Hardware/Software Systems (INTESYS)

                                                                                    DFG-Project: WU 245/9-1   

Functionality in embedded systems is more and more realized by integrated hardware / software systems. Typically, these systems are strongly coupled with technical processes, as for instance the control of a vehicle, which show time-dependent, discrete-continuous dynamics. Testing for the correct functionality of their according design as well as of the final product contributes large sums to the production costs due to its complexity. An efficient method is required for the integrated test of hardware and software in these systems, which respects all the aspects of validation, debug, test and diagnosis.
Model-based development and test gains importance in research and also in industrial practice, as they support the systematic, stepwise refinement of requirements down to the implementation. By using models to describe the functionality of integrated hard- and software systems a higher efficiency of their test can be achieved. The central goal of this project is the generation of tests for the functionality and structure of an embedded hardware / software system from its system model along with an automatic evaluation and failure diagnosis.

Publications

Journals and Conference Proceedings
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5. Test Pattern Generation in Presence of Unknown Values Based on Restricted Symbolic Logic
Erb, D., Scheibler, K., Kochte, M.A., Sauer, M., Wunderlich, H.-J. and Becker, B.
Proceedings of the IEEE International Test Conference (ITC'14), Seattle, Washington, USA, 20-23 October 2014, pp. 1-10
2014
DOI PDF 
Keywords: SAT, QBF, test generation, ATPG, Unknown values, Restricted symbolic logic
Abstract: Test generation algorithms based on standard n-valued logic algebras are pessimistic in presence of unknown (X) values, overestimate the number of signals with X-values and underestimate fault coverage. Recently, an ATPG algorithm based on quantified Boolean formula (QBF) has been presented, which is accurate in presence of X-values but has limits with respect to runtime, scalability and robustness. In this paper, we consider ATPG based on restricted symbolic logic (RSL) and demonstrate its potential. We introduce a complete RSL ATPG exploiting the full potential of RSL in ATPG. Experimental results demonstrate that RSL ATPG significantly increases fault coverage over classical algorithms and provides results very close to the accurate QBF-based algorithm. An optimized version of RSL ATPG (together with accurate fault simulation) is up to 618× faster than the QBF-based solution, more scalable and more robust.
BibTeX:
@inproceedings{ErbSKSWB2014,
  author = {Erb, Dominik and Scheibler, Karsten and Kochte, Michael A. and Sauer, Matthias and Wunderlich, Hans-Joachim and Becker, Bernd},
  title = {{Test Pattern Generation in Presence of Unknown Values Based on Restricted Symbolic Logic}},
  booktitle = {Proceedings of the IEEE International Test Conference (ITC'14)},
  year = {2014},
  pages = {1--10},
  keywords = {SAT, QBF, test generation, ATPG, Unknown values, Restricted symbolic logic},
  abstract = {Test generation algorithms based on standard n-valued logic algebras are pessimistic in presence of unknown (X) values, overestimate the number of signals with X-values and underestimate fault coverage. Recently, an ATPG algorithm based on quantified Boolean formula (QBF) has been presented, which is accurate in presence of X-values but has limits with respect to runtime, scalability and robustness. In this paper, we consider ATPG based on restricted symbolic logic (RSL) and demonstrate its potential. We introduce a complete RSL ATPG exploiting the full potential of RSL in ATPG. Experimental results demonstrate that RSL ATPG significantly increases fault coverage over classical algorithms and provides results very close to the accurate QBF-based algorithm. An optimized version of RSL ATPG (together with accurate fault simulation) is up to 618× faster than the QBF-based solution, more scalable and more robust.},
  doi = {http://dx.doi.org/10.1109/TEST.2014.7035350},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ITC_ErbSKSWB2014.pdf}
}
4. Adaptive Bayesian Diagnosis of Intermittent Faults
Rodríguez Gómez, L., Cook, A., Indlekofer, T., Hellebrand, S. and Wunderlich, H.-J.
Journal of Electronic Testing: Theory and Applications (JETTA)
Vol. 30(5), 30 September 2014, pp. 527-540
2014
DOI URL PDF 
Keywords: Built-In Self-Test, Built-in diagnosis, Transient faults, Intermittent faults, Bayesian diagnosis
Abstract: With increasing transient error rates, distinguishing intermittent and transient faults is especially challenging. In addition to particle strikes relatively high transient error rates are observed in architectures for opportunistic computing and in technologies under high variations. This paper presents a method to classify faults into permanent, intermittent and transient faults based on some intermediate signatures during embedded test or built-in self-test.
Permanent faults are easily determined by repeating test sessions. Intermittent and transient faults can be identified by the amount of failing test sessions in many cases. For the remaining faults, a Bayesian classification technique has been developed which is applicable to large digital circuits. The combination of these methods is able to identify intermittent faults with a probability of more than 98 %.
BibTeX:
@article{RodriCIHW2014,
  author = {Rodríguez Gómez, Laura and Cook, Alejandro and Indlekofer, Thomas and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
  title = {{Adaptive Bayesian Diagnosis of Intermittent Faults}},
  journal = {Journal of Electronic Testing: Theory and Applications (JETTA)},
  year = {2014},
  volume = {30},
  number = {5},
  pages = {527--540},
  keywords = { Built-In Self-Test, Built-in diagnosis, Transient faults, Intermittent faults, Bayesian diagnosis },
  abstract = { With increasing transient error rates, distinguishing intermittent and transient faults is especially challenging. In addition to particle strikes relatively high transient error rates are observed in architectures for opportunistic computing and in technologies under high variations. This paper presents a method to classify faults into permanent, intermittent and transient faults based on some intermediate signatures during embedded test or built-in self-test.
Permanent faults are easily determined by repeating test sessions. Intermittent and transient faults can be identified by the amount of failing test sessions in many cases. For the remaining faults, a Bayesian classification technique has been developed which is applicable to large digital circuits. The combination of these methods is able to identify intermittent faults with a probability of more than 98 %.}, url = { http://link.springer.com/article/10.1007/s10836-014-5477-1 }, doi = {http://dx.doi.org/10.1007/s10836-014-5477-1}, file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/JETTA_RodriCIHW2014.pdf} }
3. Exact Logic and Fault Simulation in Presence of Unknowns
Erb, D., Kochte, M.A., Sauer, M., Hillebrecht, S., Schubert, T., Wunderlich, H.-J. and Becker, B.
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Vol. 19(3), June 2014, pp. 28:1-28:17
2014
DOI PDF 
Keywords: Algorithms, Reliability, Unknown values, simulation pessimism, exact logic simulation, exact fault simulation, SAT
Abstract: Logic and fault simulation are essential techniques in electronic design automation. The accuracy of standard simulation algorithms is compromised by unknown or X-values. This results in a pessimistic overestimation of X-valued signals in the circuit and a pessimistic underestimation of fault coverage.
This work proposes efficient algorithms for combinational and sequential logic as well as for stuck-at and transition-delay fault simulation that are free of any simulation pessimism in presence of unknowns. The SAT-based algorithms exactly classifiy all signal states. During fault simulation, each fault is accurately classified as either undetected, definitely detected, or possibly detected.
The pessimism with respect to unknowns present in classic algorithms is thoroughly investigated in the experimental results on benchmark circuits. The applicability of the proposed algorithms is demonstrated on larger industrial circuits. The results show that, by accurate analysis, the number of detected faults can be significantly increased without increasing the test-set size.
BibTeX:
@article{ErbKSHSWB2014,
  author = {Erb, Dominik and Kochte, Michael A. and Sauer, Matthias and Hillebrecht, Stefan and Schubert, Tobias and Wunderlich, Hans-Joachim and Becker, Bernd},
  title = {{Exact Logic and Fault Simulation in Presence of Unknowns}},
  journal = {ACM Transactions on Design Automation of Electronic Systems (TODAES)},
  year = {2014},
  volume = {19},
  number = {3},
  pages = {28:1--28:17},
  keywords = {Algorithms, Reliability, Unknown values, simulation pessimism, exact logic simulation, exact fault simulation, SAT},
  abstract = {Logic and fault simulation are essential techniques in electronic design automation. The accuracy of standard simulation algorithms is compromised by unknown or X-values. This results in a pessimistic overestimation of X-valued signals in the circuit and a pessimistic underestimation of fault coverage.
This work proposes efficient algorithms for combinational and sequential logic as well as for stuck-at and transition-delay fault simulation that are free of any simulation pessimism in presence of unknowns. The SAT-based algorithms exactly classifiy all signal states. During fault simulation, each fault is accurately classified as either undetected, definitely detected, or possibly detected.
The pessimism with respect to unknowns present in classic algorithms is thoroughly investigated in the experimental results on benchmark circuits. The applicability of the proposed algorithms is demonstrated on larger industrial circuits. The results show that, by accurate analysis, the number of detected faults can be significantly increased without increasing the test-set size.}, doi = {http://dx.doi.org/10.1145/2611760}, file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/TODAES_ErbKSHSWB2014.pdf} }
2. Diagnosis of Multiple Faults with Highly Compacted Test Responses
Cook, A. and Wunderlich, H.-J.
Proceedings of the 19th IEEE European Test Symposium (ETS'14), Paderborn, Germany, 26-30 May 2014, pp. 27-30
2014
DOI PDF 
Keywords: Multiple Faults, Diagnosis, Response Compaction
Abstract: Defects cluster, and the probability of a multiple fault is significantly higher than just the product of the single fault probabilities. While this observation is beneficial for high yield, it complicates fault diagnosis. Multiple faults will occur especially often during process learning, yield ramp-up and field return analysis.
In this paper, a logic diagnosis algorithm is presented which is robust against multiple faults and which is able to diagnose multiple faults with high accuracy even on compressed test responses as they are produced in embedded test and built-in self-test. The developed solution takes advantage of the linear properties of a MISR compactor to identify a set of faults likely to produce the observed faulty signatures. Experimental results show an improvement in accuracy of up to 22 % over traditional logic diagnosis solutions suitable for comparable compaction ratios.
BibTeX:
@inproceedings{CookW2014,
  author = {Cook, Alejandro and Wunderlich, Hans-Joachim},
  title = {{Diagnosis of Multiple Faults with Highly Compacted Test Responses}},
  booktitle = {Proceedings of the 19th IEEE European Test Symposium (ETS'14)},
  year = {2014},
  pages = { 27--30 },
  keywords = {Multiple Faults, Diagnosis, Response Compaction},
  abstract = {Defects cluster, and the probability of a multiple fault is significantly higher than just the product of the single fault probabilities. While this observation is beneficial for high yield, it complicates fault diagnosis. Multiple faults will occur especially often during process learning, yield ramp-up and field return analysis.
In this paper, a logic diagnosis algorithm is presented which is robust against multiple faults and which is able to diagnose multiple faults with high accuracy even on compressed test responses as they are produced in embedded test and built-in self-test. The developed solution takes advantage of the linear properties of a MISR compactor to identify a set of faults likely to produce the observed faulty signatures. Experimental results show an improvement in accuracy of up to 22 % over traditional logic diagnosis solutions suitable for comparable compaction ratios.}, doi = {http://dx.doi.org/10.1109/ETS.2014.6847796}, file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ETS_CookW2014.pdf} }
1. Incremental Computation of Delay Fault Detection Probability for Variation-Aware Test Generation
Wagner, M. and Wunderlich, H.-J.
Proceedings of the 19th IEEE European Test Symposium (ETS'14), Paderborn, Germany, 26-30 May 2014, pp. 81-86
2014
DOI PDF 
Keywords: delay test, process variations, delay test quality
Abstract: Large process variations in recent technology nodes present a major challenge for the timing analysis of digital integrated circuits. The optimization decisions of a statistical delay test generation method must therefore rely on the probability of detecting a target delay fault with the currently chosen test vector pairs. However, the huge number of probability evaluations in practical applications creates a large computational overhead.
To address this issue, this paper presents the first incremental delay fault detection probability computation algorithm in the literature, which is suitable for the inner loop of automatic test pattern generation methods. Compared to Monte Carlo simulations of NXP benchmark circuits, the new method consistently shows a very large speedup and only a small approximation error.
BibTeX:
@inproceedings{WagneW2014,
  author = {Wagner, Marcus and Wunderlich, Hans-Joachim},
  title = {{Incremental Computation of Delay Fault Detection Probability for Variation-Aware Test Generation}},
  booktitle = {Proceedings of the 19th IEEE European Test Symposium (ETS'14)},
  year = {2014},
  pages = { 81--86 },
  keywords = {delay test, process variations, delay test quality},
  abstract = {Large process variations in recent technology nodes present a major challenge for the timing analysis of digital integrated circuits. The optimization decisions of a statistical delay test generation method must therefore rely on the probability of detecting a target delay fault with the currently chosen test vector pairs. However, the huge number of probability evaluations in practical applications creates a large computational overhead.
To address this issue, this paper presents the first incremental delay fault detection probability computation algorithm in the literature, which is suitable for the inner loop of automatic test pattern generation methods. Compared to Monte Carlo simulations of NXP benchmark circuits, the new method consistently shows a very large speedup and only a small approximation error.}, doi = {http://dx.doi.org/10.1109/ETS.2014.6847805}, file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ETS_WagneW2014.pdf} }
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Project Partner

  • Institut für Automatisierungs- und Softwaretechnik
    IAS

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