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HiPS: High-Performance Simulation for High Quality Small Delay Fault Testing

01.2015 - 12.2016, DAAD/JSPS PPP Japan Project: #57155440  

 

 

Project Description

Variations and imperfections during manufacturing can result in small delay defects, which can point to underlying hardware marginalities that may degrade into early life failures. The detection of such small delay defects in conventional test schemes is highly difficult since the slack along sensitized paths is typically much larger than the defect size. In typical manufacturing tests the majority of small delay defects remains undetected, resulting in low quality and reliability for such mission-critical applications as implanted medical devices, aeronautic control units, car electronics, etc.
Their detection can be facilitated by increasing the test clock frequency, called faster-than-at-speed test (FAST). However, operating the circuit at a frequency much higher than the nominal frequency increases power consumption and noise in the power and clock network. This threatens reliable fault detection and also causes over-testing of the circuit.
To ensure the quality of a given test pattern set, it is not sufficient to simulate the circuit behavior at gate level. Instead, it is  required to simulate timing models at lower abstraction level that reflect filtering, glitches and their impact on the stability of power supply. However, low-level approaches such as SPICE-simulation are inapplicable for large circuits and high number of patterns/faults due to the increasing runtime complexity.


In this work, innovative parallelized algorithms for simulation on graphics processing units (GPUs) shall be developed. By utilizing the many-core programming paradigm and exploiting multiple dimensions of parallelism found in circuit simulation, evaluation with full waveform granularity and support for highly accurate delay models will be enabled, therefore allowing for fast and accurate simulation of small delay faults.

Goals

The development of parallelized delay simulation methods that support non-functional properties (NFPs) with influence on the detection of small delay faults is the first objective of this proposal. The set of NFPs to be covered includes power noise, clock noise and skew, temperature and spatial model/layout dependencies of the chip.
The second objective is the investigation of the correlation between layout structures and parasitic non-functional effects in a circuit, which requires the identification of critical structures that cause excessive delay variation during testing. In order to allow for an accurate simulation for larger circuits within reasonable time, evaluation has to be performed at different levels of abstraction.
The third objective is the accurate simulation of faults and faulty circuit instances to assess the small delay fault coverage of a test pattern set. The proper and accurate modeling of fault mechanisms on a low abstraction level is crucial to represent realistic small delay defects. For this sequential behavior induced by resistive interconnect defects has to be considered. Moreover, the accuracy of scalar coverage metrics, which do not consider such accurate timing models or non-functional properties, is substantially increased. The high accuracy of such efficient fault simulation allows to assess the coverage of faster-than-at-speed tests considering NPFs for large circuit instances.
As a fourth objective, this information will be used to improve the robustness of FAST patterns such that false positive and false negative test results are reduced or completely avoided.

Additional Information

This project is part of the German Academic Exchange Service (DAAD) exchange program "PPP Japan" in collaboration with the Japan Society for the Promotion of Science (JSPS).

Project title (German): "Hochbeschleunigte Simulation für akkuraten Verzögerungsfehlertest"
Grant:
#57155440 (PPP Japan 2j ab 15)

Project Partners (Japan)

Department of Creative Informatics - Kyushu Institute of Technology

  • Prof. Xiaoqing Wen
  • Assist. Prof. Stefan Holst

Poster

 

Journals and Conference Proceedings

Matching entries: 0
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3. GPU-Accelerated Simulation of Small Delay Faults
Schneider, E., Kochte, M.A., Holst, S., Wen, X. and Wunderlich, H.-J.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
Vol. 36(5), May 2017, pp. 829-841
2017
DOI PDF 
Keywords: Circuit faults, Computational modeling, Delays, Instruction sets, Integrated circuit modeling, Logic gates, Fault simulation, graphics processing unit (GPU), parallel, process variation, small gate delay faults, timing-accurate, waveform
Abstract: Delay fault simulation is an essential task during test pattern generation and reliability assessment of electronic circuits. With the high sensitivity of current nano-scale designs towards even smallest delay deviations, the simulation of small gate delay faults has become extremely important. Since these faults have a subtle impact on the timing behavior, traditional fault simulation approaches based on abstract timing models are not sufficient. Furthermore, the detection of these faults is compromised by the ubiquitous variations in the manufacturing processes, which causes the actual fault coverage to vary from circuit instance to circuit instance, and makes the use of timing accurate methods mandatory. However, the application of timing accurate techniques quickly becomes infeasible for larger designs due to excessive computational requirements. In this work, we present a method for fast and waveformaccurate simulation of small delay faults on graphics processing units with exceptional computational performance. By exploiting multiple dimensions of parallelism from gates, faults, waveforms and circuit instances, the proposed approach allows for timing-accurate and exhaustive small delay fault simulation under process variation for designs with millions of gates.
BibTeX:
@article{SchneKHWW2016,
  author = {Schneider, Eric and Kochte, Michael A. and Holst, Stefan and Wen, Xiaoqing and Wunderlich, Hans-Joachim},
  title = {{GPU-Accelerated Simulation of Small Delay Faults}},
  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)},
  year = {2017},
  volume = {36},
  number = {5},
  pages = {829--841},
  keywords = {Circuit faults, Computational modeling, Delays, Instruction sets, Integrated circuit modeling, Logic gates, Fault simulation, graphics processing unit (GPU), parallel, process variation, small gate delay faults, timing-accurate, waveform},
  abstract = {Delay fault simulation is an essential task during test pattern generation and reliability assessment of electronic circuits. With the high sensitivity of current nano-scale designs towards even smallest delay deviations, the simulation of small gate delay faults has become extremely important. Since these faults have a subtle impact on the timing behavior, traditional fault simulation approaches based on abstract timing models are not sufficient. Furthermore, the detection of these faults is compromised by the ubiquitous variations in the manufacturing processes, which causes the actual fault coverage to vary from circuit instance to circuit instance, and makes the use of timing accurate methods mandatory. However, the application of timing accurate techniques quickly becomes infeasible for larger designs due to excessive computational requirements. In this work, we present a method for fast and waveformaccurate simulation of small delay faults on graphics processing units with exceptional computational performance. By exploiting multiple dimensions of parallelism from gates, faults, waveforms and circuit instances, the proposed approach allows for timing-accurate and exhaustive small delay fault simulation under process variation for designs with millions of gates.},
  doi = {http://dx.doi.org/10.1109/TCAD.2016.2598560},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2016/TCAD_SchneKHWW2016.pdf}
}
2. Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test
Holst, S., Schneider, E., Wen, X., Kajihara, S., Yamato, Y., Wunderlich, H.-J. and Kochte, M.A.
Proceedings of the 25th IEEE Asian Test Symposium (ATS'16), Hiroshima, Japan, 21-24 November 2016, pp. 19-24
2016
DOI PDF 
Abstract: IR-drop induced false capture failures and test clock stretch are severe problems in at-speed scan testing. We propose a new method to efficiently and accurately identify these problems. For the first time, our approach considers the additional dynamic power caused by glitches, the spatial and temporal distribution of all toggles, and their impact on both logic paths and the clock tree without time-consuming electrical simulations.
BibTeX:
@inproceedings{HolstSWKYWK2016,
  author = {Holst, Stefan and Schneider, Eric and Wen, Xiaoqing and Kajihara, Seiji and Yamato, Yuta and Wunderlich, Hans-Joachim and Kochte, Michael A.},
  title = {{Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test}},
  booktitle = {Proceedings of the 25th IEEE Asian Test Symposium (ATS'16)},
  year = {2016},
  pages = {19--24},
  abstract = {IR-drop induced false capture failures and test clock stretch are severe problems in at-speed scan testing. We propose a new method to efficiently and accurately identify these problems. For the first time, our approach considers the additional dynamic power caused by glitches, the spatial and temporal distribution of all toggles, and their impact on both logic paths and the clock tree without time-consuming electrical simulations.},
  doi = {http://dx.doi.org/10.1109/ATS.2016.49},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2016/ATS_HolstSWKYWK2016.pdf}
}
1. Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch
Asada, K., Wen, X., Holst, S., Miyase, K., Kajihara, S., Kochte, M.A., Schneider, E., Wunderlich, H.-J. and Qian, J.
Proceedings of the 24th IEEE Asian Test Symposium (ATS'15), Mumbai, India, 22-25 November 2015, pp. 103-108
ATS 2015 Best Paper Award
2015
DOI PDF 
Keywords: launch switching activity, IR-drop, logic path, clock path, false capture failure, test clock stretch, X-filling
Abstract: IR-drop induced by launch switching activity (LSA) in capture mode during at-speed scan testing increases delay along not only logic paths (LPs) but also clock paths (CPs). Excessive extra delay along LPs compromises test yields due to false capture failures, while excessive extra delay along CPs compromises test quality due to test clock stretch. This paper is the first to mitigate the impact of LSA on both LPs and CPs with a novel LCPA (Logic/Clock-Path-Aware) at-speed scan test generation scheme, featuring (1) a new metric for assessing the risk of false capture failures based on the amount of LSA around both LPs and CPs, (2) a procedure for avoiding false capture failures by reducing LSA around LPs or masking uncertain test responses, and (3) a procedure for reducing test clock stretch by reducing LSA around CPs. Experimental results demonstrate the effectiveness of the LCPA scheme in improving test yields and test quality.
BibTeX:
@inproceedings{AsadaWHMKKSWQ2015,
  author = {Asada, Koji and Wen, Xiaoqing and Holst, Stefan and Miyase, Kohei and Kajihara, Seiji and Kochte, Michael A. and Schneider, Eric and Wunderlich, Hans-Joachim and Qian, Jun},
  title = {{Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch}},
  booktitle = {Proceedings of the 24th IEEE Asian Test Symposium (ATS'15)},
  year = {2015},
  pages = {103-108},
  keywords = { launch switching activity, IR-drop, logic path, clock path, false capture failure, test clock stretch, X-filling },
  abstract = {IR-drop induced by launch switching activity (LSA) in capture mode during at-speed scan testing increases delay along not only logic paths (LPs) but also clock paths (CPs). Excessive extra delay along LPs compromises test yields due to false capture failures, while excessive extra delay along CPs compromises test quality due to test clock stretch. This paper is the first to mitigate the impact of LSA on both LPs and CPs with a novel LCPA (Logic/Clock-Path-Aware) at-speed scan test generation scheme, featuring (1) a new metric for assessing the risk of false capture failures based on the amount of LSA around both LPs and CPs, (2) a procedure for avoiding false capture failures by reducing LSA around LPs or masking uncertain test responses, and (3) a procedure for reducing test clock stretch by reducing LSA around CPs. Experimental results demonstrate the effectiveness of the LCPA scheme in improving test yields and test quality.},
  doi = {http://dx.doi.org/10.1109/ATS.2015.25},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/ATS_AsadaWHMKKSWQ2015.pdf}
}
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