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Deterministic Logic Built-In Self-Test

09.2000 - 09.2003, Philips-Project    

Short Description

The accelerated increase of the integrated circuits (IC) size and of the gap between the internal clock frequencies and the I/O frequencies makes the external IC testing more and more difficult and costly due to the corresponding rises of the tester memory requirements and of the test time. In this context, built-in self-test (BIST) solutions became an attractive alternative, since they allow precision measurements on-chip in a relatively short time.

The picture above sketches the structure STUMPS (self-test using MISR and parallel shift register sequence generator) architecture of the considered f the deterministic logic BIST (DLBIST) approach. Here a linear feedback shift register (LFSR) generates a pseudo-random sequence, which is mapped afterwards to a deterministic sequence with the help of a module, implementing a bit flipping function (BFF), and of a couple of XOR slots. This deterministic sequence is filled in the circuit logic, assumed to be full scanable and BIST ready (no unknown value can be propagated to the signature analyser, which is a multi-input shift register (MISR)). The test is controlled with the help of a pattern counter (bist_patcnt), of a bit counter (bist_patcnt) and of a control unit (bist_ctrl). The interaction of the whole architecture with the environment is coordinated by a test controlling block (TCB).

The goal of this project is to develop new ideas and approaches to enhance the performance and the versatility of the Deterministic Logic Self-Test. The topics addressed in this project, carried out by the University of Stuttgart and Philips, include issues like Improving Pattern Embedding and cpu Run-Time, the implementation of a Built-Out Self-Test (BOST), the synthesis of an X-Masking Logic (XML), or the enlargement of the covered fault model space towards delay faults. One of the goals behind all these is to increase the performance of the DLBIST facility, as integrated in the Philips computer aided test (CAT) flow.


Short Presentation of the Topic: Improving Pattern Embedding and cpu Run-Time

With the exception of the BFF module, whose functionality is suggested by the picture below, the synthesis of all the other DLBIST modules is more or less straightforward. Unfortunately generating the BFF for very large designs can take weeks or even months. Due to this reason the BFF synthesis became the bottleneck of the Philips CAT flow and of enlarging the DLBIST fault model space to include also the gate-delay faults. Related to the second requirement, one expects a significant increase of the number of deterministic patterns, which should be embedded in pseudo-random ones, so the reduction of the cpu run-time becomes more critical for a delay test using the DLBIST approach.

The goal of this research topic is to reduce the time complexity of the BFF generation, such that it could be performed in maximum one day, independently of the design size and of the targeted fault efficiency. As well, the size of the BFF logic should remain as small as possible.

Developed Software

 

 


 

Resulted Publications

 

Journals and Conference Proceedings
  • Deterministic Logic BIST for Transition Fault Testing
    V. Gherman, H.-J. Wunderlich, J. Schlöffel, M. Garbers
    IEEE European Test Symposium (ETS), 2006, pp. 123-128.

  • Implementing a Scheme for External Deterministic Self-Test
    A. W. Hakmi, V. Gherman, H.-J. Wunderlich, M. Garbers, J. Schlöffel
    IEEE VLSI Test Symposium (VTS), 2005, pp. 48-56.

  • Efficient Pattern Mapping for Deterministic Logic BIST
    V. Gherman, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, M. Garbers
    IEEE International Test Conference (ITC), 2004, pp. 48-56.

  • X-Masking During Logic BIST and its Impact on Defect Coverage
    Y. Tang, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, P. Engelke, I. Polian, B. Becker
    IEEE International Test Conference (ITC), 2004, pp. 442-451.

  • Efficient Pattern Mapping for Deterministic Logic BIST
    V. Gherman, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke
    IEEE European Test Symposium (ETS), 2004, pp. 327-332.
    (Informal track)

  • Impact of Test Point Insertion on Silicon Area and Timing During Layout
    H. Vranken, H.-J. Wunderlich, F.S. Sapei
    IEEE Design, Automation and Test in Europe (DATE), Paris (France), 2004, pp. 810-815.

  • Combining Deterministic Logic BIST with Test Point Insertion
    H. Vranken, F. Meister, H.-J. Wunderlich
    IEEE European Test Workshop (ETW), Korfu (Greece), 2002, pp. 389-394.

Workshop Contributions
  • Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST
    P. Engelke, V. Gherman, I. Polian, Y. Tang, H.-J. Wunderlich, B. Becker
    IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS) , Sopron, Hungary, 2005.

  • Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST
    P. Engelke, V. Gherman, I. Polian, Y. Tang, H.-J. Wunderlich, B. Becker
    17th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Innsbruck, Austria, 2005.

  • DLBIST for Delay Testing
    V. Gherman, H.-J. Wunderlich, M. Garbers, J. Schlöffel
    17th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Innsbruck, Austria, 2005.

  • Implementing a Scheme for External Deterministic Self-Test
    A. W. Hakmi, H.-J. Wunderlich, V. Gherman, M. Garbers, J. Schlöffel
    17th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Innsbruck, Austria, 2005.

  • X-Masking During Logic BIST and its Impact on Defect Coverage
    Y. Tang, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, P. Engelke, I. Polian, B. Becker
    International Workshop on Test Resource Partitioning (TRP) , Napa Valley (CA, USA), 2004.

  • Masking X-Responses During Deterministic Self-Test
    Y. Tang, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Garbers, J.Schlöffel
    16th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Dresden, Germany, 2004.

 

Diploma and Master Works

 

  • Implementierung einer externer X-Maskierungslogik für BIST
    T. Laun, Y. Tang, H.-J. Wunderlich
    Universität Stuttgart, Diplomarbeit, February 2005.

  • Implementing a Scheme for External Deterministic Self-Test
    A.W. Hakmi, Y. Tang, V. Gherman, H.-J. Wunderlich
    Universität Stuttgart, Diplomarbeit, November 2003.

  • Efficient Test Response Compaction Circuits for Space Compaction of Test Responses
    T. Bergmann, H. Vranken, Y. Tang, H.-J. Wunderlich
    Universität Stuttgart, Diplomarbeit, September 2003.

  • Exploring the Impact of Test Points on Silicon Area and Timing During Layout
    F.S. Sapei, H. Vranken, H.-J. Wunderlich
    Universität Stuttgart, Diplomarbeit, Juli 2003.

 


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