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Development of Concepts and Methods for Reliability Evaluation of Mechatronic Systems in Early Development Phases - DFG Forschergruppe 460

09.2002 - 12.2009, DFG-Researcher Group: WU 245/3-1, 3-2, 3-3    


Sub-Project TP6: Methods for Evaluation and Improvement of the
Reliability of Data-Processing Microelectronic Hardware Components

 


The reliability of a complex mechanical system highly depends on the reliability of the Data Processing "Embedded System". The aim of the project is the evaluation and improvement of the reliability of the underlying Micro-Electronic Hardware for the Data Processing System in early phases of the design. The functionality of the embedded system is implemented in both Hardware and Software, in the context of Hardware / Software Codesign, hence the reliability issues of both areas cannot be seperated. The design complexity of the hardware part in embedded systems has been rapidly increasing. This gave rise to three dominant sources of errors:

  • Design errors.

  • Production defects.

  • Permenant, transient, and intermittent faults during operation.

Illustration TP6-1 below shows the life cycle of a microelectronic system and the sources of errors that might arise in the different phases.

Figure TP6-1: Sources of errors in the life cycle of a microelectronic system

Usually the differnt kinds of errors are considered in different phases of the design. Nevertheless, deeper analysis shows that these errors can be approached with similar algorithms, which rises the issue of having them all considered, through the use of a unified method, as early as possible in the design cycle. In order to support the recognition of the above mentioned errors and tolerance against them at the beginning of the design, procedures are to be compiled into two areas:

 

  1. Development of a uniform method for the recognition and diagnosis of the errors.

  2. Automatic design of fault tolerant circuits: The so far different, partially contradictory, procedures for the design of verifiable circuits ("Synthesis for Verifiability), testable and self-checkable circuits ("Synthesis for Testability") and fault tolerant and online testable circuits are to be unified. The reliability of such circuits is to be verified with the procedures developed in 1. In praticualr, the new requirements resulting from the current technology development (e.g. ultra-high integrated systems) and new possibilites (e.g. self recognition and self repair) are to be considered. 

 


 

Poster:

Click Here to view a poster of the work. (pdf file 1.3MB)


Publications:

 

  • Bewertung und Verbesserung der Zuverlässigkeit von mikroelektronischen Komponenten in mechatronischen Systemen
    Hans-Joachim Wunderlich, Melanie Elm , Michael Kochte
    In: Bernd Bertsche, Peter Göhner, Uwe Jensen, Wolfgang Schinköthe, Hans-Joachim Wunderlich: Zuverlässigkeit mechatronischer Systeme - Grundlagen und Bewertung in frühen Entwicklungsphasen
    Springer-Verlag Berlin Heidelberg, 2009
    ISBN: 9783540850915
  • Concurrent Self-Test with Partially Specified Patterns For Low Test Latency and Overhead
    Michael A. Kochte, Christian G. Zoellin, Hans-Joachim Wunderlich
    IEEE European Test Symposim (ETS), 2009
  • Test Exploration and Validation Using Transaction Level Models
    M. A. Kochte, C. G. Zoellin, M.E. Imhof, R.S. Khaligh, M. Radetzki, H.J. Wunderlich, S. Di Carlo, P. Prinetto
    Design, Automation and Test in Europe Conference (DATE), 2009
  • Zur Zuverlässigkeitsmodellierung von Hardware-Software-Systemen
    M. Kochte, R. Baranowski, H.-J. Wunderlich
    2. GMM/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE), 29.09 - 01.10.2008, Ingolstadt, Germany
  • Selective Hardening in Early Design Steps
    C. G. Zoellin, H.-J. Wunderlich, I. Polian, B. Becker
    13th IEEE European Test Symposium (ETS), Lago Maggiore, Italy, May 25-29, 2008, pp. 185-190
  • Best paper award: Test Set Stripping Limiting the Maximum Number of Specified Bits
    M. A. Kochte, C. G. Zoellin, M. E. Imhof, H.-J. Wunderlich
    4th IEEE International Symposium on Electronic Design, Test & Applications (DELTA'08), Hong Kong, January 23-25, 2008, pp. 581-586
  • Domänenübergreifende Zuverlässigkeitsbewertung in frühen Entwicklungsphasen unter Berücksichtigung von Wechselwirkungen
    M. Wedel, P. Göhner, J. Gäng, B. Bertsche, H.-J. Wunderlich, T. Arnaout
    In: 5. Paderborner Workshop "Entwurf mechatronischer Systeme", J. Gausemeier et al. (ed.), Bd. 210, Paderborn, Germany, March 22-23, 2007, pp. 257-272
  • Some Common Aspects of Design Validation, Debug and Diagnosis
    T. Arnaout, G. Bartsch, H.-J. Wunderlich
    Proceedings of the 3rd IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06),
    pp. 3-8; January 2006, Kuala Lumpur, Malaysia (pdf 232KB)
  • On the Reliability Evaluation of SRAM-Based FPGA Designs
    O. Héron, T. Arnaout, H.-J. Wunderlich
    Proceedings of the 15th IEEE International Conference on Field Programmable Logic and Applications (FPL'05),
    pp. 403-408; August 2005, Tampere, Finland (pdf 128KB)
  • From Embedded Test to Embedded Diagnosis
    H.-J. Wunderlich
    IEEE European Test Sypmposium (ETS),
    pp. 216-221; May 2005, Tallinn, Estonia (pdf 215KB)
  • Frühe Zuverlässigkeitsanalyse mechatronischer Systeme (Early Reliability Analysis for Mechatronic Systems)
    P. Jäger, B. Bertsche, T. Arnaout, H.-J. Wunderlich
    VDI-22 Tagung Technische Zuverlässigkeit (TTZ'05),
    April 2005, Stuttgart, Deutschland (pdf 240KB)
  • Reliability Considerations for Mechatronic Systems on the Basis of a State Model
    P. Göhner, E. Zimmer, T. Arnaout, H.-J. Wunderlich
    Proceeding of the Dependability and Fault Tolerance Workshop; 17thInternational Conference on Architecture of Computing Systems (ARCS'04),
    pp. 106-112; March 2004, Augsburg, Germany (pdf 48KB)

 


 

Workshop contributions:

 

  • On the Reliability Modeling of Hardware-Software-Systems
    M. Kochte, R. Baranowski, H.-J. Wunderlich
    1st IEEE Workshop on Design for Reliability and Variability (DRV 2008)
    October 30-31, 2008, Santa Clara, CA, USA
  • Modellierung der Testinfrastruktur auf der Transaktionsebene
    M. A. Kochte, C. G. Zoellin, M.E. Imhof, R.S. Khaligh, M. Radetzki, H.J. Wunderlich, S. Di Carlo, P. Prinetto
    21. Workshop Testmethoden und Zuverlaessigkeit von Schaltungen und Systemen
    2009, Bremen, Germany

 


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