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AZTEKE

03.2002 - 02.2005, BMBF-Project: 01M3063C    

Applikationsspezifische Testmethodik für hochkomplexe Systeme der Kommunikations- und Kraftfahrzeugtechnik


Short Description

The focus of this project is on highly efficient design for test (DFT) and built-in self test technologies for systems on a chip (SoCs). Together with academic and industrial partners we develop methods and tools that replace test functions that run on test machines by on-chip test functions. The main objective is a "low cost" test in combination with a high fault coverage also for dynamic fault effects. The goal of this project is to develop new ideas and approaches to enhance the performance and the versatility of the Deterministic Logic Self-Test. The topics addressed here include issues like the optimization of the Deterministic Logic Built-In Self-Test (DLBIST), the development of a new architecture called External Deterministic Self-Test or Built-Out Self-Test (BOST), the defect coverage evaluation of a pseudo-random test sequence in which deterministic patterns have been embedded, the synthesis of X-Masking Logic (XML) and its impact on unmodeled fault coverage, and the enlargement of the covered fault model space towards delay faults.


POSTER

Click Here to view a poster of the work. (pdf file 287KB)


Resulted Publications

 

    Journals and Conference Proceedings
    • Deterministic Logic BIST for Transition Fault Testing
      V. Gherman, H.-J. Wunderlich, J. Schlöffel, M. Garbers
      IEEE European Test Symposium (ETS), 2006, pp. 123-128.
    • Implementing a Scheme for External Deterministic Self-Test
      A. W. Hakmi, V. Gherman, H.-J. Wunderlich, M. Garbers, J. Schlöffel
      IEEE VLSI Test Symposium (VTS), 2005, pp. 48-56.
    • Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST
      P. Engelke, V. Gherman, I. Polian, Y. Tang, H.-J. Wunderlich, B. Becker
      IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS) , Sopron, Hungary, 2005.
    • Efficient Pattern Mapping for Deterministic Logic BIST
      V. Gherman, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, M. Garbers
      IEEE International Test Conference (ITC), 2004, pp. 48-56.

    • X-Masking During Logic BIST and its Impact on Defect Coverage
      Y. Tang, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, P. Engelke, I. Polian, B. Becker
      IEEE International Test Conference (ITC), 2004, pp. 442-451.

    • Efficient Pattern Mapping for Deterministic Logic BIST
      V. Gherman, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke
      IEEE European Test Symposium (ETS), 2004, pp. 327-332.
      (Informal track)

    • Impact of Test Point Insertion on Silicon Area and Timing During Layout
      H. Vranken, H.-J. Wunderlich, F.S. Sapei
      IEEE Design, Automation and Test in Europe (DATE), Paris (France), 2004, pp. 810-815.

    • Combining Deterministic Logic BIST with Test Point Insertion
      H. Vranken, F. Meister, H.-J. Wunderlich
      IEEE European Test Workshop (ETW), Korfu (Greece), 2002, pp. 389-394.

    Workshop Contributions
    • Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST
      P. Engelke, V. Gherman, I. Polian, Y. Tang, H.-J. Wunderlich, B. Becker
      17th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Innsbruck, Austria, 2005.

    • DLBIST for Delay Testing
      V. Gherman, H.-J. Wunderlich, M. Garbers, J. Schlöffel
      17th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Innsbruck, Austria, 2005.

    • Implementing a Scheme for External Deterministic Self-Test
      A. W. Hakmi, H.-J. Wunderlich, V. Gherman, M. Garbers, J. Schlöffel
      17th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Innsbruck, Austria, 2005.

    • X-Masking During Logic BIST and its Impact on Defect Coverage
      Y. Tang, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, P. Engelke, I. Polian, B. Becker
      International Workshop on Test Resource Partitioning (TRP) , Napa Valley (CA, USA), 2004.

    • Masking X-Responses During Deterministic Self-Test
      Y. Tang, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Garbers, J.Schlöffel
      16th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Dresden, Germany, 2004.

 

Diploma and Master Works

 

  • Implementierung einer externer X-Maskierungslogik für BIST
    T. Laun, Y. Tang, H.-J. Wunderlich
    Universität Stuttgart, Diplomarbeit, February 2005.

  • Implementing a Scheme for External Deterministic Self-Test
    A.W. Hakmi, Y. Tang, V. Gherman, H.-J. Wunderlich
    Universität Stuttgart, Diplomarbeit, November 2003.

  • Efficient Test Response Compaction Circuits for Space Compaction of Test Responses
    T. Bergmann, H. Vranken, Y. Tang, H.-J. Wunderlich
    Universität Stuttgart, Diplomarbeit, September 2003.

  • Exploring the Impact of Test Points on Silicon Area and Timing During Layout
    F.S. Sapei, H. Vranken, H.-J. Wunderlich
    Universität Stuttgart, Diplomarbeit, Juli 2003.

 


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