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Rafal Baranowski

Name:	M.Sc. Rafal Baranowski
Adresse:	Universität Stuttgart Institut für Technische Informatik Pfaffenwaldring 47 D-70569 Stuttgart
Raum:	3.164
Telefon:	(+49) (0)711 / 685-88-221
Telefax:	(+49) (0)711 / 685-88-288
E-Mail:	rafal.baranowski@informatik.uni-stuttgart.de

Sprechstunden

Montags, 11:00 bis 12:00 Uhr

Veröffentlichungen

Efficient System-Level Aging Prediction
N. Hatami, R. Baranowski, P. Prinetto, H.-J. Wunderlich
to appear in Proc. 16th IEEE European Test Symposium (ETS12)
Efficient Multi-level Fault Simulation of HW/SW Systems for Structural Faults
R. Baranowski, S. Di Carlo, N. Hatami, M. E. Imhof, M. A. Kochte, P. Prinetto, H.-J. Wunderlich, C. G. Zoellin
SCIENCE CHINA Information Sciences, Volume 54, Number 9, 2011, pp. 1784-1796
Fail-Safety in Core-Based System Design
R. Baranowski, H.-J. Wunderlich
IEEE International On-Line Testing Symposium (IOLTS'11), Athens, Greece, July 13-15, 2011, pp. 276-281
Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level
Michael A. Kochte, Christian G. Zoellin, Rafal Baranowski, Michael E. Imhof, Hans-Joachim Wunderlich, Nadereh Hatami, Stefano Di Carlo, Paolo Prinetto
IEEE 19th Asian Test Symposium (ATS'10), Shanghai, China, December 1-4, 2010, pp. 3-8
System Reliability Evaluation Using Concurrent Multi-Level Simulation of Structural Faults
Michael A. Kochte, Christian G. Zoellin, Rafal Baranowski, Michael E. Imhof, Hans-Joachim Wunderlich, Nadereh Hatami, Stefano Di Carlo, Paolo Prinetto
International Test Conference (ITC'10), Austin, TX, USA, October 31 - November 5, 2010
Effiziente Simulation von strukturellen Fehlern für die Zuverlässigkeitsanalyse auf Systemebene
Michael A. Kochte, Christian G. Zoellin, Rafal Baranowski, Michael E. Imhof, Hans-Joachim Wunderlich, Nadereh Hatami, Stefano Di Carlo, Paolo Prinetto
4. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE'10), Wildbad Kreuth, Germany, September 13-15, 2010, pp.25-32
Application Dependent Vulnerability of Combinational Circuits
Rafal Baranowski, Hans-Joachim Wunderlich
22nd ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Paderborn, Germany, February 28 - March 2, 2010
Zur Zuverlässigkeitsmodellierung von Hardware-Software-Systemen
On the Reliability Modeling of Hardware-Software-Systems
M. Kochte, R. Baranowski, H.-J. Wunderlich
2. GMM/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE), Ingolstadt, Germany, 29.09 - 01.10.2008, pp. 83-90
On the Reliability Modeling of Embedded Hardware-Software Systems
Michael A. Kochte, Rafal Baranowski, Hans-Joachim Wunderlich
1st IEEE Workshop on Design for Reliability and Variability (DRVW), Santa Clara, CA, USA, October 30-31, 2008

Lehre

Übungen, Seminare, Praktika

SS 2012	Übung: Grundlagen der Rechnerarchitektur Hardwarepraktikum: Rechnerorganisation 2
WS 2011	Übung: Design and Test of Systems on a Chip (SOC) Fachpraktikum: Elements of High-Performance RISC Processors - Design and Synthesis
SS 2011	Seminar: Safety-critical Hardware/Software Systems
	Übung: Hardware Based Fault Tolerance
WS 2010	Fachpraktikum: Elements of High-Performance RISC Processors - Design and Synthesis
SS 2010	Übung: Design and Test of Systems on a Chip (SOC)
WS 2009	Fachpraktikum: Elements of High-Performance RISC Processors - Design and Synthesis
SS 2009	Übung: Design and Test of Systems on a Chip (SOC)
SS 2008	Übung: Formal Verification and Quality Assurance

Master-, Diplom- und Studienarbeiten

SS2011	Integration von Java-basierten DfT Tools in SystemC TLM Simulationen Software Projekt: Fabian Andres, Sebastian Halder, Tobias Weißer
WS2010	Development of an Error Detection and Recovery Technique for a SPARC V8 Processor in FPGA Technology Diplomarbeit Nr. 3097, A. M. Boktor

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