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Michael Kochte

Name:

Dr. rer. nat. Michael Kochte

Address:

University of Stuttgart

Institute of Computer Architecture and Computer Engineering

Pfaffenwaldring 47

D-70569 Stuttgart

Germany

Room:

3.171

Telephone:

(+49) (0)711 / 685 88 361

Telefax:

(+49) (0)711 / 685 88 288

E-Mail:

kochte@iti.uni-stuttgart.de

 


Master Thesis / Diplomarbeiten / Studienarbeiten

Running:

Bachelor thesis:

Hoch-beschleunigte IR-Drop Analyse von int. Schaltungen, P. Hagemann, Mai 2017

Master thesis:

Synthesis of robust reconfigurable scan networks, S. Brandhofer, Juni 2017

Projekt INF:

Hardware-Unterstützung für ein Attestation-System auf OpenRISC Architektur, S. Friz, J. Krawczuk, S. Wick, T. Yüksel, Mai 2017

Completed:

Master thesis:

Realistic gate model for efficient timing analysis of very deep submicron CMOS circuits, D. Murali, Sep 2014 - Mar 2016

Projekt INF:

Switching activity based estimation of IR-drop, D. Hardes, P. Hagemann, M. Knabben, Feb 2015 - Aug 2015

Bachelor thesis:

Adaptierung von Zeitverhalten-Variationen in rekonfigurierbaren Hardwarestrukturen, S. Brandhofer, Oct. 20, 2014 - April 20, 2015

Master thesis:

SAT-basierte Überprüfung der Fehlersicherheit von Schaltungen, M. Tilk, July 28, 2014 - Jan 27, 2015

Projekt INF:

Untersuchung von hardwarebeschleunigten Anwendungen in rekonfigurierbaren Network-on-a-Chip-basierten Systemen, S. Brandhofer, P. Goettlich, A. Lanksweirt, June 1, 2014 - Dec 1, 2014

Master thesis:

Diagnosis based on CED signatures, A. Bernabei, Feb 2014 - Aug 2015

Study thesis (INFOTECH):

OASIS testchip gateway, J. Oberacker, Winter term 2013/2014

Master thesis:

Delay Characterization in FPGA-based Reconfigurable Systems, S. Zhang, 03. Juni. 2013 - 03. Dez. 2013

Master thesis:

Accelerated Computation Using Runtime Partial Reconfiguration, N. Nayak, 27. Mai. 2013 - 26. Nov. 2013

Master thesis:

Simulation-Based Analysis For NBTI Degradation In Combinational CMOS VLSI Circuits, Z. Georgiev, Dez. 2012 - 21. Juni 2013

Master thesis:

Online Self-Test Wrapper for Runtime-Reconfigurable Systems, J. Wang, 3. Dez. 2012 - 2. Juni 2013

Diplomarbeit:

Effiziente mehrwertige Logiksimulation verzögerungsbehafteter Schaltungen auf datenparallelen Architekturen, A. Schöll, Juni 2012- Dez. 2012

Diplomarbeit:

Test von Rekonfigurierbaren Scan-Netzwerken, M. Schaal, Aug. 2012- Jan. 2012

Master Thesis:

Evaluation of Advanced Techniques for Structural FPGA Self-Test, M. Abdelfattah, 2011

Master Thesis:

Evaluation of Host - FPGA Communication Based on Ethernet, Shuo Liu, 2009

Software Praktikum (Sopra):

C++ based netlist processor and framework, Jann Kleen, 2009

Studienarbeit Nr. 2226:

Parallele Fehlersimulation auf GPGPUs, Marcel Schaal, 09.06.2009 - 09.12.2009

Studienarbeit Nr. 2187:

Power and Area Estimation of Error/Dection and Error-Correction Schemes for On-chip Busses, Christoph Hoehne, 15.08.2008 - 27.02.2009

Master Thesis Nr.2803:

Investigation of the Impact of the Error Recovery Distribution on Power and Performance of Networks-on-Chip, Donny Kurnia Sutanyo, 24.07.2008 - 23.01.2009t

Master Thesis Nr.2774:

LEON-Based Multiprocessor System on FPGA Network, Antonio Fernandez Lancho, 15.06.2008 - 15.12.2008

Master Thesis Nr.2773:

Design and Analysis of a Network-on-Chip Infrastructure, Frau Yijun Qu, 15.06.2008 - 15.12.2008

 

 

Projects

Ongoing Projects


SHIVA: Sichere Hardware in der Informationsverarbeitung

Projektseite: SHIVA: Sichere Hardware in der Informationsverarbeitung

Das Projekt „SHIVA: Sichere Hardware in der Informationsverarbeitung“, koordiniert von Prof. Dr. Wunderlich (Institut für Technische Informatik), erforscht Entwurfs- und Verifikationsmethoden zur Steigerung der Sicherheit mikroelektronischer Hardware, beispielsweise aus der Automobilelektronik, der Medizintechnik oder auch der Fertigungstechnik. Es soll damit der Ausschluss einer Manipulation des Systems, der Ausschluss der Beobachtung interner Daten, verwendeter Verfahren und Prozesse und der Schutz des geistigen Eigentums an der Hardware garantiert werden.

seit 02.2016,    

ACCESS: Verification, Test, and Diagnosis of Advanced Scan Infrastructures

Projektseite: ACCESS: Verification, Test, and Diagnosis of Advanced Scan Infrastructures

VLSI designs incorporate specialized instrumentation for post-silicon validation and debug, volume test and diagnosis, as well as in-field system maintenance. Due to the increasing complexity, however, the embedded infrastructure and flexible access mechanisms such as Reconfigurable Scan Networks (RSNs) themselves become a dependability bottleneck.

While efficient verification, test, and diagnosis techniques exist for combinational and some classes of sequential circuits, Reconfigurable Scan Networks (RSNs) still pose a serious challenge. RSNs are controlled via a serial interface and exhibit deeply sequential behavior (cf. IJTAG, IEEE P1687). Due to complex combinational and sequential dependencies, RSNs are beyond the capabilities of existing algorithms for verification, test, and diagnosis which were developed for classical, non-reconfigurable scan networks. The goal of ACCESS is to establish a methodology for efficient verification, test and diagnosis of RSNs to meet stringent reliability, safety and security goals.

seit 08.2014, DFG-Projekt: WU 245/17-1    

OTERA: Online Test Strategies for Reliable Reconfigurable Architectures

Projektseite: Online Test Strategies for Reliable Reconfigurable Architectures

Dynamisch rekonfigurierbare Architekturen ermöglichen eine signifikante Beschleunigung verschiedener Anwendungen durch die Anpassung und Optimierung der Struktur des Systems zur Laufzeit. Permanente und transiente Fehler bedrohen die zuverlässigen Betrieb einer solchen Architektur. Dieses Projekt zielt darauf ab, die Zuverlässigkeit von Laufzeit-rekonfigurierbaren Systemen durch eine neuartige System- Level-Strategie für Online-Tests und Online-Anpassung an Fehler zu erhöhen. Dies wird erreicht durch (a) Scheduling, so dass Tests für rekonfigurierbare Ressourcen mit minimaler Auswirkung auf die Leistung ausgeführt werden, (b) Ressourcen-Management, so dass teilweise fehlerhafte Ressourcen für Komponenten verwendet werden, die den fehlerhaften Teil nicht verwenden, und (c) Online-Uberwachung und Error-Checking. Um eine zuverlässige Rekonfiguration zur Laufzeit zu gewährleisten, wird jeder Rekonfigurationsprozess durch eine neuartige und effiziente Kombination von Online-Struktur- und Funktionstests gründlich getestet. Im Vergleich zu bisherigen Fehlertoleranzkonzepten vermeidet dieser Ansatz die hohen Hardwarekosten von struktureller Redundanz. Die eingesparten Ressourcen können zur weiteren Beschleunigung der Anwendungen verwendet werden. Dennoch deckt das vorgeschlagene Verfahren Fehler in den rekonfigurierbaren Ressourcen, der Anwendungslogik und Fehler im Rekonfigurationsprozess ab.

seit 10.2010, DFG-Projekt: WU 245/10-1, 10-2, 10-3   

Completed Projects


OASIS: Online-Ausfallvorhersage mikroelektronischer Schaltungen mittels Alterungssignaturen

Projektseite: Online-Ausfallvorhersage mikroelektronischer Schaltungen mittels Alterungssignaturen

Mikroelektronische Schaltungen sind, wie auch mechanische Komponenten, lebenszeitbegrenzenden Alterungsprozessen ausgesetzt. Um Ausfälle aufgrund der Alterung vorherzusagen, werden Verfahren entwickelt und untersucht, die online (während des Betriebs) die Leistungsfähigkeit und die noch zu erwartende Lebensdauer bestimmen. Mittels Monitoring werden Betriebsbedingungen und Alterungsindikatoren in einer Infrastruktur analysiert, so dass durch Früherkennung einem Ausfall durch systemtechnische Maßnahmen vorgebeugt werden kann. Neue Wartungskonzepte ermöglichen eine erhebliche Vereinfachung von strukturellen Fehlertoleranzmaßnahmen (z.B. Redundanzkonzepten) selbst in sicherheitskritischen Anwendungen, da gezielte Maßnahmen vor Eintritt altersbedingter Fehlfunktionen ergriffen werden können. Die effektive Lebensdauer eines mikroelektronischen Produkts kann mit Hilfe eines derartigen Online-Monitorings auf ein Vielfaches erhöht werden.

03.2011 - 12.2014, DFG-Projekt: WU 245/11-1    

DAAD Projekt VIGONI: Combining Fault Tolerance and Offline Test Strategies for Nanoscaled Electronics

Projektseite: Combining Fault Tolerance and Offline Test Strategies for Nanoscaled Electronics

Projektpartner: Dipartimento di Automatica e Informatica, Politecnico di Torino

01.2007 - 12.2009, DAAD/Vigoni-Projekt    

Forschergruppe: Konzepte und Methoden zur Ermittlung der Zuverlässigkeit mechatronischer Systeme in frühen Entwicklungsphasen

Projektseite: Konzepte und Methoden zur Ermittlung der Zuverlässigkeit mechatronischer Systeme in frühen Entwicklungsphasen

Die Sicherstellung von bestimmten Zuverlässigkeitsanforderungen in mechatronischen System ist ein wichtiger Entwurfsschritt, insbesondere in Systemen die direkten Einfluss auf deren Benutzer haben. Zur Abschätzung der Systemzuverlässigkeit ist es erforderlich nicht nur einzelne Komponenten, sondern auch deren Interaktion zu berücksichtigen. In diesem Projekt werden Werkzeuge und Techniken untersucht mit denen die Zuverlässigkeit solcher System auf der elektronischen Ebene verbessert werden kann.

09.2002 - 12.2009, DFG-Forschergruppe: WU 245/3-1, 3-2, 3-3    

Publications

Dissertation

Boolean Reasoning for Digital Circuits in Presence of Unknown Values - Application to Test Automation

Accessible at: Online Publikationsverbund der Universität Stuttgart (OPUS)

Other Publications

  • K-J. Lee, P-H. Tang, M. Kochte
    An On-Chip Self-Test Architecture with Test Patterns Recorded in Scan Chains
    Proc. IEEE International Test Conference (ITC), 15-17 November 2016, Paper 16.3
  • Wen-Hsuan Hsu, Michael A. Kochte, Kuen-Jong Lee
    Built-In Test and Diagnosis for TSVs with Different Placement Topologies and Crosstalk Impact Ranges
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Preprint
    27 September 2016, DOI: 10.1109/TCAD.2016.2613928
  • Hsu, W.-H., Kochte M.A., and Lee, K.-J.
    3D-IC Test Architecture for TSVs with Different Impact Ranges of Crosstalk Faults
    Proc. IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
    25-27 April 2016, D19-1, Best paper candidate
  • Yamato, Y.; Wen, X.; Kochte, M.; Miyase, K.; Kajihara, S.; Wang, L.T.
    LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing
    IEEE Design & Test, vol. 30(4), August 2013
    doi: 10.1109/MDT.2012.2221152
  • X. Wen, K. Enokimoto, K. Miyase, Y. Yamato, M. Kochte, S. Kajihara, P. Girard, and M. Tehranipoor
    Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing
    Proc. IEEE VLSI Test Symposium, pp. 166-171, Dana Point, USA, May 2-4, 2011
  • The Blue Gene Team:
    Overview of the IBM Blue Gene/P Project.
    IBM Journal of Research and Development, vol. 52, no. 1/2, 2008.

Book Chapters

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1. Bewertung und Verbesserung der Zuverlässigkeit von mikroelektronischen Komponenten in mechatronischen Systemen
Wunderlich, H.-J., Elm, M. and Kochte, M.A.
in Bertsche, B., Göhner, P., Jensen, U., Schinköthe, W. and Wunderlich, H.-J.(Ed.)
Zuverlässigkeit mechatronischer Systeme: Grundlagen und Bewertung in frühen Entwicklungsphasen, pp. 391-464
ISBN: 978-3-540-85089-2, Springer-Verlag Heidelberg, 2009
2009
DOI  
Abstract: In den letzten Jahrzehnten hat der Anteil der informationsverarbeitenden Komponenten an den Herstellungskosten mechatronischer Systeme rapide zugenommen. In den 70er Jahren machte die Informationsverarbeitung noch ca. 15% des Systems aus. Zu Beginn dieses Jahrtausends sind es bereits über 60% [8.9], wie auch aus Abb. 8.1 hervorgeht. Dieser Zuwachs in den Herstellungskosten ist auf die Zunahme der durch die Informationsverarbeitung realisierten Funktionen zurückzuführen. Sehr deutlich ist diese Zunahme im Automobil zu beobachten. Während das Antiblockiersystem und die digitale Motorsteuerung schon seit Jahren zum Standard gehören, werden nun zunehmend auch Fahrerassistenz- und Infotainmentsysteme ins Kraftfahrzeug integriert. Bei diesen Systemen beginnt die Grenze zwischen klassischer Sicherheits- und Komfortfunktion zu verschwimmen. Die Bandbreite möglichen Fehlverhaltens reicht vom Ausfall des Navigationssystems über Störungen der Zentralverriegelung bis hin zum automatischen Einleiten von Bremsmanövern bei hohen Geschwindigkeiten. Entsprechend ergeben sich hier hohe Anforderungen an die Zuverlässigkeit dieser Systeme.
BibTeX:
@inbook{WundeEK2009,
  author = {Wunderlich, Hans-Joachim and Elm, Melanie and Kochte, Michael A.},
  editor = {Bertsche, Bernd and Göhner, Peter and Jensen, Uwe and Schinköthe, Wolfgang and Wunderlich, Hans-Joachim},
  title = {{Bewertung und Verbesserung der Zuverlässigkeit von mikroelektronischen Komponenten in mechatronischen Systemen}},
  booktitle = {Zuverlässigkeit mechatronischer Systeme: Grundlagen und Bewertung in frühen Entwicklungsphasen},
  publisher = {Springer-Verlag Heidelberg},
  year = {2009},
  pages = {391--464},
  abstract = {In den letzten Jahrzehnten hat der Anteil der informationsverarbeitenden Komponenten an den Herstellungskosten mechatronischer Systeme rapide zugenommen. In den 70er Jahren machte die Informationsverarbeitung noch ca. 15% des Systems aus. Zu Beginn dieses Jahrtausends sind es bereits über 60% [8.9], wie auch aus Abb. 8.1 hervorgeht. Dieser Zuwachs in den Herstellungskosten ist auf die Zunahme der durch die Informationsverarbeitung realisierten Funktionen zurückzuführen. Sehr deutlich ist diese Zunahme im Automobil zu beobachten. Während das Antiblockiersystem und die digitale Motorsteuerung schon seit Jahren zum Standard gehören, werden nun zunehmend auch Fahrerassistenz- und Infotainmentsysteme ins Kraftfahrzeug integriert. Bei diesen Systemen beginnt die Grenze zwischen klassischer Sicherheits- und Komfortfunktion zu verschwimmen. Die Bandbreite möglichen Fehlverhaltens reicht vom Ausfall des Navigationssystems über Störungen der Zentralverriegelung bis hin zum automatischen Einleiten von Bremsmanövern bei hohen Geschwindigkeiten. Entsprechend ergeben sich hier hohe Anforderungen an die Zuverlässigkeit dieser Systeme.},
  doi = {http://dx.doi.org/10.1007/978-3-540-85091-5_8}
}
Created by JabRef on 13/06/2017.

Journal and Conference Proceedings

Matching entries: 0
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64. Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors
Holst, S., Schneider, E., Kawagoe, K., Kochte, M.A., Miyase, K., Wunderlich, H.-J., Kajihara, S. and Wen, X.
to appear in Proceedings of the IEEE International Test Conference (ITC'17), Fort Worth, Texas, USA, 31 October-2 November 2017
2017
 
BibTeX:
@inproceedings{HolstSKKMWKW2017,
  author = {Holst, Stefan and Schneider, Eric and Kawagoe, Koshi and Kochte, Michael A. and Miyase, Kohei and Wunderlich, Hans-Joachim and Kajihara, Seiji and Wen, Xiaoqing},
  title = {{Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors}},
  booktitle = {to appear in Proceedings of the IEEE International Test Conference (ITC'17)},
  year = {2017}
}
63. Trustworthy Reconfigurable Access to On-Chip Infrastructure
Kochte, M.A., Baranowski, R. and Wunderlich, H.-J.
to appear in Proceedings of the 1st International Test Conference in Asia (ITC-Asia'17), Taipei, Taiwan, 13-15 September 2017
2017
 
BibTeX:
@inproceedings{KochtBW2017,
  author = {Kochte, Michael A. and Baranowski, Rafal and Wunderlich, Hans-Joachim},
  title = {{Trustworthy Reconfigurable Access to On-Chip Infrastructure}},
  booktitle = {to appear in Proceedings of the 1st International Test Conference in Asia (ITC-Asia'17)},
  year = {2017}
}
62. Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures
Zhang, H., Bauer, L., Kochte, M.A., Schneider, E., Wunderlich, H.-J. and Henkel, J.
IEEE Transactions on Computers
Vol. 66(6), 1 June 2017, pp. 957-970
2017
DOI PDF 
Keywords: Runtime reconfiguration, aging mitigation, fault-tolerance, resilience, graceful degradation, FPGA
Abstract: Runtime reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) allow area- and power-efficient acceleration of complex applications. However, being manufactured in latest semiconductor process technologies, FPGAs are increasingly prone to aging effects, which reduce the reliability and lifetime of such systems. Aging mitigation and fault tolerance techniques for the reconfigurable fabric become essential to realize dependable reconfigurable architectures. This article presents an accelerator diversification method that creates multiple configurations for runtime reconfigurable accelerators that are diversified in their usage of Configurable Logic Blocks (CLBs). In particular, it creates a minimal number of configurations such that all single-CLB and some multi-CLB faults can be tolerated. For each fault we ensure that there is at least one configuration that does not use that CLB.
Secondly, a novel runtime accelerator placement algorithm is presented that exploits the diversity in resource usage of these configurations to balance the stress imposed by executions of the accelerators on the reconfigurable fabric. By tracking the stress due to accelerator usage at runtime, the stress is balanced both within a reconfigurable region as well as over all reconfigurable regions of the system. The accelerator placement algorithm also considers faulty CLBs in the regions and selects the appropriate configuration such that the system maintains a high performance in presence of multiple permanent faults.
Experimental results demonstrate that our methods deliver up to 3.7x higher performance in presence of faults at marginal runtime costs and 1.6x higher MTTF than state-of-the-art aging mitigation methods.
BibTeX:
@article{ZhangBKSWH2017,
  author = {Zhang, Hongyan and Bauer, Lars and Kochte, Michael A. and Schneider, Eric and Wunderlich, Hans-Joachim and Henkel, Jörg},
  title = {{Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures}},
  journal = {IEEE Transactions on Computers},
  year = {2017},
  volume = {66},
  number = {6},
  pages = {957--970},
  keywords = {Runtime reconfiguration, aging mitigation, fault-tolerance, resilience, graceful degradation, FPGA},
  abstract = {Runtime reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) allow area- and power-efficient acceleration of complex applications. However, being manufactured in latest semiconductor process technologies, FPGAs are increasingly prone to aging effects, which reduce the reliability and lifetime of such systems. Aging mitigation and fault tolerance techniques for the reconfigurable fabric become essential to realize dependable reconfigurable architectures. This article presents an accelerator diversification method that creates multiple configurations for runtime reconfigurable accelerators that are diversified in their usage of Configurable Logic Blocks (CLBs). In particular, it creates a minimal number of configurations such that all single-CLB and some multi-CLB faults can be tolerated. For each fault we ensure that there is at least one configuration that does not use that CLB.
Secondly, a novel runtime accelerator placement algorithm is presented that exploits the diversity in resource usage of these configurations to balance the stress imposed by executions of the accelerators on the reconfigurable fabric. By tracking the stress due to accelerator usage at runtime, the stress is balanced both within a reconfigurable region as well as over all reconfigurable regions of the system. The accelerator placement algorithm also considers faulty CLBs in the regions and selects the appropriate configuration such that the system maintains a high performance in presence of multiple permanent faults.
Experimental results demonstrate that our methods deliver up to 3.7x higher performance in presence of faults at marginal runtime costs and 1.6x higher MTTF than state-of-the-art aging mitigation methods. }, doi = {http://dx.doi.org/10.1109/TC.2016.2616405}, file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2017/TC_ZhangBKSWH2017.pdf} }
61. Specification and Verification of Security in Reconfigurable Scan Networks
Kochte, M.A., Sauer, M., Rodríguez Gómez, L., Raiola, P., Becker, B. and Wunderlich, H.-J.
Proceedings of the 22nd IEEE European Test Symposium (ETS'17), Limassol, Cyprus, 22-26 May 2017
2017
 
Keywords: Keywords-Access Control, On-Chip Infrastructure, Reconfigurable Scan Network, Verification, Side-Channel Attack, IEEE Std 1687, IJTAG, Hardware Security
Abstract: A large amount of on-chip infrastructure, such as design-for-test, debug, monitoring, or calibration, is required for the efficient manufacturing, debug, and operation of complex hardware systems. The access to such infrastructure poses severe system safety and security threats since it may constitute a side-channel exposing internal state, sensitive data, or IP to attackers. Reconfigurable scan networks (RSNs) have been proposed as a scalable and flexible scan-based access mechanism to on-chip infrastructure. The increasing number and variety of integrated infrastructure as well as diverse access constraints over the system lifetime demand for systematic methods for the specification and formal verification of access protection and security properties in RSNs. This work presents a novel method to specify and verify fine-grained access permissions and restrictions to instruments attached to an RSN. The permissions and restrictions are transformed into predicates that are added to a formal model of a given RSN to prove which access properties hold or do not hold.
BibTeX:
@inproceedings{KochtSRRBW2017,
  author = {Kochte, Michael A. and Sauer, Matthias and Rodríguez Gómez, Laura and Raiola, Pascal and Becker, Bernd and Wunderlich, Hans-Joachim},
  title = {{Specification and Verification of Security in Reconfigurable Scan Networks}},
  booktitle = {Proceedings of the 22nd IEEE European Test Symposium (ETS'17)},
  year = {2017},
  keywords = {Keywords-Access Control, On-Chip Infrastructure, Reconfigurable Scan Network, Verification, Side-Channel Attack, IEEE Std 1687, IJTAG, Hardware Security},
  abstract = {A large amount of on-chip infrastructure, such as design-for-test, debug, monitoring, or calibration, is required for the efficient manufacturing, debug, and operation of complex hardware systems. The access to such infrastructure poses severe system safety and security threats since it may constitute a side-channel exposing internal state, sensitive data, or IP to attackers. Reconfigurable scan networks (RSNs) have been proposed as a scalable and flexible scan-based access mechanism to on-chip infrastructure. The increasing number and variety of integrated infrastructure as well as diverse access constraints over the system lifetime demand for systematic methods for the specification and formal verification of access protection and security properties in RSNs. This work presents a novel method to specify and verify fine-grained access permissions and restrictions to instruments attached to an RSN. The permissions and restrictions are transformed into predicates that are added to a formal model of a given RSN to prove which access properties hold or do not hold.}
}
60. GPU-Accelerated Simulation of Small Delay Faults
Schneider, E., Kochte, M.A., Holst, S., Wen, X. and Wunderlich, H.-J.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
Vol. 36(5), May 2017, pp. 829-841
2017
DOI PDF 
Keywords: Circuit faults, Computational modeling, Delays, Instruction sets, Integrated circuit modeling, Logic gates, Fault simulation, graphics processing unit (GPU), parallel, process variation, small gate delay faults, timing-accurate, waveform
Abstract: Delay fault simulation is an essential task during test pattern generation and reliability assessment of electronic circuits. With the high sensitivity of current nano-scale designs towards even smallest delay deviations, the simulation of small gate delay faults has become extremely important. Since these faults have a subtle impact on the timing behavior, traditional fault simulation approaches based on abstract timing models are not sufficient. Furthermore, the detection of these faults is compromised by the ubiquitous variations in the manufacturing processes, which causes the actual fault coverage to vary from circuit instance to circuit instance, and makes the use of timing accurate methods mandatory. However, the application of timing accurate techniques quickly becomes infeasible for larger designs due to excessive computational requirements. In this work, we present a method for fast and waveformaccurate simulation of small delay faults on graphics processing units with exceptional computational performance. By exploiting multiple dimensions of parallelism from gates, faults, waveforms and circuit instances, the proposed approach allows for timing-accurate and exhaustive small delay fault simulation under process variation for designs with millions of gates.
BibTeX:
@article{SchneKHWW2016,
  author = {Schneider, Eric and Kochte, Michael A. and Holst, Stefan and Wen, Xiaoqing and Wunderlich, Hans-Joachim},
  title = {{GPU-Accelerated Simulation of Small Delay Faults}},
  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)},
  year = {2017},
  volume = {36},
  number = {5},
  pages = {829--841},
  keywords = {Circuit faults, Computational modeling, Delays, Instruction sets, Integrated circuit modeling, Logic gates, Fault simulation, graphics processing unit (GPU), parallel, process variation, small gate delay faults, timing-accurate, waveform},
  abstract = {Delay fault simulation is an essential task during test pattern generation and reliability assessment of electronic circuits. With the high sensitivity of current nano-scale designs towards even smallest delay deviations, the simulation of small gate delay faults has become extremely important. Since these faults have a subtle impact on the timing behavior, traditional fault simulation approaches based on abstract timing models are not sufficient. Furthermore, the detection of these faults is compromised by the ubiquitous variations in the manufacturing processes, which causes the actual fault coverage to vary from circuit instance to circuit instance, and makes the use of timing accurate methods mandatory. However, the application of timing accurate techniques quickly becomes infeasible for larger designs due to excessive computational requirements. In this work, we present a method for fast and waveformaccurate simulation of small delay faults on graphics processing units with exceptional computational performance. By exploiting multiple dimensions of parallelism from gates, faults, waveforms and circuit instances, the proposed approach allows for timing-accurate and exhaustive small delay fault simulation under process variation for designs with millions of gates.},
  doi = {http://dx.doi.org/10.1109/TCAD.2016.2598560},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2016/TCAD_SchneKHWW2016.pdf}
}
59. Aging Monitor Reuse for Small Delay Fault Testing
Liu, C., Kochte, M.A. and Wunderlich, H.-J.
Proceedings of the 35th VLSI Test Symposium (VTS'17), Caesars Palace, Las Vegas, Nevada, USA, 9-12 April 2017
2017
DOI PDF 
Keywords: Delay monitoring, delay test, faster-than-at-speed test, stability checker, small delay fault, ATPG
Abstract: Small delay faults receive more and more attention, since they may indicate a circuit reliability marginality even if they do not violate the timing at the time of production. At-speed test and faster-than-at-speed test (FAST) are rather expensive tasks to test for such faults. The paper at hand avoids complex on-chip structures or expensive high-speed ATE for test response evaluation, if aging monitors which are integrated into the device under test anyway are reused. The main challenge in reusing aging monitors for FAST consists in possible false alerts at higher frequencies. While a certain test vector pair makes a delay fault observable at one monitor, it may also exceed the time slack in the fault free case at a different monitor which has to be masked. Therefore, a multidimensional optimizing problem has to be solved for minimizing the masking overhead and the number of test vectors while maximizing delay fault coverage.
BibTeX:
@inproceedings{LiuKW2017,
  author = {Liu, Chang and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Aging Monitor Reuse for Small Delay Fault Testing}},
  booktitle = {Proceedings of the 35th VLSI Test Symposium (VTS'17)},
  year = {2017},
  keywords = {Delay monitoring, delay test, faster-than-at-speed test, stability checker, small delay fault, ATPG},
  abstract = {Small delay faults receive more and more attention, since they may indicate a circuit reliability marginality even if they do not violate the timing at the time of production. At-speed test and faster-than-at-speed test (FAST) are rather expensive tasks to test for such faults. The paper at hand avoids complex on-chip structures or expensive high-speed ATE for test response evaluation, if aging monitors which are integrated into the device under test anyway are reused. The main challenge in reusing aging monitors for FAST consists in possible false alerts at higher frequencies. While a certain test vector pair makes a delay fault observable at one monitor, it may also exceed the time slack in the fault free case at a different monitor which has to be masked. Therefore, a multidimensional optimizing problem has to be solved for minimizing the masking overhead and the number of test vectors while maximizing delay fault coverage.},
  doi = {http://dx.doi.org/10.1109/VTS.2017.7928921},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2017/VTS_LiuKW2017.pdf}
}
58. Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test
Holst, S., Schneider, E., Wen, X., Kajihara, S., Yamato, Y., Wunderlich, H.-J. and Kochte, M.A.
Proceedings of the 25th IEEE Asian Test Symposium (ATS'16), Hiroshima, Japan, 21-24 November 2016, pp. 19-24
2016
DOI PDF 
Abstract: IR-drop induced false capture failures and test clock stretch are severe problems in at-speed scan testing. We propose a new method to efficiently and accurately identify these problems. For the first time, our approach considers the additional dynamic power caused by glitches, the spatial and temporal distribution of all toggles, and their impact on both logic paths and the clock tree without time-consuming electrical simulations.
BibTeX:
@inproceedings{HolstSWKYWK2016,
  author = {Holst, Stefan and Schneider, Eric and Wen, Xiaoqing and Kajihara, Seiji and Yamato, Yuta and Wunderlich, Hans-Joachim and Kochte, Michael A.},
  title = {{Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test}},
  booktitle = {Proceedings of the 25th IEEE Asian Test Symposium (ATS'16)},
  year = {2016},
  pages = {19--24},
  abstract = {IR-drop induced false capture failures and test clock stretch are severe problems in at-speed scan testing. We propose a new method to efficiently and accurately identify these problems. For the first time, our approach considers the additional dynamic power caused by glitches, the spatial and temporal distribution of all toggles, and their impact on both logic paths and the clock tree without time-consuming electrical simulations.},
  doi = {http://dx.doi.org/10.1109/ATS.2016.49},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2016/ATS_HolstSWKYWK2016.pdf}
}
57. Test Strategies for Reconfigurable Scan Networks
Kochte, M.A., Baranowski, R., Schaal, M. and Wunderlich, H.-J.
Proceedings of the 25th IEEE Asian Test Symposium (ATS'16), Hiroshima, Japan, 21-24 November 2016, pp. 113-118
2016
DOI PDF 
Keywords: Test generation, reconfigurable scan network, design-for-test, on-chip infrastructure, IEEE Std 1687, iJTAG
Abstract: On-chip infrastructure is an essential part of today’s complex designs and enables their cost-efficient manufacturing and operation. The diversity and high number of infrastructure elements demands flexible and low-latency access mechanisms, such as reconfigurable scan networks (RSNs). The correct operation of the infrastructure access itself is highly important for the test of the system logic, its diagnosis, debug and bring-up, as well as post-silicon validation. Ensuring correct operation requires the thorough testing of the RSN. Because of sequential and combinational dependencies in RSN accesses, test generation for general RSNs is computationally very difficult and requires dedicated test strategies. This paper explores different test strategies for general RSNs and discusses the achieved structural fault coverage. Experimental results show that the combination of functional test heuristics together with a dedicated RSN test pattern generation approach significantly outperforms the test quality of a standard ATPG tool.
BibTeX:
@inproceedings{KochtBSW2016,
  author = {Kochte, Michael A. and Baranowski, Rafal and Schaal, Marcel and Wunderlich, Hans-Joachim},
  title = {{Test Strategies for Reconfigurable Scan Networks}},
  booktitle = {Proceedings of the 25th IEEE Asian Test Symposium (ATS'16)},
  year = {2016},
  pages = {113--118},
  keywords = {Test generation, reconfigurable scan network, design-for-test, on-chip infrastructure, IEEE Std 1687, iJTAG},
  abstract = {On-chip infrastructure is an essential part of today’s complex designs and enables their cost-efficient manufacturing and operation. The diversity and high number of infrastructure elements demands flexible and low-latency access mechanisms, such as reconfigurable scan networks (RSNs). The correct operation of the infrastructure access itself is highly important for the test of the system logic, its diagnosis, debug and bring-up, as well as post-silicon validation. Ensuring correct operation requires the thorough testing of the RSN. Because of sequential and combinational dependencies in RSN accesses, test generation for general RSNs is computationally very difficult and requires dedicated test strategies. This paper explores different test strategies for general RSNs and discusses the achieved structural fault coverage. Experimental results show that the combination of functional test heuristics together with a dedicated RSN test pattern generation approach significantly outperforms the test quality of a standard ATPG tool.},
  doi = {http://dx.doi.org/10.1109/ATS.2016.35},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2016/ATS_KochtBSW2016.pdf}
}
56. Autonomous Testing for 3D-ICs with IEEE Std. 1687
Ye, J.-C., Kochte, M.A., Lee, K.-J. and Wunderlich, H.-J.
Proceedings of the 25th IEEE Asian Test Symposium (ATS'16), Hiroshima, Japan, 21-24 November 2016, pp. 215-220
2016
DOI PDF 
Keywords: IEEE Std. 1687, IJTAG, reconfigurable scan network, autonomous testing, 3D-ICs, DFT
Abstract: IEEE Std. 1687, or IJTAG, defines flexible serial scan-based architectures for accessing embedded instruments efficiently. In this paper, we present a novel test architecture that employs IEEE Std. 1687 together with an efficient test controller to carry out 3D-IC testing autonomously. The test controller can deliver parallel test data for the IEEE Std. 1687 structures and the cores under test, and provide required control signals to control the whole test procedure. This design can achieve at-speed, autonomous and programmable testing in 3D-ICs. Experimental results show that the additional area and test cycle overhead of this architecture is small considering its autonomous test capability.
BibTeX:
@inproceedings{YeKLW2016,
  author = {Ye, Jin-Cun and Kochte, Michael A. and Lee, Kuen-Jong and Wunderlich, Hans-Joachim},
  title = {{Autonomous Testing for 3D-ICs with IEEE Std. 1687}},
  booktitle = {Proceedings of the 25th IEEE Asian Test Symposium (ATS'16)},
  year = {2016},
  pages = {215--220},
  keywords = {IEEE Std. 1687, IJTAG, reconfigurable scan network, autonomous testing, 3D-ICs, DFT},
  abstract = {IEEE Std. 1687, or IJTAG, defines flexible serial scan-based architectures for accessing embedded instruments efficiently. In this paper, we present a novel test architecture that employs IEEE Std. 1687 together with an efficient test controller to carry out 3D-IC testing autonomously. The test controller can deliver parallel test data for the IEEE Std. 1687 structures and the cores under test, and provide required control signals to control the whole test procedure. This design can achieve at-speed, autonomous and programmable testing in 3D-ICs. Experimental results show that the additional area and test cycle overhead of this architecture is small considering its autonomous test capability.},
  doi = {http://dx.doi.org/10.1109/ATS.2016.56},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2016/ATS_YeKLW2016.pdf}
}
55. Efficient Algorithm-Based Fault Tolerance for Sparse Matrix Operations
Schöll, A., Braun, C., Kochte, M.A. and Wunderlich, H.-J.
Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'16), Toulouse, France, 28 June-1 July 2016, pp. 251-262
2016
DOI PDF 
Keywords: Fault Tolerance, Sparse Linear Algebra, ABFT, Online Error Localization
Abstract: We propose a fault tolerance approach for sparse matrix operations that detects and implicitly locates errors in the results for efficient local correction. This approach reduces the runtime overhead for fault tolerance and provides high error coverage. Existing algorithm-based fault tolerance approaches for sparse matrix operations detect and correct errors, but they often rely on expensive error localization steps. General checkpointing schemes can induce large recovery cost for high error rates. For sparse matrix-vector multiplications, experimental results show an average reduction in runtime overhead of 43.8%, while the error coverage is on average improved by 52.2% compared to related work. The practical applicability is demonstrated in a case study using the iterative Preconditioned Conjugate Gradient solver. When scaling the error rate by four orders of magnitude, the average runtime overhead increases only by 31.3% compared to low error rates.
BibTeX:
@inproceedings{SchoeBKW2016,
  author = {Schöll, Alexander and Braun, Claus and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Efficient Algorithm-Based Fault Tolerance for Sparse Matrix Operations}},
  booktitle = {Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'16)},
  year = {2016},
  pages = {251--262},
  keywords = {Fault Tolerance, Sparse Linear Algebra, ABFT, Online Error Localization},
  abstract = {We propose a fault tolerance approach for sparse matrix operations that detects and implicitly locates errors in the results for efficient local correction. This approach reduces the runtime overhead for fault tolerance and provides high error coverage. Existing algorithm-based fault tolerance approaches for sparse matrix operations detect and correct errors, but they often rely on expensive error localization steps. General checkpointing schemes can induce large recovery cost for high error rates. For sparse matrix-vector multiplications, experimental results show an average reduction in runtime overhead of 43.8%, while the error coverage is on average improved by 52.2% compared to related work. The practical applicability is demonstrated in a case study using the iterative Preconditioned Conjugate Gradient solver. When scaling the error rate by four orders of magnitude, the average runtime overhead increases only by 31.3% compared to low error rates.},
  doi = {http://dx.doi.org/10.1109/DSN.2016.31},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2016/DSN_SchoeBKW2016.pdf}
}
54. Formal Verification of Secure Reconfigurable Scan Network Infrastructure
Kochte, M.A., Baranowski, R., Sauer, M., Becker, B. and Wunderlich, H.-J.
Proceedings of the 21st IEEE European Test Symposium (ETS'16), Amsterdam, The Netherlands, 23-27 May 2016 , pp. 1-6
2016
DOI PDF 
Keywords: Security, Formal verification, IEEE Std 1687, IJTAG, Reconfigurable scan network, Infrastructure, Sidechannel attack
Abstract: Reconfigurable scan networks (RSN) as standardized by IEEE Std 1687 allow flexible and efficient access to on-chip infrastructure for test and diagnosis, post-silicon validation, debug, bring-up, or maintenance in the field. However, unauthorized access or manipulation of the attached instruments, monitors, or controllers pose security and safety risks. Different RSN architectures have recently been proposed to implement secure access to the connected instruments, for instance by authentication and authorization. To ensure that the implemented security schemes cannot be bypassed, design verification of the security properties is mandatory. However, combinational and deep sequential dependencies of modern RSNs and their extensions for security require novel approaches to formal verification for unbounded model checking. This work presents for the first time a formal design verification methodology for security properties of RSNs based on unbounded model checking that is able to verify access protection at logical level. Experimental results demonstrate that state-of-the-art security schemes for RSNs can be efficiently handled, even for very large designs.
BibTeX:
@inproceedings{KochtBSBW2016,
  author = {Kochte, Michael A. and Baranowski, Rafal and Sauer, Matthias and Becker, Bernd and Wunderlich, Hans-Joachim },
  title = {{Formal Verification of Secure Reconfigurable Scan Network Infrastructure}},
  booktitle = {Proceedings of the 21st IEEE European Test Symposium (ETS'16)},
  year = { 2016 },
  pages = {1-6},
  keywords = {Security, Formal verification, IEEE Std 1687, IJTAG, Reconfigurable scan network, Infrastructure, Sidechannel attack},
  abstract = {Reconfigurable scan networks (RSN) as standardized by IEEE Std 1687 allow flexible and efficient access to on-chip infrastructure for test and diagnosis, post-silicon validation, debug, bring-up, or maintenance in the field. However, unauthorized access or manipulation of the attached instruments, monitors, or controllers pose security and safety risks. Different RSN architectures have recently been proposed to implement secure access to the connected instruments, for instance by authentication and authorization. To ensure that the implemented security schemes cannot be bypassed, design verification of the security properties is mandatory. However, combinational and deep sequential dependencies of modern RSNs and their extensions for security require novel approaches to formal verification for unbounded model checking. This work presents for the first time a formal design verification methodology for security properties of RSNs based on unbounded model checking that is able to verify access protection at logical level. Experimental results demonstrate that state-of-the-art security schemes for RSNs can be efficiently handled, even for very large designs.},
  doi = {http://dx.doi.org/10.1109/ETS.2016.7519290},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2016/ETS_KochtBSBW2016.pdf}
}
53. SHIVA: Sichere Hardware in der Informationsverarbeitung
Kochte, M.A., Sauer, M., Raiola, P., Becker, B. and Wunderlich, H.-J.
Proceedings of the ITG/GI/GMM edaWorkshop 2016, Hannover, Germany, 11-12 May 2016
2016
URL PDF 
Abstract: Das Projekt ”SHIVA: Sichere Hardware in der Informationsverarbeitung“ ist Teil des Forschungsprogramms ”IKTSicherheit für weltweit vernetzte vertrauenswürdige Infrastrukturen“ der Baden-Württemberg Stiftung. Ziel des Projekts sind die Erforschung von Entwurfs- und Verifikationsmethoden zur Steigerung der Sicherheit mikroelektronischer Hardware, beispielsweise aus der Automobilelektronik, der Medizintechnik oder auch der Fertigungstechnik. Es soll damit die missbräuchliche Verwendung nicht-funktionaler Hardware-Infrastruktur zur Beobachtung interner sensibler Daten, verwendeter Verfahren und Prozesse sowie zu Angriffen auf das geistige Eigentum an der Hardware ausgeschlossen werden. Das Projekt ist eine Kooperation des Instituts für Technische Informatik (ITI) der Universität Stuttgart und des Lehrstuhls für Rechnerarchitektur der Universität Freiburg. Dieser Beitrag stellt die Projektziele und erste Forschungsergebnisse vor.
BibTeX:
@inproceedings{KochtSRBW2016,
  author = {Kochte, Michael A. and Sauer, Matthias and Raiola, Pascal and Becker, Bernd and Wunderlich, Hans-Joachim},
  title = {{SHIVA: Sichere Hardware in der Informationsverarbeitung}},
  booktitle = {Proceedings of the ITG/GI/GMM edaWorkshop 2016},
  year = {2016},
  abstract = {Das Projekt ”SHIVA: Sichere Hardware in der Informationsverarbeitung“ ist Teil des Forschungsprogramms ”IKTSicherheit für weltweit vernetzte vertrauenswürdige Infrastrukturen“ der Baden-Württemberg Stiftung. Ziel des Projekts sind die Erforschung von Entwurfs- und Verifikationsmethoden zur Steigerung der Sicherheit mikroelektronischer Hardware, beispielsweise aus der Automobilelektronik, der Medizintechnik oder auch der Fertigungstechnik. Es soll damit die missbräuchliche Verwendung nicht-funktionaler Hardware-Infrastruktur zur Beobachtung interner sensibler Daten, verwendeter Verfahren und Prozesse sowie zu Angriffen auf das geistige Eigentum an der Hardware ausgeschlossen werden. Das Projekt ist eine Kooperation des Instituts für Technische Informatik (ITI) der Universität Stuttgart und des Lehrstuhls für Rechnerarchitektur der Universität Freiburg. Dieser Beitrag stellt die Projektziele und erste Forschungsergebnisse vor.},
  url = {http://www.book-on-demand.de/shop/14818},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2016/EDA_KochtSRBW2016.pdf}
}
52. Dependable On-Chip Infrastructure for Dependable MPSOCs
Kochte, M.A. and Wunderlich, H.-J.
Proceedings of the 17th IEEE Latin American Test Symposium (LATS'16), Foz do Iguaçu, Brazil, 6-8 April 2016 , pp. 183-188
2016
DOI PDF 
Keywords: Dependability, on-chip infrastructure, reconfigurable scan network, IEEE Std 1687, iJTAG, hardware security
Abstract: Today's MPSOCs employ complex on-chip infrastructure and instrumentation for efficient test, debug, diagnosis, and post-silicon validation, reliability management and maintenance in the field, or monitoring and calibration during operation. To enable flexible and efficient access to such instrumentation, reconfigurable scan networks (RSNs) as recently standardized by IEEE Std 1687 can be used. Given the importance of infrastructure for the dependability of the whole MPSOC, however, the RSN itself must be highly dependable. This paper addresses dependability issues of RSNs including verification, test, and security, and their importance for dependable MPSOCs. First research results are summarized, and open questions for future work are highlighted.
BibTeX:
@inproceedings{KochtW2016,
  author = {Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Dependable On-Chip Infrastructure for Dependable MPSOCs}},
  booktitle = {Proceedings of the 17th IEEE Latin American Test Symposium (LATS'16)},
  year = { 2016 },
  pages = {183-188},
  keywords = { Dependability, on-chip infrastructure, reconfigurable scan network, IEEE Std 1687, iJTAG, hardware security },
  abstract = {Today's MPSOCs employ complex on-chip infrastructure and instrumentation for efficient test, debug, diagnosis, and post-silicon validation, reliability management and maintenance in the field, or monitoring and calibration during operation. To enable flexible and efficient access to such instrumentation, reconfigurable scan networks (RSNs) as recently standardized by IEEE Std 1687 can be used. Given the importance of infrastructure for the dependability of the whole MPSOC, however, the RSN itself must be highly dependable. This paper addresses dependability issues of RSNs including verification, test, and security, and their importance for dependable MPSOCs. First research results are summarized, and open questions for future work are highlighted.},
  doi = {http://dx.doi.org/10.1109/LATW.2016.7483366},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2016/LATS_KochtW2016.pdf}
}
51. Mixed 01X-RSL-Encoding for Fast and Accurate ATPG with Unknowns
Erb, D., Scheibler, K., Kochte, M.A., Sauer, M., Wunderlich, H.-J. and Becker, B.
Proceedings of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC'16), Macao SAR, China, 25-28 January 2016 , pp. 749-754
2016
DOI PDF 
Keywords: Unknown values, test generation, Restricted symbolic logic, SAT, Stuck-at fault
Abstract: Unknown (X) values in a design introduce pessimism in conventional test generation algorithms which results in a loss of fault coverage. This pessimism is reduced by a more accurate modeling and analysis. Unfortunately, accurate analysis techniques highly increase runtime and limit scalability. One promising technique to prevent high runtimes while still providing high accuracy is the use of restricted symbolic logic (RSL). However, also pure RSL-based algorithms reach their limits as soon as millon gate circuits need to be processed. In this paper, we propose new ATPG techniques to overcome such limitations. An efficient hybrid encoding combines the accuracy of RSL-based modeling with the compactness of conventional threevalued encoding. A low-cost two-valued SAT-based untestability check is able to classify most untestable faults with low runtime. An incremental and event-based accurate fault simulator is introduced to reduce fault simulation effort. The experiments demonstrate the effectiveness of the proposed techniques. Over 97% of the faults are accurately classified. Both the number of aborts and the total runtime are significantly reduced compared to the state-of-the-art pure RSL-based algorithm. For circuits up to a million gates, the fault coverage could be increased considerably compared to a state-of-the-art commercial tool with very competitive runtimes.
BibTeX:
@inproceedings{ErbSKSWB2016,
  author = {Erb, Dominik and Scheibler, Karsten and Kochte, Michael A. and Sauer, Matthias and Wunderlich, Hans-Joachim and Becker, Bernd},
  title = {{Mixed 01X-RSL-Encoding for Fast and Accurate ATPG with Unknowns}},
  booktitle = {Proceedings of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC'16)},
  year = { 2016 },
  pages = {749-754},
  keywords = {Unknown values, test generation, Restricted symbolic logic, SAT, Stuck-at fault},
  abstract = {Unknown (X) values in a design introduce pessimism in conventional test generation algorithms which results in a loss of fault coverage. This pessimism is reduced by a more accurate modeling and analysis. Unfortunately, accurate analysis techniques highly increase runtime and limit scalability. One promising technique to prevent high runtimes while still providing high accuracy is the use of restricted symbolic logic (RSL). However, also pure RSL-based algorithms reach their limits as soon as millon gate circuits need to be processed. In this paper, we propose new ATPG techniques to overcome such limitations. An efficient hybrid encoding combines the accuracy of RSL-based modeling with the compactness of conventional threevalued encoding. A low-cost two-valued SAT-based untestability check is able to classify most untestable faults with low runtime. An incremental and event-based accurate fault simulator is introduced to reduce fault simulation effort. The experiments demonstrate the effectiveness of the proposed techniques. Over 97% of the faults are accurately classified. Both the number of aborts and the total runtime are significantly reduced compared to the state-of-the-art pure RSL-based algorithm. For circuits up to a million gates, the fault coverage could be increased considerably compared to a state-of-the-art commercial tool with very competitive runtimes.},
  doi = {http://dx.doi.org/10.1109/ASPDAC.2016.7428101},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2016/ASPDAC_ErbSKSWB2016.pdf}
}
50. Accurate QBF-based Test Pattern Generation in Presence of Unknown Values
Erb, D., Kochte, M.A., Reimer, S., Sauer, M., Wunderlich, H.-J. and Becker, B.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
Vol. 34(12), December 2015, pp. 2025-2038
2015
DOI PDF 
Keywords: Unknown values, X-values, ATPG, QBF, SAT, stuck-at fault, transition-delay fault
Abstract: Unknown (X) values emerge during the design process as well as during system operation and test application. X-sources are for instance black boxes in design models, clockdomain boundaries, analog-to-digital converters, or uncontrolled or uninitialized sequential elements. To compute a test pattern for a given fault, well-defined logic values are required both for fault activation and propagation to observing outputs. In presence of X-values, conventional test generation algorithms, based on structural algorithms, Boolean satisfiability (SAT), or BDD-based reasoning may fail to generate test patterns or to prove faults untestable. This work proposes the first efficient stuck-at and transitiondelay fault test generation algorithm able to prove testability or untestability of faults in presence of X-values. It overcomes the principal pessimism of conventional algorithms when X-values are considered by mapping the test generation problem to the satisfiability of Quantified Boolean Formulae (QBF). Experiments on ISCAS benchmarks and larger industrial circuits investigate the increase in fault coverage for conventional deterministic and potential detection requirements for both randomized and clustered X-sources.
BibTeX:
@article{ErbKRSWB2015,
  author = {Erb, Dominik and Kochte, Michael A. and Reimer, Sven and Sauer, Matthias and Wunderlich, Hans-Joachim and Becker, Bernd},
  title = {{Accurate QBF-based Test Pattern Generation in Presence of Unknown Values}},
  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)},
  year = {2015},
  volume = {34},
  number = {12},
  pages = {2025--2038},
  keywords = {Unknown values, X-values, ATPG, QBF, SAT, stuck-at fault, transition-delay fault},
  abstract = { Unknown (X) values emerge during the design process as well as during system operation and test application. X-sources are for instance black boxes in design models, clockdomain boundaries, analog-to-digital converters, or uncontrolled or uninitialized sequential elements. To compute a test pattern for a given fault, well-defined logic values are required both for fault activation and propagation to observing outputs. In presence of X-values, conventional test generation algorithms, based on structural algorithms, Boolean satisfiability (SAT), or BDD-based reasoning may fail to generate test patterns or to prove faults untestable. This work proposes the first efficient stuck-at and transitiondelay fault test generation algorithm able to prove testability or untestability of faults in presence of X-values. It overcomes the principal pessimism of conventional algorithms when X-values are considered by mapping the test generation problem to the satisfiability of Quantified Boolean Formulae (QBF). Experiments on ISCAS benchmarks and larger industrial circuits investigate the increase in fault coverage for conventional deterministic and potential detection requirements for both randomized and clustered X-sources.},
  doi = {http://dx.doi.org/10.1109/TCAD.2015.2440315},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/TCAD_ErbKRSWB2015.pdf}
}
49. Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch
Asada, K., Wen, X., Holst, S., Miyase, K., Kajihara, S., Kochte, M.A., Schneider, E., Wunderlich, H.-J. and Qian, J.
Proceedings of the 24th IEEE Asian Test Symposium (ATS'15), Mumbai, India, 22-25 November 2015, pp. 103-108
ATS 2015 Best Paper Award
2015
DOI PDF 
Keywords: launch switching activity, IR-drop, logic path, clock path, false capture failure, test clock stretch, X-filling
Abstract: IR-drop induced by launch switching activity (LSA) in capture mode during at-speed scan testing increases delay along not only logic paths (LPs) but also clock paths (CPs). Excessive extra delay along LPs compromises test yields due to false capture failures, while excessive extra delay along CPs compromises test quality due to test clock stretch. This paper is the first to mitigate the impact of LSA on both LPs and CPs with a novel LCPA (Logic/Clock-Path-Aware) at-speed scan test generation scheme, featuring (1) a new metric for assessing the risk of false capture failures based on the amount of LSA around both LPs and CPs, (2) a procedure for avoiding false capture failures by reducing LSA around LPs or masking uncertain test responses, and (3) a procedure for reducing test clock stretch by reducing LSA around CPs. Experimental results demonstrate the effectiveness of the LCPA scheme in improving test yields and test quality.
BibTeX:
@inproceedings{AsadaWHMKKSWQ2015,
  author = {Asada, Koji and Wen, Xiaoqing and Holst, Stefan and Miyase, Kohei and Kajihara, Seiji and Kochte, Michael A. and Schneider, Eric and Wunderlich, Hans-Joachim and Qian, Jun},
  title = {{Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch}},
  booktitle = {Proceedings of the 24th IEEE Asian Test Symposium (ATS'15)},
  year = {2015},
  pages = {103-108},
  keywords = { launch switching activity, IR-drop, logic path, clock path, false capture failure, test clock stretch, X-filling },
  abstract = {IR-drop induced by launch switching activity (LSA) in capture mode during at-speed scan testing increases delay along not only logic paths (LPs) but also clock paths (CPs). Excessive extra delay along LPs compromises test yields due to false capture failures, while excessive extra delay along CPs compromises test quality due to test clock stretch. This paper is the first to mitigate the impact of LSA on both LPs and CPs with a novel LCPA (Logic/Clock-Path-Aware) at-speed scan test generation scheme, featuring (1) a new metric for assessing the risk of false capture failures based on the amount of LSA around both LPs and CPs, (2) a procedure for avoiding false capture failures by reducing LSA around LPs or masking uncertain test responses, and (3) a procedure for reducing test clock stretch by reducing LSA around CPs. Experimental results demonstrate the effectiveness of the LCPA scheme in improving test yields and test quality.},
  doi = {http://dx.doi.org/10.1109/ATS.2015.25},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/ATS_AsadaWHMKKSWQ2015.pdf}
}
48. Optimized Selection of Frequencies for Faster-Than-at-Speed Test
Kampmann, M., Kochte, M.A., Schneider, E., Indlekofer, T., Hellebrand, S. and Wunderlich, H.-J.
Proceedings of the 24th IEEE Asian Test Symposium (ATS'15), Mumbai, India, 22-25 November 2015, pp. 109-114
2015
DOI PDF 
Keywords: BIST, small delay defects, delay test, faster-than-at-speed-test
Abstract: Small gate delay faults (SDFs) are not detectable at-speed, if they can only be propagated along short paths. These hidden delay faults (HDFs) do not influence the circuit’s behavior initially, but they may indicate design marginalities leading to early-life failures, and therefore they cannot be neglected. HDFs can be detected by faster-than-at-speed test (FAST), where typically several different frequencies are used to maximize the coverage. A given set of test patterns P potentially detects a HDF if it contains a test pattern sensitizing a path through the fault site, and the efficiency of FAST can be measured as the ratio of actually detected HDFs to potentially detected HDFs. The paper at hand targets maximum test efficiency with a minimum number of frequencies. The procedure starts with a test set for transition delay faults and a set of preselected equidistant frequencies. Timing-accurate simulation of this initial setup identifies the hard-to-detect faults, which are then targeted by a more complex timing-aware ATPG procedure. For the yet undetected HDFs, a minimum number of frequencies are determined using an efficient hypergraph algorithm. Experimental results show that with this approach, the number of test frequencies required for maximum test efficiency can be reduced considerably. Furthermore, test set inflation is limited as timing-aware ATPG is only used for a small subset of HDFs.
BibTeX:
@inproceedings{KampmKSIHW2015,
  author = {Kampmann, Matthias and Kochte, Michael A. and Schneider, Eric and Indlekofer, Thomas and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
  title = {{Optimized Selection of Frequencies for Faster-Than-at-Speed Test}},
  booktitle = {Proceedings of the 24th IEEE Asian Test Symposium (ATS'15)},
  year = {2015},
  pages = {109-114},
  keywords = {BIST, small delay defects, delay test, faster-than-at-speed-test},
  abstract = {Small gate delay faults (SDFs) are not detectable at-speed, if they can only be propagated along short paths. These hidden delay faults (HDFs) do not influence the circuit’s behavior initially, but they may indicate design marginalities leading to early-life failures, and therefore they cannot be neglected. HDFs can be detected by faster-than-at-speed test (FAST), where typically several different frequencies are used to maximize the coverage. A given set of test patterns P potentially detects a HDF if it contains a test pattern sensitizing a path through the fault site, and the efficiency of FAST can be measured as the ratio of actually detected HDFs to potentially detected HDFs. The paper at hand targets maximum test efficiency with a minimum number of frequencies. The procedure starts with a test set for transition delay faults and a set of preselected equidistant frequencies. Timing-accurate simulation of this initial setup identifies the hard-to-detect faults, which are then targeted by a more complex timing-aware ATPG procedure. For the yet undetected HDFs, a minimum number of frequencies are determined using an efficient hypergraph algorithm. Experimental results show that with this approach, the number of test frequencies required for maximum test efficiency can be reduced considerably. Furthermore, test set inflation is limited as timing-aware ATPG is only used for a small subset of HDFs.},
  doi = {http://dx.doi.org/10.1109/ATS.2015.26},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/ATS_KampmKSIHW2015.pdf}
}
47. Intermittent and Transient Fault Diagnosis on Sparse Code Signatures
Kochte, M., Dalirsani, A., Bernabei, A., Omana, M., Metra, C. and Wunderlich, H.-J.
Proceedings of the 24th IEEE Asian Test Symposium (ATS'15), Mumbai, India, 22-25 November 2015, pp. 157-162
2015
DOI PDF 
Keywords: Diagnosis, intermittent, transient, concurrent error detection, code signature, self-checking, online testing
Abstract: Failure diagnosis of field returns typically requires high quality test stimuli and assumes that tests can be repeated. For intermittent faults with fault activation conditions depending on the physical environment, the repetition of tests cannot ensure that the behavior in the field is also observed during diagnosis, causing field returns diagnosed as no-trouble-found. In safety critical applications, self-checking circuits, which provide concurrent error detection, are frequently used. To diagnose intermittent and transient faulty behavior in such circuits, we use the stored encoded circuit outputs in case of a failure (called signatures) for later analysis in diagnosis. For the first time, a diagnosis algorithm is presented that is capable of performing the classification of intermittent or transient faults using only the very limited amount of functional stimuli and signatures observed during operation and stored on chip. The experimental results demonstrate that even with these harsh limitations it is possible to distinguish intermittent from transient faulty behavior. This is essential to determine whether a circuit in which failures have been observed should be subject to later physical failure analysis, since intermittent faulty behavior has been diagnosed. In case of transient faulty behavior, it may still be operated reliably.
BibTeX:
@inproceedings{KochtDBOMW2015,
  author = {Kochte, Michael and Dalirsani, Atefe and Bernabei, Andrea and Omana, Martin and Metra, Cecilia and Wunderlich, Hans-Joachim},
  title = {{Intermittent and Transient Fault Diagnosis on Sparse Code Signatures}},
  booktitle = {Proceedings of the 24th IEEE Asian Test Symposium (ATS'15)},
  year = {2015},
  pages = {157-162},
  keywords = { Diagnosis, intermittent, transient, concurrent error detection, code signature, self-checking, online testing },
  abstract = {Failure diagnosis of field returns typically requires high quality test stimuli and assumes that tests can be repeated. For intermittent faults with fault activation conditions depending on the physical environment, the repetition of tests cannot ensure that the behavior in the field is also observed during diagnosis, causing field returns diagnosed as no-trouble-found. In safety critical applications, self-checking circuits, which provide concurrent error detection, are frequently used. To diagnose intermittent and transient faulty behavior in such circuits, we use the stored encoded circuit outputs in case of a failure (called signatures) for later analysis in diagnosis. For the first time, a diagnosis algorithm is presented that is capable of performing the classification of intermittent or transient faults using only the very limited amount of functional stimuli and signatures observed during operation and stored on chip. The experimental results demonstrate that even with these harsh limitations it is possible to distinguish intermittent from transient faulty behavior. This is essential to determine whether a circuit in which failures have been observed should be subject to later physical failure analysis, since intermittent faulty behavior has been diagnosed. In case of transient faulty behavior, it may still be operated reliably.},
  doi = {http://dx.doi.org/10.1109/ATS.2015.34},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/ATS_KochtDBOMW2015.pdf}
}
46. STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures
Zhang, H., Kochte, M.A., Schneider, E., Bauer, L., Wunderlich, H.-J. and Henkel, J.
Proceedings of the 34th IEEE/ACM International Conference on Computer-Aided Design (ICCAD'15), Austin, Texas, USA, 2-6 November 2015, pp. 38-45
2015
URL PDF 
Abstract: Aging effects in nano-scale CMOS circuits impair the reliability and Mean Time to Failure (MTTF) of embedded systems. Especially for FPGAs that are manufactured in the latest technology node, aging is a major concern. We introduce the first cross-layer aging-aware placement method for accelerators in FPGA-based runtime reconfigurable architectures. It optimizes stress distribution by accelerator placement at runtime, i.e. to which reconfigurable region an accelerator shall be reconfigured. Additionally, it optimizes logic placement at synthesis time to diversify the resource usage of individual accelerators, i.e. which CLBs of a reconfigurable region shall be used by an accelerator. Both layers together balance the intra- and inter-region stress induced by the application workload at negligible performance cost. Experimental results show significant reduction of maximum stress of up to 64% and 35%, which leads to up to 177% and 14% MTTF improvement relative to state-of- the-art methods w.r.t. HCI and BTI aging, respectively.
BibTeX:
@inproceedings{ZhangKSBWH2015,
  author = {Zhang, Hongyan and Kochte, Michael A. and Schneider, Eric and Bauer, Lars and Wunderlich, Hans-Joachim and Henkel, Jörg},
  title = {{STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures}},
  booktitle = {Proceedings of the 34th IEEE/ACM International Conference on Computer-Aided Design (ICCAD'15)},
  year = {2015},
  pages = {38-45},
  abstract = {Aging effects in nano-scale CMOS circuits impair the reliability and Mean Time to Failure (MTTF) of embedded systems. Especially for FPGAs that are manufactured in the latest technology node, aging is a major concern. We introduce the first cross-layer aging-aware placement method for accelerators in FPGA-based runtime reconfigurable architectures. It optimizes stress distribution by accelerator placement at runtime, i.e. to which reconfigurable region an accelerator shall be reconfigured. Additionally, it optimizes logic placement at synthesis time to diversify the resource usage of individual accelerators, i.e. which CLBs of a reconfigurable region shall be used by an accelerator. Both layers together balance the intra- and inter-region stress induced by the application workload at negligible performance cost. Experimental results show significant reduction of maximum stress of up to 64% and 35%, which leads to up to 177% and 14% MTTF improvement relative to state-of- the-art methods w.r.t. HCI and BTI aging, respectively.},
  url = { http://dl.acm.org/citation.cfm?id=2840825 },
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/ICCAD_ZhangKSBWH2015.pdf}
}
45. Low-Overhead Fault-Tolerance for the Preconditioned Conjugate Gradient Solver
Schöll, A., Braun, C., Kochte, M.A. and Wunderlich, H.-J.
Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'15), Amherst, Massachusetts, USA, 12-14 October 2015, pp. 60-65
2015
DOI PDF 
Keywords: Fault Tolerance, Sparse Linear System Solving, Preconditioned Conjugate Gradient, ABFT
Abstract: Linear system solvers are an integral part for many different compute-intensive applications and they benefit from the compute power of heterogeneous computer architectures. However, the growing spectrum of reliability threats for such nano-scaled CMOS devices makes the integration of fault tolerance mandatory. The preconditioned conjugate gradient (PCG) method is one widely used solver as it finds solutions typically faster compared to direct methods. Although this iterative approach is able to tolerate certain errors, latest research shows that the PCG solver is still vulnerable to transient effects. Even single errors, for instance, caused by marginal hardware, harsh environments, or particle radiation, can considerably affect execution times, or lead to silent data corruption. In this work, a novel fault-tolerant PCG solver with extremely low runtime overhead is proposed. Since the error detection method does not involve expensive operations, it scales very well with increasing problem sizes. In case of errors, the method selects between three different correction methods according to the identified error. Experimental results show a runtime overhead for error detection ranging only from 0.04% to 1.70%.
BibTeX:
@inproceedings{SchoeBKW2015a,
  author = {Schöll, Alexander and Braun, Claus and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Low-Overhead Fault-Tolerance for the Preconditioned Conjugate Gradient Solver}},
  booktitle = {Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'15)},
  year = {2015},
  pages = {60-65},
  keywords = { Fault Tolerance, Sparse Linear System Solving, Preconditioned Conjugate Gradient, ABFT },
  abstract = {Linear system solvers are an integral part for many different compute-intensive applications and they benefit from the compute power of heterogeneous computer architectures. However, the growing spectrum of reliability threats for such nano-scaled CMOS devices makes the integration of fault tolerance mandatory. The preconditioned conjugate gradient (PCG) method is one widely used solver as it finds solutions typically faster compared to direct methods. Although this iterative approach is able to tolerate certain errors, latest research shows that the PCG solver is still vulnerable to transient effects. Even single errors, for instance, caused by marginal hardware, harsh environments, or particle radiation, can considerably affect execution times, or lead to silent data corruption. In this work, a novel fault-tolerant PCG solver with extremely low runtime overhead is proposed. Since the error detection method does not involve expensive operations, it scales very well with increasing problem sizes. In case of errors, the method selects between three different correction methods according to the identified error. Experimental results show a runtime overhead for error detection ranging only from 0.04% to 1.70%. },
  doi = {http://dx.doi.org/10.1109/DFT.2015.7315136},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/DFTS_SchoeBKW2015.pdf}
}
44. Efficient Observation Point Selection for Aging Monitoring
Liu, C., Kochte, M.A. and Wunderlich, H.-J.
Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS'15), Elia, Halkidiki, Greece, 6-8 July 2015, pp. 176-181
2015
DOI PDF 
Keywords: Aging monitoring, delay monitoring, online test, concurrent test, stability checker, path selection
Abstract: Circuit aging causes a performance degradation and eventually a functional failure. It depends on the workload and the environmental condition of the system, which are hard to predict in early design phases resulting in pessimistic worst case design. Existing delay monitoring schemes measure the remaining slack of paths in the circuit, but cause a significant hardware penalty including global wiring. More importantly, the low sensitization ratio of long paths in applications may lead to a very low measurement frequency or even an unmonitored timing violation. In this work, we propose a delay monitor placement method by analyzing the topological circuit structure and sensitization of paths. The delay monitors are inserted at meticulously selected positions in the circuit, named observation points (OPs). This OP monitor placement method can reduce the number of inserted monitors by up to 98% compared to a placement at the end of long paths. The experimental validation shows the effectiveness of this aging indication, i.e. a monitor issues a timing alert always earlier than any imminent timing failure.
BibTeX:
@inproceedings{LiuKW2015,
  author = {Liu, Chang and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Efficient Observation Point Selection for Aging Monitoring}},
  booktitle = {Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS'15)},
  year = {2015},
  pages = {176--181},
  keywords = {Aging monitoring, delay monitoring, online test, concurrent test, stability checker, path selection},
  abstract = {Circuit aging causes a performance degradation and eventually a functional failure. It depends on the workload and the environmental condition of the system, which are hard to predict in early design phases resulting in pessimistic worst case design. Existing delay monitoring schemes measure the remaining slack of paths in the circuit, but cause a significant hardware penalty including global wiring. More importantly, the low sensitization ratio of long paths in applications may lead to a very low measurement frequency or even an unmonitored timing violation. In this work, we propose a delay monitor placement method by analyzing the topological circuit structure and sensitization of paths. The delay monitors are inserted at meticulously selected positions in the circuit, named observation points (OPs). This OP monitor placement method can reduce the number of inserted monitors by up to 98% compared to a placement at the end of long paths. The experimental validation shows the effectiveness of this aging indication, i.e. a monitor issues a timing alert always earlier than any imminent timing failure.},
  doi = {http://dx.doi.org/10.1109/IOLTS.2015.7229855},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/IOLTS_LiuKW2015.pdf}
}
43. Efficient On-Line Fault-Tolerance for the Preconditioned Conjugate Gradient Method
Schöll, A., Braun, C., Kochte, M.A. and Wunderlich, H.-J.
Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS'15), Elia, Halkidiki, Greece, 6-8 July 2015, pp. 95-100
2015
DOI PDF 
Keywords: Sparse Linear System Solving, Fault Tolerance, Preconditioned Conjugate Gradient, ABFT
Abstract: Linear system solvers are key components of many scientific applications and they can benefit significantly from modern heterogeneous computer architectures. However, such nano-scaled CMOS devices face an increasing number of reliability threats, which make the integration of fault tolerance mandatory. The preconditioned conjugate gradient method (PCG) is a very popular solver since it typically finds solutions faster than direct methods, and it is less vulnerable to transient effects. However, as latest research shows, the vulnerability is still considerable. Even single errors caused, for instance, by marginal hardware, harsh operating conditions or particle radiation can increase execution times considerably or corrupt solutions without indication. In this work, a novel and highly efficient fault-tolerant PCG method is presented. The method applies only two inner products to reliably detect errors. In case of errors, the method automatically selects between roll-back and efficient on-line correction. This significantly reduces the error detection overhead and expensive re-computations.
BibTeX:
@inproceedings{SchoeBKW2015,
  author = {Schöll, Alexander and Braun, Claus and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Efficient On-Line Fault-Tolerance for the Preconditioned Conjugate Gradient Method}},
  booktitle = {Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS'15)},
  year = {2015},
  pages = {95--100},
  keywords = {Sparse Linear System Solving, Fault Tolerance, Preconditioned Conjugate Gradient, ABFT},
  abstract = {Linear system solvers are key components of many scientific applications and they can benefit significantly from modern heterogeneous computer architectures. However, such nano-scaled CMOS devices face an increasing number of reliability threats, which make the integration of fault tolerance mandatory. The preconditioned conjugate gradient method (PCG) is a very popular solver since it typically finds solutions faster than direct methods, and it is less vulnerable to transient effects. However, as latest research shows, the vulnerability is still considerable. Even single errors caused, for instance, by marginal hardware, harsh operating conditions or particle radiation can increase execution times considerably or corrupt solutions without indication. In this work, a novel and highly efficient fault-tolerant PCG method is presented. The method applies only two inner products to reliably detect errors. In case of errors, the method automatically selects between roll-back and efficient on-line correction. This significantly reduces the error detection overhead and expensive re-computations.},
  doi = {http://dx.doi.org/10.1109/IOLTS.2015.7229839},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/IOLTS_SchoeBKW2015.pdf}
}
42. Adaptive Multi-Layer Techniques for Increased System Dependability
Bauer, L., Henkel, J., Herkersdorf, A., Kochte, M.A., Kühn, J.M., Rosenstiel, W., Schweizer, T., Wallentowitz, S., Wenzel, V., Wild, T., Wunderlich, H.-J. and Zhang, H.
it - Information Technology
Vol. 57(3), 8 June 2015, pp. 149-158
2015
DOI PDF 
Keywords: Dependability, fault tolerance, graceful degradation, aging mitigation, online test and error detection, thermal management, multi-core architecture, reconfigurable architecture
Abstract: Achieving system-level dependability is a demanding task. The manifold requirements and dependability threats can no longer be statically addressed at individual abstraction layers. Instead, all components of future multi-processor systems-on-chip (MPSoCs) have to contribute to this common goal in an adaptive manner.
In this paper we target a generic heterogeneous MPSoC that combines general purpose processors along with dedicated application-specific hard-wired accelerators, fine-grained reconfigurable processors, and coarse-grained reconfigurable architectures. We present different reactive and proactive measures at the layers of the runtime system (online resource management), system architecture (global communication), micro architecture (individual tiles), and gate netlist (tile-internal circuits) to address dependability threats.
BibTeX:
@article{BauerHHKKRSWWWWZ2015,
  author = {Bauer, Lars and Henkel, Jörg and Herkersdorf, Andreas and Kochte, Michael A. and Kühn, Johannes M. and Rosenstiel, Wolfgang and Schweizer, Thomas and Wallentowitz, Stefan and Wenzel, Volker and Wild, Thomas and Wunderlich, Hans-Joachim and Zhang, Hongyan},
  title = {{Adaptive Multi-Layer Techniques for Increased System Dependability}},
  journal = {it - Information Technology},
  year = {2015},
  volume = {57},
  number = {3},
  pages = {149--158},
  keywords = {Dependability, fault tolerance, graceful degradation, aging mitigation, online test and error detection, thermal management, multi-core architecture, reconfigurable architecture},
  abstract = {Achieving system-level dependability is a demanding task. The manifold requirements and dependability threats can no longer be statically addressed at individual abstraction layers. Instead, all components of future multi-processor systems-on-chip (MPSoCs) have to contribute to this common goal in an adaptive manner.
In this paper we target a generic heterogeneous MPSoC that combines general purpose processors along with dedicated application-specific hard-wired accelerators, fine-grained reconfigurable processors, and coarse-grained reconfigurable architectures. We present different reactive and proactive measures at the layers of the runtime system (online resource management), system architecture (global communication), micro architecture (individual tiles), and gate netlist (tile-internal circuits) to address dependability threats.}, doi = {http://dx.doi.org/10.1515/itit-2014-1082}, file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/ITIT_BauerHHKKRSWWWWZ2015.pdf} }
41. Fine-Grained Access Management in Reconfigurable Scan Networks
Baranowski, R., Kochte, M.A. and Wunderlich, H.-J.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
Vol. 34(6), June 2015, pp. 937-946
2015
DOI PDF 
Keywords: Debug and diagnosis, reconfigurable scan network, IJTAG, IEEE Std 1687, secure DFT, hardware security, instrument protection
Abstract: Modern VLSI designs incorporate a high amount of instrumentation that supports post-silicon validation and debug, volume test and diagnosis, as well as in-field system monitoring and maintenance. Reconfigurable scan architectures, as allowed by the novel IEEE Std 1149.1-2013 (JTAG) and IEEE Std 1687- 2014 (IJTAG), emerge as a scalable mechanism for access to such on-chip instruments. While the on-chip instrumentation is crucial for meeting quality, dependability, and time-to-market goals, it is prone to abuse and threatens system safety and security. A secure access management method is mandatory to assure that critical instruments be accessible to authorized entities only. This work presents a novel protection method for fine-grained access management in complex reconfigurable scan networks based on a challenge-response authentication protocol. The target scan network is extended with an authorization instrument and Secure Segment Insertion Bits (S²IB) that together control the accessibility of individual instruments. To the best of the authors’ knowledge, this is the first fine-grained access management scheme that scales well with the number of protected instruments and offers a high level of security. Compared with recent stateof- the-art techniques, this scheme is more favorable with respect to implementation cost, performance overhead, and provided security level.
BibTeX:
@article{BaranKW2015a,
  author = {Baranowski, Rafal and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Fine-Grained Access Management in Reconfigurable Scan Networks}},
  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)},
  year = {2015},
  volume = {34},
  number = {6},
  pages = {937--946},
  keywords = {Debug and diagnosis, reconfigurable scan network, IJTAG, IEEE Std 1687, secure DFT, hardware security, instrument protection},
  abstract = {Modern VLSI designs incorporate a high amount of instrumentation that supports post-silicon validation and debug, volume test and diagnosis, as well as in-field system monitoring and maintenance. Reconfigurable scan architectures, as allowed by the novel IEEE Std 1149.1-2013 (JTAG) and IEEE Std 1687- 2014 (IJTAG), emerge as a scalable mechanism for access to such on-chip instruments. While the on-chip instrumentation is crucial for meeting quality, dependability, and time-to-market goals, it is prone to abuse and threatens system safety and security. A secure access management method is mandatory to assure that critical instruments be accessible to authorized entities only. This work presents a novel protection method for fine-grained access management in complex reconfigurable scan networks based on a challenge-response authentication protocol. The target scan network is extended with an authorization instrument and Secure Segment Insertion Bits (S²IB) that together control the accessibility of individual instruments. To the best of the authors’ knowledge, this is the first fine-grained access management scheme that scales well with the number of protected instruments and offers a high level of security. Compared with recent stateof- the-art techniques, this scheme is more favorable with respect to implementation cost, performance overhead, and provided security level.},
  doi = {http://dx.doi.org/10.1109/TCAD.2015.2391266},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/TCAD_BaranKW2015.pdf}
}
40. GPU-Accelerated Small Delay Fault Simulation
Schneider, E., Holst, S., Kochte, M.A., Wen, X. and Wunderlich, H.-J.
Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE'15), Grenoble, France, 9-13 March 2015, pp. 1174-1179
Best Paper Candidate
2015
URL PDF 
Abstract: The simulation of delay faults is an essential task in design validation and reliability assessment of circuits. Due to the high sensitivity of current nano-scale designs against smallest delay deviations, small delay faults recently became the focus of test research. Because of the subtle delay impact, traditional fault simulation approaches based on abstract timing models are not sufficient for representing small delay faults. Hence, timing accurate simulation approaches have to be utilized, which quickly become inapplicable for larger designs due to high computational requirements. In this work we present a waveform-accurate approach for fast high-throughput small delay fault simulation on Graphics Processing Units (GPUs). By exploiting parallelism from gates, faults and patterns, the proposed approach enables accurate exhaustive small delay fault simulation even for multi-million gate designs without fault dropping for the first time.
BibTeX:
@inproceedings{SchneHKWW2015,
  author = { Schneider, Eric and Holst, Stefan and Kochte, Michael A. and Wen, Xiaoqing and Wunderlich, Hans-Joachim },
  title = {{GPU-Accelerated Small Delay Fault Simulation}},
  booktitle = {Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE'15)},
  year = {2015},
  pages = {1174--1179},
  abstract = {The simulation of delay faults is an essential task in design validation and reliability assessment of circuits. Due to the high sensitivity of current nano-scale designs against smallest delay deviations, small delay faults recently became the focus of test research. Because of the subtle delay impact, traditional fault simulation approaches based on abstract timing models are not sufficient for representing small delay faults. Hence, timing accurate simulation approaches have to be utilized, which quickly become inapplicable for larger designs due to high computational requirements. In this work we present a waveform-accurate approach for fast high-throughput small delay fault simulation on Graphics Processing Units (GPUs). By exploiting parallelism from gates, faults and patterns, the proposed approach enables accurate exhaustive small delay fault simulation even for multi-million gate designs without fault dropping for the first time.},
  url = { http://dl.acm.org/citation.cfm?id=2757084 },
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/DATE_SchneHKWW2015.pdf}
}
39. Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation
Baranowski, R., Kochte, M.A. and Wunderlich, H.-J.
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Vol. 20(2), February 2015, pp. 30:1-30:27
2015
DOI PDF 
Keywords: Algorithms, Verification, Performance
Abstract: Efficient access to on-chip instrumentation is a key requirement for post-silicon validation, test, debug, bringup, and diagnosis. Reconfigurable scan networks, as proposed by e.g. IEEE P1687 and IEEE Std 1149.1-2013, emerge as an effective and affordable means to cope with the increasing complexity of on-chip infrastructure. Reconfigurable scan networks are often hierarchical and may have complex structural and functional dependencies. Common approaches for scan verification based on static structural analysis and functional simulation are not sufficient to ensure correct operation of these types of architectures. To access an instrument in a reconfigurable scan network, a scan-in bit sequence must be generated according to the current state and structure of the network. Due to sequential and combinational dependencies, the access pattern generation process (pattern retargeting) poses a complex decision and optimization problem. This article presents the first generalized formal model that considers structural and functional dependencies of reconfigurable scan networks and is directly applicable to P1687-based and 1149.1-2013-based scan architectures. This model enables efficient formal verification of complex scan networks, as well as automatic generation of access patterns. The proposed pattern generation method supports concurrent access to multiple target scan registers (access merging) and generates short scan-in sequences.
BibTeX:
@article{BaranKW2015,
  author = {Baranowski, Rafal and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation}},
  journal = {ACM Transactions on Design Automation of Electronic Systems (TODAES)},
  year = {2015},
  volume = {20},
  number = {2},
  pages = {30:1--30:27},
  keywords = {Algorithms, Verification, Performance},
  abstract = {Efficient access to on-chip instrumentation is a key requirement for post-silicon validation, test, debug, bringup, and diagnosis. Reconfigurable scan networks, as proposed by e.g. IEEE P1687 and IEEE Std 1149.1-2013, emerge as an effective and affordable means to cope with the increasing complexity of on-chip infrastructure. Reconfigurable scan networks are often hierarchical and may have complex structural and functional dependencies. Common approaches for scan verification based on static structural analysis and functional simulation are not sufficient to ensure correct operation of these types of architectures. To access an instrument in a reconfigurable scan network, a scan-in bit sequence must be generated according to the current state and structure of the network. Due to sequential and combinational dependencies, the access pattern generation process (pattern retargeting) poses a complex decision and optimization problem. This article presents the first generalized formal model that considers structural and functional dependencies of reconfigurable scan networks and is directly applicable to P1687-based and 1149.1-2013-based scan architectures. This model enables efficient formal verification of complex scan networks, as well as automatic generation of access patterns. The proposed pattern generation method supports concurrent access to multiple target scan registers (access merging) and generates short scan-in sequences.},
  doi = {http://dx.doi.org/10.1145/2699863},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/TODAES_BaranKW2015.pdf}
}
38. Access Port Protection for Reconfigurable Scan Networks
Baranowski, R., Kochte, M.A. and Wunderlich, H.-J.
Journal of Electronic Testing: Theory and Applications (JETTA)
Vol. 30(6), December 2014, pp. 711-723
2014 JETTA-TTTC Best Paper Award
2014
DOI URL PDF 
Keywords: Debug and diagnosis, reconfigurable scan network, IJTAG, IEEE P1687, secure DFT, hardware security
Abstract: Scan infrastructures based on IEEE Std. 1149.1 (JTAG), 1500 (SECT), and P1687 (IJTAG) provide a cost-effective access mechanism for test, reconfiguration, and debugging purposes. The improved accessibility of on-chip instruments, however, poses a serious threat to system safety and security. While state-of-theart protection methods for scan architectures compliant with JTAG and SECT are very effective, most of these techniques face scalability issues in reconfigurable scan networks allowed by the upcoming IJTAG standard. This paper describes a scalable solution for multilevel access management in reconfigurable scan networks. The access to protected instruments is restricted locally at the interface to the network. The access restriction is realized by a sequence filter that allows only a precomputed set of scan-in access sequences. This approach does not require any modification of the scan architecture and causes no access time penalty. Therefore, it is well suited for core-based designs with hard macros and 3D integrated circuits. Experimental results for complex reconfigurable scan networks show that the area overhead depends primarily on the number of allowed accesses, and is marginal even if this number exceeds the count of registers in the network.
BibTeX:
@article{BaranKW2014a,
  author = {Baranowski, Rafal and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Access Port Protection for Reconfigurable Scan Networks}},
  journal = {Journal of Electronic Testing: Theory and Applications (JETTA)},
  publisher = {Springer-Verlag},
  year = {2014},
  volume = {30},
  number = {6},
  pages = {711--723},
  keywords = {Debug and diagnosis, reconfigurable scan network, IJTAG, IEEE P1687, secure DFT, hardware security},
  abstract = {Scan infrastructures based on IEEE Std. 1149.1 (JTAG), 1500 (SECT), and P1687 (IJTAG) provide a cost-effective access mechanism for test, reconfiguration, and debugging purposes. The improved accessibility of on-chip instruments, however, poses a serious threat to system safety and security. While state-of-theart protection methods for scan architectures compliant with JTAG and SECT are very effective, most of these techniques face scalability issues in reconfigurable scan networks allowed by the upcoming IJTAG standard. This paper describes a scalable solution for multilevel access management in reconfigurable scan networks. The access to protected instruments is restricted locally at the interface to the network. The access restriction is realized by a sequence filter that allows only a precomputed set of scan-in access sequences. This approach does not require any modification of the scan architecture and causes no access time penalty. Therefore, it is well suited for core-based designs with hard macros and 3D integrated circuits. Experimental results for complex reconfigurable scan networks show that the area overhead depends primarily on the number of allowed accesses, and is marginal even if this number exceeds the count of registers in the network.},
  url = { http://link.springer.com/article/10.1007/s10836-014-5484-2 },
  doi = {http://dx.doi.org/10.1007/s10836-014-5484-2},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/JETTA_BaranKW2014.pdf}
}
37. Test Pattern Generation in Presence of Unknown Values Based on Restricted Symbolic Logic
Erb, D., Scheibler, K., Kochte, M.A., Sauer, M., Wunderlich, H.-J. and Becker, B.
Proceedings of the IEEE International Test Conference (ITC'14), Seattle, Washington, USA, 20-23 October 2014, pp. 1-10
2014
DOI PDF 
Keywords: SAT, QBF, test generation, ATPG, Unknown values, Restricted symbolic logic
Abstract: Test generation algorithms based on standard n-valued logic algebras are pessimistic in presence of unknown (X) values, overestimate the number of signals with X-values and underestimate fault coverage. Recently, an ATPG algorithm based on quantified Boolean formula (QBF) has been presented, which is accurate in presence of X-values but has limits with respect to runtime, scalability and robustness. In this paper, we consider ATPG based on restricted symbolic logic (RSL) and demonstrate its potential. We introduce a complete RSL ATPG exploiting the full potential of RSL in ATPG. Experimental results demonstrate that RSL ATPG significantly increases fault coverage over classical algorithms and provides results very close to the accurate QBF-based algorithm. An optimized version of RSL ATPG (together with accurate fault simulation) is up to 618× faster than the QBF-based solution, more scalable and more robust.
BibTeX:
@inproceedings{ErbSKSWB2014,
  author = {Erb, Dominik and Scheibler, Karsten and Kochte, Michael A. and Sauer, Matthias and Wunderlich, Hans-Joachim and Becker, Bernd},
  title = {{Test Pattern Generation in Presence of Unknown Values Based on Restricted Symbolic Logic}},
  booktitle = {Proceedings of the IEEE International Test Conference (ITC'14)},
  year = {2014},
  pages = {1--10},
  keywords = {SAT, QBF, test generation, ATPG, Unknown values, Restricted symbolic logic},
  abstract = {Test generation algorithms based on standard n-valued logic algebras are pessimistic in presence of unknown (X) values, overestimate the number of signals with X-values and underestimate fault coverage. Recently, an ATPG algorithm based on quantified Boolean formula (QBF) has been presented, which is accurate in presence of X-values but has limits with respect to runtime, scalability and robustness. In this paper, we consider ATPG based on restricted symbolic logic (RSL) and demonstrate its potential. We introduce a complete RSL ATPG exploiting the full potential of RSL in ATPG. Experimental results demonstrate that RSL ATPG significantly increases fault coverage over classical algorithms and provides results very close to the accurate QBF-based algorithm. An optimized version of RSL ATPG (together with accurate fault simulation) is up to 618× faster than the QBF-based solution, more scalable and more robust.},
  doi = {http://dx.doi.org/10.1109/TEST.2014.7035350},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ITC_ErbSKSWB2014.pdf}
}
36. FAST-BIST: Faster-than-At-Speed BIST Targeting Hidden Delay Defects
Hellebrand, S., Indlekofer, T., Kampmann, M., Kochte, M.A., Liu, C. and Wunderlich, H.-J.
Proceedings of the IEEE International Test Conference (ITC'14), Seattle, Washington, USA, 20-23 October 2014, pp. 1-8
2014
DOI PDF 
Abstract: Small delay faults may be an indicator of a reliability threat, even if they do not affect the system functionality yet. In recent years, Faster-than-at-Speed-Test (FAST) has become a feasible method to detect faults, which are hidden by the timing slack or by long critical paths in the combinational logic. FAST poses severe challenges to the automatic test equipment with respect to timing, performance, and resolution. In this paper, it is shown how logic built-in self-test (BIST) or embedded deterministic test can be used for an efficient FAST application. Running BIST just at a higher frequency is not an option, as outputs of long paths will receive undefined values due to set time violations and destroy the content of the signature registers. Instead, for a given test pattern sequence, faults are classified according to the optimal detection frequency. For each class, a MISR-based compaction scheme is adapted, such that the critical bits to be observed can be determined by algebraic computations. Experiments show that rather a small number of inter-mediate signatures have to be evaluated to observe a large fraction of hidden delay faults testable by the given test sequence.
BibTeX:
@inproceedings{HelleIKKLW2014,
  author = {Hellebrand, Sybille and Indlekofer, Thomas and Kampmann, Matthias and Kochte, Michael A. and Liu, Chang and Wunderlich, Hans-Joachim},
  title = {{FAST-BIST: Faster-than-At-Speed BIST Targeting Hidden Delay Defects}},
  booktitle = {Proceedings of the IEEE International Test Conference (ITC'14)},
  year = {2014},
  pages = {1--8},
  abstract = {Small delay faults may be an indicator of a reliability threat, even if they do not affect the system functionality yet. In recent years, Faster-than-at-Speed-Test (FAST) has become a feasible method to detect faults, which are hidden by the timing slack or by long critical paths in the combinational logic. FAST poses severe challenges to the automatic test equipment with respect to timing, performance, and resolution. In this paper, it is shown how logic built-in self-test (BIST) or embedded deterministic test can be used for an efficient FAST application. Running BIST just at a higher frequency is not an option, as outputs of long paths will receive undefined values due to set time violations and destroy the content of the signature registers. Instead, for a given test pattern sequence, faults are classified according to the optimal detection frequency. For each class, a MISR-based compaction scheme is adapted, such that the critical bits to be observed can be determined by algebraic computations. Experiments show that rather a small number of inter-mediate signatures have to be evaluated to observe a large fraction of hidden delay faults testable by the given test sequence.},
  doi = {http://dx.doi.org/10.1109/TEST.2014.7035360},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ITC_HelleIKKLW2014.pdf}
}
35. Area-Efficient Synthesis of Fault-Secure NoC Switches
Dalirsani, A., Kochte, M.A. and Wunderlich, H.-J.
Proceedings of the 20th IEEE International On-Line Testing Symposium (IOLTS'14), Platja d'Aro, Catalunya, Spain, 7-9 July 2014, pp. 13-18
2014
DOI PDF 
Keywords: Network-on-Chip, self-checking, fault-secure, online testing, concurrent error detection
Abstract: This paper introduces a hybrid method to synthesize area-efficient fault-secure NoC switches to detect all errors resulting from any single-point combinational or transition fault in switches and interconnect links. Firstly, the structural faults that are always detectable by data encoding at flit-level are identified. Next, the fault-secure structure is constructed with minimized area such that errors caused by the remaining faults are detected under any given input vector. The experimental evaluation shows significant area savings compared to conventional fault-secure schemes. In addition, the resulting structure can be reused for test compaction. This reduces the amount of test response data and test time without loss of fault coverage or diagnostic resolution.
BibTeX:
@inproceedings{DalirKW2014,
  author = {Dalirsani, Atefe and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Area-Efficient Synthesis of Fault-Secure NoC Switches}},
  booktitle = {Proceedings of the 20th IEEE International On-Line Testing Symposium (IOLTS'14)},
  year = {2014},
  pages = {13--18},
  keywords = {Network-on-Chip, self-checking, fault-secure, online testing, concurrent error detection},
  abstract = {This paper introduces a hybrid method to synthesize area-efficient fault-secure NoC switches to detect all errors resulting from any single-point combinational or transition fault in switches and interconnect links. Firstly, the structural faults that are always detectable by data encoding at flit-level are identified. Next, the fault-secure structure is constructed with minimized area such that errors caused by the remaining faults are detected under any given input vector. The experimental evaluation shows significant area savings compared to conventional fault-secure schemes. In addition, the resulting structure can be reused for test compaction. This reduces the amount of test response data and test time without loss of fault coverage or diagnostic resolution.},
  doi = {http://dx.doi.org/10.1109/IOLTS.2014.6873662},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/IOLTS_DalirKW2014.pdf}
}
34. GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems
Zhang, H., Kochte, M.A., Imhof, M.E., Bauer, L., Wunderlich, H.-J. and Henkel, J.
Proceedings of the 51st ACM/EDAC/IEEE Design Automation Conference (DAC'14), San Francisco, California, USA, 1-5 June 2014, pp. 1-6
HiPEAC Paper Award
2014
DOI PDF 
Abstract: Soft errors are a reliability threat for reconfigurable systems implemented with SRAM-based FPGAs. They can be handled through fault tolerance techniques like scrubbing and modular redundancy. However, selecting these techniques statically at design or compile time tends to be pessimistic and prohibits optimal adaptation to changing soft error rate at runtime.
We present the GUARD method which allows for autonomous runtime reliability management in reconfigurable architectures: Based on the error rate observed during runtime, the runtime system dynamically determines whether a computation should be executed by a hardened processor, or whether it should be accelerated by inherently less reliable reconfigurable hardware which can trade-off performance and reliability. GUARD is the first runtime system for reconfigurable architectures that guarantees a target reliability while optimizing the performance. This allows applications to dynamically chose the desired degree of reliability. Compared to related work with statically optimized fault tolerance techniques, GUARD provides up to 68.3% higher performance at the same target reliability.
BibTeX:
@inproceedings{ZhangKIBWH2014,
  author = {Zhang, Hongyan and Kochte, Michael A. and Imhof, Michael E. and Bauer, Lars and Wunderlich, Hans-Joachim and Henkel, Jörg},
  title = {{GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems}},
  booktitle = {Proceedings of the 51st ACM/EDAC/IEEE Design Automation Conference (DAC'14)},
  year = {2014},
  pages = {1--6},
  abstract = {Soft errors are a reliability threat for reconfigurable systems implemented with SRAM-based FPGAs. They can be handled through fault tolerance techniques like scrubbing and modular redundancy. However, selecting these techniques statically at design or compile time tends to be pessimistic and prohibits optimal adaptation to changing soft error rate at runtime.
We present the GUARD method which allows for autonomous runtime reliability management in reconfigurable architectures: Based on the error rate observed during runtime, the runtime system dynamically determines whether a computation should be executed by a hardened processor, or whether it should be accelerated by inherently less reliable reconfigurable hardware which can trade-off performance and reliability. GUARD is the first runtime system for reconfigurable architectures that guarantees a target reliability while optimizing the performance. This allows applications to dynamically chose the desired degree of reliability. Compared to related work with statically optimized fault tolerance techniques, GUARD provides up to 68.3% higher performance at the same target reliability.}, doi = {http://dx.doi.org/10.1145/2593069.2593146}, file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/DAC_ZhangKIBWH2014.pdf} }
33. Exact Logic and Fault Simulation in Presence of Unknowns
Erb, D., Kochte, M.A., Sauer, M., Hillebrecht, S., Schubert, T., Wunderlich, H.-J. and Becker, B.
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Vol. 19(3), June 2014, pp. 28:1-28:17
2014
DOI PDF 
Keywords: Algorithms, Reliability, Unknown values, simulation pessimism, exact logic simulation, exact fault simulation, SAT
Abstract: Logic and fault simulation are essential techniques in electronic design automation. The accuracy of standard simulation algorithms is compromised by unknown or X-values. This results in a pessimistic overestimation of X-valued signals in the circuit and a pessimistic underestimation of fault coverage.
This work proposes efficient algorithms for combinational and sequential logic as well as for stuck-at and transition-delay fault simulation that are free of any simulation pessimism in presence of unknowns. The SAT-based algorithms exactly classifiy all signal states. During fault simulation, each fault is accurately classified as either undetected, definitely detected, or possibly detected.
The pessimism with respect to unknowns present in classic algorithms is thoroughly investigated in the experimental results on benchmark circuits. The applicability of the proposed algorithms is demonstrated on larger industrial circuits. The results show that, by accurate analysis, the number of detected faults can be significantly increased without increasing the test-set size.
BibTeX:
@article{ErbKSHSWB2014,
  author = {Erb, Dominik and Kochte, Michael A. and Sauer, Matthias and Hillebrecht, Stefan and Schubert, Tobias and Wunderlich, Hans-Joachim and Becker, Bernd},
  title = {{Exact Logic and Fault Simulation in Presence of Unknowns}},
  journal = {ACM Transactions on Design Automation of Electronic Systems (TODAES)},
  year = {2014},
  volume = {19},
  number = {3},
  pages = {28:1--28:17},
  keywords = {Algorithms, Reliability, Unknown values, simulation pessimism, exact logic simulation, exact fault simulation, SAT},
  abstract = {Logic and fault simulation are essential techniques in electronic design automation. The accuracy of standard simulation algorithms is compromised by unknown or X-values. This results in a pessimistic overestimation of X-valued signals in the circuit and a pessimistic underestimation of fault coverage.
This work proposes efficient algorithms for combinational and sequential logic as well as for stuck-at and transition-delay fault simulation that are free of any simulation pessimism in presence of unknowns. The SAT-based algorithms exactly classifiy all signal states. During fault simulation, each fault is accurately classified as either undetected, definitely detected, or possibly detected.
The pessimism with respect to unknowns present in classic algorithms is thoroughly investigated in the experimental results on benchmark circuits. The applicability of the proposed algorithms is demonstrated on larger industrial circuits. The results show that, by accurate analysis, the number of detected faults can be significantly increased without increasing the test-set size.}, doi = {http://dx.doi.org/10.1145/2611760}, file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/TODAES_ErbKSHSWB2014.pdf} }
32. Resilience Articulation Point (RAP): Cross-layer Dependability Modeling for Nanometer System-on-chip Resilience
Herkersdorf, A., Aliee, H., Engel, M., Glaß, M., Gimmler-Dumont, C., Henkel, J., Kleeberger, V.B., Kochte, M.A., Kühn, J.M., Mueller-Gritschneder, D., Nassif, S.R., Rauchfuss, H., Rosenstiel, W., Schlichtmann, U., Shafique, M., Tahoori, M.B., Teich, J., Wehn, N., Weis, C. and Wunderlich, H.-J.
Elsevier Microelectronics Reliability Journal
Vol. 54(6-7), June-July 2014, pp. 1066-1074
2014
DOI PDF 
Keywords: Cross-layer SoC resilience, probabilistic dependability modeling, SRAM error models, critical charge, transient soft errors, permanent aging defects, error abstraction, error transformation, system-level failure analysis, resilience articulation point
Abstract: The Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro-interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells, voltage variations and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture-level resilience methods.
BibTeX:
@article{HerkeAEGGHKKKMNRRSSTTWWW2014,
  author = {Herkersdorf, Andreas and Aliee, Hananeh and Engel, Michael and Glaß, Michael and Gimmler-Dumont, Christina and Henkel, Jörg and Kleeberger, Veit B. and Kochte, Michael A. and Kühn, Johannes M. and Mueller-Gritschneder, Daniel and Nassif, Sani R. and Rauchfuss, Holm and Rosenstiel, Wolfgang and Schlichtmann, Ulf and Shafique, Muhammad and Tahoori, Mehdi B. and Teich, Jürgen and Wehn, Norbert and Weis, Christian and Wunderlich, Hans-Joachim },
  title = {{Resilience Articulation Point (RAP): Cross-layer Dependability Modeling for Nanometer System-on-chip Resilience}},
  journal = {Elsevier Microelectronics Reliability Journal},
  year = {2014},
  volume = {54},
  number = {6--7},
  pages = {1066--1074},
  keywords = {Cross-layer SoC resilience, probabilistic dependability modeling, SRAM error models, critical charge, transient soft errors, permanent aging defects, error abstraction, error transformation, system-level failure analysis, resilience articulation point},
  abstract = {The Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro-interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells, voltage variations and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture-level resilience methods. },
  doi = {http://dx.doi.org/10.1016/j.microrel.2013.12.012},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/Elsevier_HerkeAEGGHKKKMNRRSSTTWWW2014.pdf}
}
31. Verifikation Rekonfigurierbarer Scan-Netze
Baranowski, R., Kochte, M.A. and Wunderlich, H.-J.
Proceedings of the 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'14), Böblingen, Germany, 10-12 March 2014, pp. 137-146
2014
URL PDF 
Keywords: Verification, debug and diagnosis, reconfigurable scan network, IJTAG, IEEE P1687, design for test
Abstract: Rekonfigurierbare Scan-Netze, z. B. entsprechend IEEE Std. P1687 oder 1149.1-2013, ermöglichen den effizienten Zugriff auf On-Chip-Infrastruktur für Bringup, Debug, Post-Silicon-Validierung und Diagnose. Diese Scan-Netze sind oft hierarchisch und können komplexe strukturelle und funktionale Abhängigkeiten aufweisen. Bekannte Verfahren zur Verifikation von Scan-Ketten, basierend auf Simulation und struktureller Analyse, sind nicht geeignet, Korrektheitseigenschaften von komplexen Scan-Netzen zu verifizieren. Diese Arbeit stellt ein formales Modell für rekonfigurierbare Scan-Netze vor, welches die strukturellen und funktionalen Abhängigkeiten abbildet und anwendbar ist für Architekturen nach IEEE P1687. Das Modell dient als Grundlage für effizientes Bounded Model Checking von Eigenschaften, wie z. B. der Erreichbarkeit von Scan-Registern.
BibTeX:
@inproceedings{BaranKW2014,
  author = {Baranowski, Rafal and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Verifikation Rekonfigurierbarer Scan-Netze}},
  booktitle = {Proceedings of the 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'14)},
  year = {2014},
  pages = {137--146},
  keywords = {Verification, debug and diagnosis, reconfigurable scan network, IJTAG, IEEE P1687, design for test},
  abstract = {Rekonfigurierbare Scan-Netze, z. B. entsprechend IEEE Std. P1687 oder 1149.1-2013, ermöglichen den effizienten Zugriff auf On-Chip-Infrastruktur für Bringup, Debug, Post-Silicon-Validierung und Diagnose. Diese Scan-Netze sind oft hierarchisch und können komplexe strukturelle und funktionale Abhängigkeiten aufweisen. Bekannte Verfahren zur Verifikation von Scan-Ketten, basierend auf Simulation und struktureller Analyse, sind nicht geeignet, Korrektheitseigenschaften von komplexen Scan-Netzen zu verifizieren. Diese Arbeit stellt ein formales Modell für rekonfigurierbare Scan-Netze vor, welches die strukturellen und funktionalen Abhängigkeiten abbildet und anwendbar ist für Architekturen nach IEEE P1687. Das Modell dient als Grundlage für effizientes Bounded Model Checking von Eigenschaften, wie z. B. der Erreichbarkeit von Scan-Registern.},
  url = {https://cuvillier.de/de/shop/publications/6629-mbmv-2014},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/MBMV_BaranKW2014.pdf}
}
30. Securing Access to Reconfigurable Scan Networks
Baranowski, R., Kochte, M.A. and Wunderlich, H.-J.
Proceedings of the 22nd IEEE Asian Test Symposium (ATS'13), Yilan, Taiwan, 18-21 November 2013
2013
DOI PDF 
Keywords: Debug and diagnosis, reconfigurable scan network, IJTAG, IEEE P1687, secure DFT, hardware security
Abstract: The accessibility of on-chip embedded infrastructure for test, reconfiguration, and debug poses a serious safety and security problem. Special care is required in the design and development of scan architectures based on IEEE Std. 1149.1 (JTAG), IEEE Std. 1500, and especially reconfigurable scan networks, as allowed by the upcoming IEEE P1687 (IJTAG). Traditionally, the scan infrastructure is secured after manufacturing test using fuses that disable the test access port (TAP) completely or partially. The fuse-based approach is efficient if some scan chains or instructions of the TAP controller are to be permanently blocked. However, this approach becomes costly if fine-grained access management is required, and it faces scalability issues in reconfigurable scan networks. In this paper, we propose a scalable solution for multi-level access management in reconfigurable scan networks. The access to protected registers is restricted locally at TAP-level by a sequence filter which allows only a precomputed set of scan-in access sequences. Our approach does not require any modification of the scan architecture and causes no access time penalty. Experimental results for complex reconfigurable scan networks show that the area overhead depends primarily on the number of allowed accesses, and is marginal even if this number exceeds the count of network’s registers.
BibTeX:
@inproceedings{BaranKW2013a,
  author = {Baranowski, Rafal and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Securing Access to Reconfigurable Scan Networks}},
  booktitle = {Proceedings of the 22nd IEEE Asian Test Symposium (ATS'13)},
  year = {2013},
  keywords = {Debug and diagnosis, reconfigurable scan network, IJTAG, IEEE P1687, secure DFT, hardware security},
  abstract = {The accessibility of on-chip embedded infrastructure for test, reconfiguration, and debug poses a serious safety and security problem. Special care is required in the design and development of scan architectures based on IEEE Std. 1149.1 (JTAG), IEEE Std. 1500, and especially reconfigurable scan networks, as allowed by the upcoming IEEE P1687 (IJTAG). Traditionally, the scan infrastructure is secured after manufacturing test using fuses that disable the test access port (TAP) completely or partially. The fuse-based approach is efficient if some scan chains or instructions of the TAP controller are to be permanently blocked. However, this approach becomes costly if fine-grained access management is required, and it faces scalability issues in reconfigurable scan networks. In this paper, we propose a scalable solution for multi-level access management in reconfigurable scan networks. The access to protected registers is restricted locally at TAP-level by a sequence filter which allows only a precomputed set of scan-in access sequences. Our approach does not require any modification of the scan architecture and causes no access time penalty. Experimental results for complex reconfigurable scan networks show that the area overhead depends primarily on the number of allowed accesses, and is marginal even if this number exceeds the count of network’s registers.},
  doi = {http://dx.doi.org/10.1109/ATS.2013.61},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2013/ATS_BaranKW2013.pdf}
}
29. Accurate Multi-Cycle ATPG in Presence of X-Values
Erb, D., Kochte, M.A., Sauer, M., Wunderlich, H.-J. and Becker, B.
Proceedings of the 22nd IEEE Asian Test Symposium (ATS'13), Yilan, Taiwan, 18-21 November 2013
2013
DOI PDF 
Keywords: Unknown values, test generation, ATPG, QBF, multi-cycle, partial scan
Abstract: Unknown (X) values in a circuit impair test quality and increase test costs. Classical n-valued algorithms for fault simulation and ATPG, which typically use a three- or four-valued logic for the good and faulty circuit, are in principle pessimistic in presence of X-values and cannot accurately compute the achievable fault coverage.
In partial scan or pipelined circuits, X-values originate in non-scan flip-flops. These circuits are tested using multi-cycle tests. Here we present multi-cycle test generation techniques for circuits with X-values due to partial scan or other X-sources. The proposed techniques have been integrated into a multi-cycle ATPG framework which employs formal Boolean and quantified Boolean (QBF) satisfiability techniques to compute the possible signal states in the circuit accurately. Efficient encoding of the problem instance ensures reasonable runtimes.
We show that in presence of X-values, the detection of stuck-at faults requires not only exact formal reasoning in a single cycle, but especially the consideration of multiple cycles for excitation of the fault site as well as propagation and controlled reconvergence of fault effects.
For the first time, accurate deterministic ATPG for multi-cycle test application is supported for stuck-at faults. Experiments on ISCAS'89 and industrial circuits with X-sources show that this new approach increases the fault coverage considerably.
BibTeX:
@inproceedings{ErbKSWB2013,
  author = {Erb, Dominik and Kochte, Michael A. and Sauer, Matthias and Wunderlich, Hans-Joachim and Becker, Bernd},
  title = {{Accurate Multi-Cycle ATPG in Presence of X-Values}},
  booktitle = {Proceedings of the 22nd IEEE Asian Test Symposium (ATS'13)},
  year = {2013},
  keywords = {Unknown values, test generation, ATPG, QBF, multi-cycle, partial scan},
  abstract = { Unknown (X) values in a circuit impair test quality and increase test costs. Classical n-valued algorithms for fault simulation and ATPG, which typically use a three- or four-valued logic for the good and faulty circuit, are in principle pessimistic in presence of X-values and cannot accurately compute the achievable fault coverage.
In partial scan or pipelined circuits, X-values originate in non-scan flip-flops. These circuits are tested using multi-cycle tests. Here we present multi-cycle test generation techniques for circuits with X-values due to partial scan or other X-sources. The proposed techniques have been integrated into a multi-cycle ATPG framework which employs formal Boolean and quantified Boolean (QBF) satisfiability techniques to compute the possible signal states in the circuit accurately. Efficient encoding of the problem instance ensures reasonable runtimes.
We show that in presence of X-values, the detection of stuck-at faults requires not only exact formal reasoning in a single cycle, but especially the consideration of multiple cycles for excitation of the fault site as well as propagation and controlled reconvergence of fault effects.
For the first time, accurate deterministic ATPG for multi-cycle test application is supported for stuck-at faults. Experiments on ISCAS'89 and industrial circuits with X-sources show that this new approach increases the fault coverage considerably. }, doi = {http://dx.doi.org/10.1109/ATS.2013.53}, file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2013/ATS_ErbKSWB2013.pdf} }
28. SAT-based Code Synthesis for Fault-Secure Circuits
Dalirsani, A., Kochte, M.A. and Wunderlich, H.-J.
Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'13), New York City, NY, USA, 2-4 October 2013, pp. 38-44
2013
DOI URL PDF 
Keywords: Concurrent error detection (CED), error control coding, self-checking circuit, totally self-checking (TSC)
Abstract: This paper presents a novel method for synthesizing fault-secure circuits based on parity codes over groups of circuit outputs. The fault-secure circuit is able to detect all errors resulting from combinational and transition faults at a single node. The original circuit is not modified. If the original circuit is non-redundant, the result is a totally self-checking circuit. At first, the method creates the minimum number of parity groups such that the effect of each fault is not masked in at least one parity group. To ensure fault-secureness, the obtained groups are split such that no fault leads to silent data corruption. This is performed by a formal Boolean satisfiability (SAT) based analysis. Since the proposed method reduces the number of required parity groups, the number of two-rail checkers and the complexity of the prediction logic required for fault-secureness decreases as well. Experimental results show that the area overhead is much less compared to duplication and less in comparison to previous methods for synthesis of totally self-checking circuits. Since the original circuit is not modified, the method can be applied for fixed hard macros and IP cores.
BibTeX:
@inproceedings{DalirKW2013,
  author = {Dalirsani, Atefe and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{SAT-based Code Synthesis for Fault-Secure Circuits}},
  booktitle = {Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'13)},
  year = {2013},
  pages = {38--44},
  keywords = {Concurrent error detection (CED), error control coding, self-checking circuit, totally self-checking (TSC)},
  abstract = {This paper presents a novel method for synthesizing fault-secure circuits based on parity codes over groups of circuit outputs. The fault-secure circuit is able to detect all errors resulting from combinational and transition faults at a single node. The original circuit is not modified. If the original circuit is non-redundant, the result is a totally self-checking circuit. At first, the method creates the minimum number of parity groups such that the effect of each fault is not masked in at least one parity group. To ensure fault-secureness, the obtained groups are split such that no fault leads to silent data corruption. This is performed by a formal Boolean satisfiability (SAT) based analysis. Since the proposed method reduces the number of required parity groups, the number of two-rail checkers and the complexity of the prediction logic required for fault-secureness decreases as well. Experimental results show that the area overhead is much less compared to duplication and less in comparison to previous methods for synthesis of totally self-checking circuits. Since the original circuit is not modified, the method can be applied for fixed hard macros and IP cores.},
  url = {http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6653580},
  doi = {http://dx.doi.org/10.1109/DFT.2013.6653580},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2013/DFTS_DalirKW2013.pdf}
}
27. Module Diversification: Fault Tolerance and Aging Mitigation for Runtime Reconfigurable Architectures
Zhang, H., Bauer, L., Kochte, M.A., Schneider, E., Braun, C., Imhof, M.E., Wunderlich, H.-J. and Henkel, J.
Proceedings of the IEEE International Test Conference (ITC'13), Anaheim, California, USA, 10-12 September 2013
2013
DOI URL PDF 
Keywords: Reliability, online test, fault-tolerance, aging mitigation, partial runtime reconfiguration, FPGA
Abstract: Runtime reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) are attractive for realizing complex applications. However, being manufactured in latest semiconductor process technologies, FPGAs are increasingly prone to aging effects, which reduce the reliability of such systems and must be tackled by aging mitigation and application of fault tolerance techniques. This paper presents module diversification, a novel design method that creates different configurations for runtime reconfigurable modules. Our method provides fault tolerance by creating the minimal number of configurations such that for any faulty Configurable Logic Block (CLB) there is at least one configuration that does not use that CLB. Additionally, we determine the fraction of time that each configuration should be used to balance the stress and to mitigate the aging process in FPGA-based runtime reconfigurable systems. The generated configurations significantly improve reliability by fault-tolerance and aging mitigation.
BibTeX:
@inproceedings{ZhangBKSBIWH2013,
  author = {Zhang, Hongyan and Bauer, Lars and Kochte, Michael A. and Schneider, Eric and Braun, Claus and Imhof, Michael E. and Wunderlich, Hans-Joachim and Henkel, Jörg},
  title = {{Module Diversification: Fault Tolerance and Aging Mitigation for Runtime Reconfigurable Architectures}},
  booktitle = {Proceedings of the IEEE International Test Conference (ITC'13)},
  year = {2013},
  keywords = {Reliability, online test, fault-tolerance, aging mitigation, partial runtime reconfiguration, FPGA},
  abstract = {Runtime reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) are attractive for realizing complex applications. However, being manufactured in latest semiconductor process technologies, FPGAs are increasingly prone to aging effects, which reduce the reliability of such systems and must be tackled by aging mitigation and application of fault tolerance techniques. This paper presents module diversification, a novel design method that creates different configurations for runtime reconfigurable modules. Our method provides fault tolerance by creating the minimal number of configurations such that for any faulty Configurable Logic Block (CLB) there is at least one configuration that does not use that CLB. Additionally, we determine the fraction of time that each configuration should be used to balance the stress and to mitigate the aging process in FPGA-based runtime reconfigurable systems. The generated configurations significantly improve reliability by fault-tolerance and aging mitigation.},
  url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6651926},
  doi = {http://dx.doi.org/10.1109/TEST.2013.6651926},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2013/ITC_ZhangBKSBIWH2013.pdf}
}
26. Test Strategies for Reliable Runtime Reconfigurable Architectures
Bauer, L., Braun, C., Imhof, M.E., Kochte, M.A., Schneider, E., Zhang, H., Henkel, J. and Wunderlich, H.-J.
IEEE Transactions on Computers
Vol. 62(8), Los Alamitos, California, USA, August 2013, pp. 1494-1507
2013
DOI URL PDF 
Keywords: FPGA, Reconfigurable Architectures, Online Test
Abstract: FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. The reliability of FPGAs, being manufactured in latest technologies, is threatened by soft errors, as well as aging effects and latent defects.To ensure reliable reconfiguration, it is mandatory to guarantee the correct operation of the reconfigurable fabric. This can be achieved by periodic or on-demand online testing. This paper presents a reliable system architecture for runtime-reconfigurable systems, which integrates two non-concurrent online test strategies: Pre-configuration online tests (PRET) and post-configuration online tests (PORT). The PRET checks that the reconfigurable hardware is free of faults by periodic or on-demand tests. The PORT has two objectives: It tests reconfigured hardware units after reconfiguration to check that the configuration process completed correctly and it validates the expected functionality. During operation, PORT is used to periodically check the reconfigured hardware units for malfunctions in the programmable logic. Altogether, this paper presents PRET, PORT, and the system integration of such test schemes into a runtime-reconfigurable system, including the resource management and test scheduling. Experimental results show that the integration of online testing in reconfigurable systems incurs only minimum impact on performance while delivering high fault coverage and low test latency.
BibTeX:
@article{BauerBIKSZHW2013,
  author = {Bauer, Lars and Braun, Claus and Imhof, Michael E. and Kochte, Michael A. and Schneider, Eric and Zhang, Hongyan and Henkel, Jörg and Wunderlich, Hans-Joachim},
  title = {{Test Strategies for Reliable Runtime Reconfigurable Architectures}},
  journal = {IEEE Transactions on Computers},
  publisher = {IEEE Computer Society},
  year = {2013},
  volume = {62},
  number = {8},
  pages = {1494--1507},
  keywords = {FPGA, Reconfigurable Architectures, Online Test},
  abstract = {FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. The reliability of FPGAs, being manufactured in latest technologies, is threatened by soft errors, as well as aging effects and latent defects.To ensure reliable reconfiguration, it is mandatory to guarantee the correct operation of the reconfigurable fabric. This can be achieved by periodic or on-demand online testing. This paper presents a reliable system architecture for runtime-reconfigurable systems, which integrates two non-concurrent online test strategies: Pre-configuration online tests (PRET) and post-configuration online tests (PORT). The PRET checks that the reconfigurable hardware is free of faults by periodic or on-demand tests. The PORT has two objectives: It tests reconfigured hardware units after reconfiguration to check that the configuration process completed correctly and it validates the expected functionality. During operation, PORT is used to periodically check the reconfigured hardware units for malfunctions in the programmable logic. Altogether, this paper presents PRET, PORT, and the system integration of such test schemes into a runtime-reconfigurable system, including the resource management and test scheduling. Experimental results show that the integration of online testing in reconfigurable systems incurs only minimum impact on performance while delivering high fault coverage and low test latency.},
  url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6475939},
  doi = {http://dx.doi.org/10.1109/TC.2013.53},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2013/TC_BauerBIKSZHW2013.pdf}
}
25. Scan Pattern Retargeting and Merging with Reduced Access Time
Baranowski, R., Kochte, M.A. and Wunderlich, H.-J.
Proceedings of the IEEE European Test Symposium (ETS'13), Avignon, France, 27-30 May 2013, pp. 39-45
2013
DOI PDF 
Keywords: Design for debug & diagnosis, optimal pattern retargeting, scan pattern generation, reconfigurable scan network, IJTAG, P1687
Abstract: Efficient access to on-chip instrumentation is a key enabler for post-silicon validation, debug, bringup or diagnosis. Re- configurable scan networks, as proposed by e.g. the IEEE Std. P1687, emerge as an effective and affordable means to cope with the increasing complexity of on-chip infrastructure. To access an element in a reconfigurable scan network, a scan- in bit sequence must be generated according to the current state and structure of the network. Due to sequential and combinational dependencies, the scan pattern generation process (pattern retargeting) poses a complex decision and optimization problem. This work presents a method for scan pattern generation with reduced access time. We map the access time reduction to a pseudo- Boolean optimization problem, which enables the use of efficient solvers to exhaustively explore the search space of valid scan-in sequences. This is the first automated method for efficient pattern retargeting in complex reconfigurable scan architectures such as P1687- based networks. It supports the concurrent access to multiple target scan registers (access merging) and generates reduced (short) scan-in sequences, considering all sequential and combinational dependencies. The proposed method achieves an access time reduction by up to 88x or 2.4x in average w.r.t. unoptimized satisfying solutions.
BibTeX:
@inproceedings{BaranKW2013,
  author = {Baranowski, Rafal and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Scan Pattern Retargeting and Merging with Reduced Access Time}},
  booktitle = {Proceedings of the IEEE European Test Symposium (ETS'13)},
  publisher = {IEEE Computer Society},
  year = {2013},
  pages = {39--45},
  keywords = {Design for debug & diagnosis, optimal pattern retargeting, scan pattern generation, reconfigurable scan network, IJTAG, P1687},
  abstract = {Efficient access to on-chip instrumentation is a key enabler for post-silicon validation, debug, bringup or diagnosis. Re- configurable scan networks, as proposed by e.g. the IEEE Std. P1687, emerge as an effective and affordable means to cope with the increasing complexity of on-chip infrastructure. To access an element in a reconfigurable scan network, a scan- in bit sequence must be generated according to the current state and structure of the network. Due to sequential and combinational dependencies, the scan pattern generation process (pattern retargeting) poses a complex decision and optimization problem. This work presents a method for scan pattern generation with reduced access time. We map the access time reduction to a pseudo- Boolean optimization problem, which enables the use of efficient solvers to exhaustively explore the search space of valid scan-in sequences. This is the first automated method for efficient pattern retargeting in complex reconfigurable scan architectures such as P1687- based networks. It supports the concurrent access to multiple target scan registers (access merging) and generates reduced (short) scan-in sequences, considering all sequential and combinational dependencies. The proposed method achieves an access time reduction by up to 88x or 2.4x in average w.r.t. unoptimized satisfying solutions.},
  doi = {http://dx.doi.org/10.1109/ETS.2013.6569354},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2013/ETS_BaranKW2013.pdf}
}
24. Accurate QBF-based Test Pattern Generation in Presence of Unknown Values
Hillebrecht, S., Kochte, M.A., Erb, D., Wunderlich, H.-J. and Becker, B.
Proceedings of the Conference on Design, Automation and Test in Europe (DATE'13), Grenoble, France, 18-22 March 2013, pp. 436-441
2013
DOI PDF 
Keywords: Unknown values, test generation, ATPG, QBF
Abstract: Unknown (X) values may emerge during the design process as well as during system operation and test application. Sources of X-values are for example black boxes, clockdomain boundaries, analog-to-digital converters, or uncontrolled or uninitialized sequential elements. To compute a detecting pattern for a given stuck-at fault, well defined logic values are required both for fault activation as well as for fault effect propagation to observing outputs. In presence of X-values, classical test generation algorithms, based on topological algorithms or formal Boolean satisfiability (SAT) or BDD-based reasoning, may fail to generate testing patterns or to prove faults untestable. This work proposes the first efficient stuck-at fault ATPG algorithm able to prove testability or untestability of faults in presence of X-values. It overcomes the principal inaccuracy and pessimism of classical algorithms when X-values are considered. This accuracy is achieved by mapping the test generation problem to an instance of quantified Boolean formula (QBF) satisfiability. The resulting fault coverage improvement is shown by experimental results on ISCAS benchmark and larger industrial circuits.
BibTeX:
@inproceedings{HilleKEWB2013,
  author = {Hillebrecht, Stefan and Kochte, Michael A. and Erb, Dominik and Wunderlich, Hans-Joachim and Becker, Bernd},
  title = {{Accurate QBF-based Test Pattern Generation in Presence of Unknown Values}},
  booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe (DATE'13)},
  publisher = {IEEE Computer Society},
  year = {2013},
  pages = {436--441},
  keywords = {Unknown values, test generation, ATPG, QBF},
  abstract = {Unknown (X) values may emerge during the design process as well as during system operation and test application. Sources of X-values are for example black boxes, clockdomain boundaries, analog-to-digital converters, or uncontrolled or uninitialized sequential elements. To compute a detecting pattern for a given stuck-at fault, well defined logic values are required both for fault activation as well as for fault effect propagation to observing outputs. In presence of X-values, classical test generation algorithms, based on topological algorithms or formal Boolean satisfiability (SAT) or BDD-based reasoning, may fail to generate testing patterns or to prove faults untestable. This work proposes the first efficient stuck-at fault ATPG algorithm able to prove testability or untestability of faults in presence of X-values. It overcomes the principal inaccuracy and pessimism of classical algorithms when X-values are considered. This accuracy is achieved by mapping the test generation problem to an instance of quantified Boolean formula (QBF) satisfiability. The resulting fault coverage improvement is shown by experimental results on ISCAS benchmark and larger industrial circuits.},
  doi = {http://dx.doi.org/10.7873/DATE.2013.098},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2013/DATE_HilleKEWB2013.pdf}
}
23. Accurate X-Propagation for Test Applications by SAT-Based Reasoning
Kochte, M.A., Elm, M. and Wunderlich, H.-J.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
Vol. 31(12), December 2012, pp. 1908-1919
2012
DOI PDF 
Keywords: Unknown values; stuck-at fault coverage; accurate fault simulation; simulation pessimism
Abstract: Unknown or X-values during test application may originate from uncontrolled sequential cells or macros, from clock or A/D boundaries or from tri-state logic. The exact identification of X-value propagation paths in logic circuits is crucial in logic simulation and fault simulation. In the first case, it enables the proper assessment of expected responses and the effective and efficient handling of X-values during test response compaction. In the second case, it is important for a proper assessment of fault coverage of a given test set and consequently influences the efficiency of test pattern generation. The commonly employed n-valued logic simulation evaluates the propagation of X-values only pessimistically, i.e. the X-propagation paths found by n- valued logic simulation are a superset of the actual propagation paths. This paper presents an efficient method to overcome this pessimism and to determine accurately the set of signals which carry an X-value for an input pattern. As examples, it investigates the influence of this pessimism on the two applications X-masking and stuck-at fault coverage assessment. The experimental results on benchmark and industrial circuits assess the pessimism of classic algorithms and show that these algorithms significantly overestimate the signals with X-values. The experiments show that overmasking of test data during test compression can be reduced by an accurate analysis. In stuck-at fault simulation, the coverage of the test set is increased by the proposed algorithm without incurring any overhead.
BibTeX:
@article{KochtEW2012,
  author = {Kochte, Michael A. and Elm, Melanie and Wunderlich, Hans-Joachim},
  title = {{Accurate X-Propagation for Test Applications by SAT-Based Reasoning}},
  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)},
  publisher = {IEEE Computer Society},
  year = {2012},
  volume = {31},
  number = {12},
  pages = {1908--1919},
  keywords = {Unknown values; stuck-at fault coverage; accurate fault simulation; simulation pessimism},
  abstract = {Unknown or X-values during test application may originate from uncontrolled sequential cells or macros, from clock or A/D boundaries or from tri-state logic. The exact identification of X-value propagation paths in logic circuits is crucial in logic simulation and fault simulation. In the first case, it enables the proper assessment of expected responses and the effective and efficient handling of X-values during test response compaction. In the second case, it is important for a proper assessment of fault coverage of a given test set and consequently influences the efficiency of test pattern generation. The commonly employed n-valued logic simulation evaluates the propagation of X-values only pessimistically, i.e. the X-propagation paths found by n- valued logic simulation are a superset of the actual propagation paths. This paper presents an efficient method to overcome this pessimism and to determine accurately the set of signals which carry an X-value for an input pattern. As examples, it investigates the influence of this pessimism on the two applications X-masking and stuck-at fault coverage assessment. The experimental results on benchmark and industrial circuits assess the pessimism of classic algorithms and show that these algorithms significantly overestimate the signals with X-values. The experiments show that overmasking of test data during test compression can be reduced by an accurate analysis. In stuck-at fault simulation, the coverage of the test set is increased by the proposed algorithm without incurring any overhead.},
  doi = {http://dx.doi.org/10.1109/TCAD.2012.2210422},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2012/TCAD_KochtEW2012.pdf}
}
22. Modeling, Verification and Pattern Generation for Reconfigurable Scan Networks
Baranowski, R., Kochte, M.A. and Wunderlich, H.-J.
Proceedings of the IEEE International Test Conference (ITC'12), Anaheim, California, USA, 5-8 November 2012, pp. 1-9
2012
DOI PDF 
Keywords: Reconfigurable scan network, Pattern generation, Pattern retargeting, DFT, IJTAG, P1687
Abstract: Reconfigurable scan architectures allow flexible integration and efficient access to infrastructure in SoCs, e.g. for test, diagnosis, repair or debug. Such scan networks are often hierarchical and have complex structural and functional dependencies. For instance, the IEEE P1687 proposal, known as IJTAG, allows integration of multiplexed scan networks with arbitrary internal control signals. Common approaches for scan verification based on static structural analysis and functional simulation are not sufficient to ensure correct operation of these types of architectures. Hierarchy and flexibility may result in complex or even contradicting configuration requirements to access single elements. Sequential logic justification is therefore mandatory both to verify the validity of a scan network, and to generate the required access sequences. This work presents a formal method for verification of reconfigurable scan architectures, as well as pattern retargeting, i.e. generation of required scan-in data. The method is based on a formal model of structural and functional dependencies. Network verification and pattern retargeting is mapped to a Boolean satisfiability problem, which enables the use of efficient SAT solvers to exhaustively explore the search space of valid scan configurations.
BibTeX:
@inproceedings{BaranKW2012,
  author = {Baranowski, Rafal and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Modeling, Verification and Pattern Generation for Reconfigurable Scan Networks}},
  booktitle = {Proceedings of the IEEE International Test Conference (ITC'12)},
  publisher = {IEEE Computer Society},
  year = {2012},
  pages = {1--9},
  keywords = {Reconfigurable scan network, Pattern generation, Pattern retargeting, DFT, IJTAG, P1687},
  abstract = {Reconfigurable scan architectures allow flexible integration and efficient access to infrastructure in SoCs, e.g. for test, diagnosis, repair or debug. Such scan networks are often hierarchical and have complex structural and functional dependencies. For instance, the IEEE P1687 proposal, known as IJTAG, allows integration of multiplexed scan networks with arbitrary internal control signals. Common approaches for scan verification based on static structural analysis and functional simulation are not sufficient to ensure correct operation of these types of architectures. Hierarchy and flexibility may result in complex or even contradicting configuration requirements to access single elements. Sequential logic justification is therefore mandatory both to verify the validity of a scan network, and to generate the required access sequences. This work presents a formal method for verification of reconfigurable scan architectures, as well as pattern retargeting, i.e. generation of required scan-in data. The method is based on a formal model of structural and functional dependencies. Network verification and pattern retargeting is mapped to a Boolean satisfiability problem, which enables the use of efficient SAT solvers to exhaustively explore the search space of valid scan configurations.},
  doi = {http://dx.doi.org/10.1109/TEST.2012.6401555},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2012/ITC_BaranKW2012.pdf}
}
21. Transparent Structural Online Test for Reconfigurable Systems
Abdelfattah, M.S., Bauer, L., Braun, C., Imhof, M.E., Kochte, M.A., Zhang, H., Henkel, J. and Wunderlich, H.-J.
Proceedings of the 18th IEEE International On-Line Testing Symposium (IOLTS'12), Sitges, Spain, 27-29 June 2012, pp. 37-42
2012
DOI PDF 
Keywords: FPGA; Reconfigurable Architectures; Online Test
Abstract: FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. However, the reliability of modern FPGAs is threatened by latent defects and aging effects. Hence, it is mandatory to ensure the reliable operation of the FPGA’s reconfigurable fabric. This can be achieved by periodic or on-demand online testing. In this paper, a system-integrated, transparent structural online test method for runtime reconfigurable systems is proposed. The required tests are scheduled like functional workloads, and thorough optimizations of the test overhead reduce the performance impact. The proposed scheme has been implemented on a reconfigurable system. The results demonstrate that thorough testing of the reconfigurable fabric can be achieved at negligible performance impact on the application.
BibTeX:
@inproceedings{AbdelBBIKZHW2012,
  author = {Abdelfattah, Mohamed S. and Bauer, Lars and Braun, Claus and Imhof, Michael E. and Kochte, Michael A. and Zhang, Hongyan and Henkel, Jörg and Wunderlich, Hans-Joachim},
  title = {{Transparent Structural Online Test for Reconfigurable Systems}},
  booktitle = {Proceedings of the 18th IEEE International On-Line Testing Symposium (IOLTS'12)},
  publisher = {IEEE Computer Society},
  year = {2012},
  pages = {37--42},
  keywords = {FPGA; Reconfigurable Architectures; Online Test},
  abstract = {FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. However, the reliability of modern FPGAs is threatened by latent defects and aging effects. Hence, it is mandatory to ensure the reliable operation of the FPGA’s reconfigurable fabric. This can be achieved by periodic or on-demand online testing. In this paper, a system-integrated, transparent structural online test method for runtime reconfigurable systems is proposed. The required tests are scheduled like functional workloads, and thorough optimizations of the test overhead reduce the performance impact. The proposed scheme has been implemented on a reconfigurable system. The results demonstrate that thorough testing of the reconfigurable fabric can be achieved at negligible performance impact on the application.},
  doi = {http://dx.doi.org/10.1109/IOLTS.2012.6313838},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2012/IOLTS_AbdelBBIKZHW2012.pdf}
}
20. OTERA: Online Test Strategies for Reliable Reconfigurable Architectures
Bauer, L., Braun, C., Imhof, M.E., Kochte, M.A., Zhang, H., Wunderlich, H.-J. and Henkel, J.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS'12), Erlangen, Germany, 25-28 June 2012, pp. 38-45
2012
DOI PDF 
Abstract: FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. However, the reliability of FPGAs, which are manufactured in latest technologies, is threatened not only by soft errors, but also by aging effects and latent defects. To ensure reliable reconfiguration, it is mandatory to guarantee the correct operation of the underlying reconfigurable fabric. This can be achieved by periodic or on-demand online testing. The OTERA project develops and evaluates components and strategies for reconfigurable systems that feature reliable reconfiguration. The research focus ranges from structural online tests for the FPGA infrastructure and functional online tests for the configured functionality up to the resource management and test scheduling. This paper gives an overview of the project tasks and presents first results.
BibTeX:
@inproceedings{BauerBIKZWH2012,
  author = {Bauer, Lars and Braun, Claus and Imhof, Michael E. and Kochte, Michael A. and Zhang, Hongyan and Wunderlich, Hans-Joachim and Henkel, Jörg},
  title = {{OTERA: Online Test Strategies for Reliable Reconfigurable Architectures}},
  booktitle = {Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS'12)},
  publisher = {IEEE Computer Society},
  year = {2012},
  pages = {38--45},
  abstract = {FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. However, the reliability of FPGAs, which are manufactured in latest technologies, is threatened not only by soft errors, but also by aging effects and latent defects. To ensure reliable reconfiguration, it is mandatory to guarantee the correct operation of the underlying reconfigurable fabric. This can be achieved by periodic or on-demand online testing. The OTERA project develops and evaluates components and strategies for reconfigurable systems that feature reliable reconfiguration. The research focus ranges from structural online tests for the FPGA infrastructure and functional online tests for the configured functionality up to the resource management and test scheduling. This paper gives an overview of the project tasks and presents first results.},
  doi = {http://dx.doi.org/10.1109/AHS.2012.6268667},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2012/AHS_BauerBIKZWH2012.pdf}
}
19. Exact Stuck-at Fault Classification in Presence of Unknowns
Hillebrecht, S., Kochte, M.A., Wunderlich, H.-J. and Becker, B.
Proceedings of the 17th IEEE European Test Symposium (ETS'12), Annecy, France, 28 May-1 June 2012, pp. 98-103
2012
DOI PDF 
Keywords: Unknown values; simulation pessimism; exact fault simulation; SAT
Abstract: Fault simulation is an essential tool in electronic design automation. The accuracy of the computation of fault coverage in classic n-valued simulation algorithms is compromised by unknown (X) values. This results in a pessimistic underestimation of the coverage, and overestimation of unknown (X) values at the primary and pseudo-primary outputs. This work proposes the first stuck-at fault simulation algorithm free of any simulation pessimism in presence of unknowns. The SAT-based algorithm exactly classifies any fault and distinguishes between definite and possible detects. The pessimism w. r. t. unknowns present in classic algorithms is discussed in the experimental results on ISCAS benchmark and industrial circuits. The applicability of our algorithm to large industrial circuits is demonstrated.
BibTeX:
@inproceedings{HilleKWB2012,
  author = {Hillebrecht, Stefan and Kochte, Michael A. and Wunderlich, Hans-Joachim and Becker, Bernd},
  title = {{Exact Stuck-at Fault Classification in Presence of Unknowns}},
  booktitle = {Proceedings of the 17th IEEE European Test Symposium (ETS'12)},
  publisher = {IEEE Computer Society},
  year = {2012},
  pages = {98--103},
  keywords = {Unknown values; simulation pessimism; exact fault simulation; SAT},
  abstract = {Fault simulation is an essential tool in electronic design automation. The accuracy of the computation of fault coverage in classic n-valued simulation algorithms is compromised by unknown (X) values. This results in a pessimistic underestimation of the coverage, and overestimation of unknown (X) values at the primary and pseudo-primary outputs. This work proposes the first stuck-at fault simulation algorithm free of any simulation pessimism in presence of unknowns. The SAT-based algorithm exactly classifies any fault and distinguishes between definite and possible detects. The pessimism w. r. t. unknowns present in classic algorithms is discussed in the experimental results on ISCAS benchmark and industrial circuits. The applicability of our algorithm to large industrial circuits is demonstrated.},
  doi = {http://dx.doi.org/10.1109/ETS.2012.6233017},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2012/ETS_HilleKWB2012.pdf}
}
18. Efficient BDD-based Fault Simulation in Presence of Unknown Values
Kochte, M.A., Kundu, S., Miyase, K., Wen, X. and Wunderlich, H.-J.
Proceedings of the 20th IEEE Asian Test Symposium (ATS'11), New Delhi, India, 20-23 November 2011, pp. 383-388
2011
DOI PDF 
Keywords: Unknown values; X propagation; precise fault simulation; symbolic simulation; BDD
Abstract: Unknown (X) values, originating from memories, clock domain boundaries or A/D interfaces, may compromise test signatures and fault coverage. Classical logic and fault simulation
algorithms are pessimistic w.r.t. the propagation of X values in the circuit. This work proposes efficient hybrid logic and stuck-at fault simulation algorithms which combine heuristics and local
BDDs to increase simulation accuracy. Experimental results on benchmark and large industrial circuits show significantly increased fault coverage and low runtime. The achieved simulation
precision is quantified for the first time.
BibTeX:
@inproceedings{KochtKMWW2011,
  author = {Kochte, Michael A. and Kundu, S. and Miyase, Kohei and Wen, Xiaoqing and Wunderlich, Hans-Joachim},
  title = {{Efficient BDD-based Fault Simulation in Presence of Unknown Values}},
  booktitle = {Proceedings of the 20th IEEE Asian Test Symposium (ATS'11)},
  publisher = {IEEE Computer Society},
  year = {2011},
  pages = {383--388},
  keywords = {Unknown values; X propagation; precise fault simulation; symbolic simulation; BDD},
  abstract = {Unknown (X) values, originating from memories, clock domain boundaries or A/D interfaces, may compromise test signatures and fault coverage. Classical logic and fault simulation
algorithms are pessimistic w.r.t. the propagation of X values in the circuit. This work proposes efficient hybrid logic and stuck-at fault simulation algorithms which combine heuristics and local
BDDs to increase simulation accuracy. Experimental results on benchmark and large industrial circuits show significantly increased fault coverage and low runtime. The achieved simulation
precision is quantified for the first time.}, doi = {http://dx.doi.org/10.1109/ATS.2011.52}, file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2011/ATS_KochtKMWW2011.pdf} }
17. A Novel Scan Segmentation Design Method for Avoiding Shift Timing Failures in Scan Testing
Yamato, Y., Wen, X., Kochte, M.A., Miyase, K., Kajihara, S. and Wang, L.-T.
Proceedings of the IEEE International Test Conference (ITC'11), Anaheim, California, USA, 20-22 September 2011
2011
DOI PDF 
Keywords: scan testing; shift power reduction; scan segmentation; switching activity; clock tree; clock skew
Abstract: High power consumption in scan testing can cause undue yield loss which has increasingly become a serious problem for deep-submicron VLSI circuits. Growing evidence attributes this problem to shift timing failures, which are primarily caused by excessive switching activity in the proximities of clock paths that tends to introduce severe clock skew due to IR-drop-induced delay increase. This paper is the first of its kind to address this critical issue with a novel layout-aware scheme based on scan segmentation design, called LCTI-SS (Low-Clock-Tree-
Impact Scan Segmentation). An optimal combination of scan segments is identified for simultaneous clocking so that the switching activity in the proximities of clock trees is reduced while maintaining the average power reduction effect on conventional scan segmentation. Experimental results on benchmark and industrial circuits have demonstrated the advantage of the LCTI-SS scheme.
BibTeX:
@inproceedings{YamatWKMKW2011,
  author = {Yamato, Yuta and Wen, Xiaoqing and Kochte, Michael A. and Miyase, Kohei and Kajihara, Seiji and Wang, Laung-Terng},
  title = {{A Novel Scan Segmentation Design Method for Avoiding Shift Timing Failures in Scan Testing}},
  booktitle = {Proceedings of the IEEE International Test Conference (ITC'11)},
  publisher = {IEEE Computer Society},
  year = {2011},
  keywords = {scan testing; shift power reduction; scan segmentation; switching activity; clock tree; clock skew},
  abstract = {High power consumption in scan testing can cause undue yield loss which has increasingly become a serious problem for deep-submicron VLSI circuits. Growing evidence attributes this problem to shift timing failures, which are primarily caused by excessive switching activity in the proximities of clock paths that tends to introduce severe clock skew due to IR-drop-induced delay increase. This paper is the first of its kind to address this critical issue with a novel layout-aware scheme based on scan segmentation design, called LCTI-SS (Low-Clock-Tree-
Impact Scan Segmentation). An optimal combination of scan segments is identified for simultaneous clocking so that the switching activity in the proximities of clock trees is reduced while maintaining the average power reduction effect on conventional scan segmentation. Experimental results on benchmark and industrial circuits have demonstrated the advantage of the LCTI-SS scheme.}, doi = {http://dx.doi.org/10.1109/TEST.2011.6139162}, file = {http://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2011/ITC_YamatWKMKW2011.pdf} }
16. Efficient Multi-level Fault Simulation of HW/SW Systems for Structural Faults
Baranowski, R., Di Carlo, S., Hatami, N., Imhof, M.E., Kochte, M.A., Prinetto, P., Wunderlich, H.-J. and Zoellin, C.G.
SCIENCE CHINA Information Sciences
Vol. 54(9), September 2011, pp. 1784-1796
2011
DOI PDF 
Keywords: fault simulation; multi-level; transaction-level modeling
Abstract: In recent technology nodes, reliability is increasingly considered a part of the standard design flow to be taken into account at all levels of embedded systems design. While traditional fault simulation techniques based on low-level models at gate- and register transfer-level offer high accuracy, they are too inefficient to properly cope with the complexity of modern embedded systems. Moreover, they do not allow for early exploration of design alternatives when a detailed model of the whole system is not yet available, which is highly required to increase the efficiency and quality of the design flow. Multi-level models that combine the simulation efficiency of high abstraction models with the accuracy of low-level models are therefore essential to efficiently evaluate the impact of physical defects on the system. This paper proposes a methodology to efficiently implement concurrent multi-level fault simulation across gate- and transaction-level models in an integrated simulation environment. It leverages state-of-the-art techniques for efficient fault simulation of structural faults together with transaction-level modeling. This combination of different models allows to accurately evaluate the impact of faults on the entire hardware/software system while keeping the computational effort low. Moreover, since only selected portions of the system require low-level models, early exploration of different design alternatives is efficiently supported. Experimental results obtained from three case studies are presented to demonstrate the high accuracy of the proposed method when compared with a standard gate/RT mixed-level approach and the strong improvement of simulation time which is reduced by four orders of magnitude in average.
BibTeX:
@article{BaranDHIKPWZ2011,
  author = {Baranowski, Rafal and Di Carlo, Stefano and Hatami, Nadereh and Imhof, Michael E. and Kochte, Michael A. and Prinetto, Paolo and Wunderlich, Hans-Joachim and Zoellin, Christian G.},
  title = {{Efficient Multi-level Fault Simulation of HW/SW Systems for Structural Faults}},
  journal = {SCIENCE CHINA Information Sciences},
  publisher = {Science China Press, co-published with Springer-Verlag},
  year = {2011},
  volume = {54},
  number = {9},
  pages = {1784--1796},
  keywords = {fault simulation; multi-level; transaction-level modeling},
  abstract = {In recent technology nodes, reliability is increasingly considered a part of the standard design flow to be taken into account at all levels of embedded systems design. While traditional fault simulation techniques based on low-level models at gate- and register transfer-level offer high accuracy, they are too inefficient to properly cope with the complexity of modern embedded systems. Moreover, they do not allow for early exploration of design alternatives when a detailed model of the whole system is not yet available, which is highly required to increase the efficiency and quality of the design flow. Multi-level models that combine the simulation efficiency of high abstraction models with the accuracy of low-level models are therefore essential to efficiently evaluate the impact of physical defects on the system. This paper proposes a methodology to efficiently implement concurrent multi-level fault simulation across gate- and transaction-level models in an integrated simulation environment. It leverages state-of-the-art techniques for efficient fault simulation of structural faults together with transaction-level modeling. This combination of different models allows to accurately evaluate the impact of faults on the entire hardware/software system while keeping the computational effort low. Moreover, since only selected portions of the system require low-level models, early exploration of different design alternatives is efficiently supported. Experimental results obtained from three case studies are presented to demonstrate the high accuracy of the proposed method when compared with a standard gate/RT mixed-level approach and the strong improvement of simulation time which is reduced by four orders of magnitude in average.},
  doi = {http://dx.doi.org/10.1007/s11432-011-4366-9},
  file = {http://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2011/SCIS_BaranDHIKPWZ2011.pdf}
}
15. SAT-based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures
Kochte, M.A., Miyase, K., Wen, X., Kajihara, S., Yamato, Y., Enokimoto, K. and Wunderlich, H.-J.
Proceedings of the 17th IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED'11), Fukuoka, Japan, 1-3 August 2011, pp. 33-38
2011
DOI URL PDF 
Keywords: Low capture-power test; X-filling; ATPG
Abstract: Excessive power dissipation during VLSI testing results in over-testing, yield loss and heat damage of the device. For low power devices with advanced power management features and more stringent power budgets, power-aware testing is even more mandatory. Effective and efficient test set postprocessing techniques based on X-identification and power-aware X-filling have been proposed for external and embedded deterministic test. This work proposes a novel X-filling algorithm for combinational and broadcast-scan-based test compression schemes which have great practical significance. The algorithm ensures compressibility of test cubes using a SAT-based check. Compared to methods based on topological justification, the solution space of the compressed test vector is not pruned early during the search. Thus, this method allows much more precise low-power X-filling of test vectors. Experiments on benchmark and industrial circuits show the applicability to capture-power reduction during scan testing.
BibTeX:
@inproceedings{KochtMWKYEW2011,
  author = {Kochte, Michael A. and Miyase, Kohei and Wen, Xiaoqing and Kajihara, Seiji and Yamato, Yuta and Enokimoto, Kazunari and Wunderlich, Hans-Joachim},
  title = {{SAT-based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures}},
  booktitle = {Proceedings of the 17th IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED'11)},
  publisher = {IEEE Computer Society},
  year = {2011},
  pages = {33--38},
  keywords = {Low capture-power test; X-filling; ATPG},
  abstract = {Excessive power dissipation during VLSI testing results in over-testing, yield loss and heat damage of the device. For low power devices with advanced power management features and more stringent power budgets, power-aware testing is even more mandatory. Effective and efficient test set postprocessing techniques based on X-identification and power-aware X-filling have been proposed for external and embedded deterministic test. This work proposes a novel X-filling algorithm for combinational and broadcast-scan-based test compression schemes which have great practical significance. The algorithm ensures compressibility of test cubes using a SAT-based check. Compared to methods based on topological justification, the solution space of the compressed test vector is not pruned early during the search. Thus, this method allows much more precise low-power X-filling of test vectors. Experiments on benchmark and industrial circuits show the applicability to capture-power reduction during scan testing.},
  url = {http://dl.acm.org/citation.cfm?id=2016802.2016812},
  doi = {http://dx.doi.org/10.1109/ISLPED.2011.5993600},
  file = {http://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2011/ISLPED_KochtMWKYEW2011.pdf}
}
14. Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing
Wen, X., Enokimoto, K., Miyase, K., Yamato, Y., Kochte, M.A., Kajihara, S., Girard, P. and Tehranipoor, M.
Proceedings of the 29th IEEE VLSI Test Symposium (VTS'11), Dana Point, California, USA, 1-5 May 2011, pp. 166-171
2011
DOI PDF 
Keywords: test generation; test power; at-speed scan testing; power supply noise; launch safety
Abstract: At-speed scan testing may suffer from severe yield loss due to the launch safety problem, where test responses are invalidated by excessive launch switching activity (LSA) caused by test stimulus launching in the at-speed test cycle. However, previous low-power test generation techniques can only reduce LSA to some extent but cannot guarantee launch safety. This paper proposes a novel & practical power-aware test generation flow, featuring guaranteed launch safety. The basic idea is to enhance ATPG with a unique two-phase (rescue & mask) scheme by targeting at the real cause of the launch safety problem, i.e., the excessive LSA in the neighboring areas (namely impact areas) around long paths sensitized by a test vector. The rescue phase is to reduce excessive LSA in impact areas in a focused manner, and the mask phase is to exclude from use in fault detection the uncertain test response at the endpoint of any long sensitized path that still has excessive LSA in its impact area even after the rescue phase is executed. This scheme is the first of its kind for achieving guaranteed launch safety with minimal impact on test quality and test costs, which is the ultimate goal of power-aware at-speed scan test generation.
BibTeX:
@inproceedings{WenEMYKKGT2011,
  author = {Wen, Xiaoqing and Enokimoto, Kazunari and Miyase, Kohei and Yamato, Yuta and Kochte, Michael A. and Kajihara, Seiji and Girard, Patrick and Tehranipoor, Mohammad},
  title = {{Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing}},
  booktitle = {Proceedings of the 29th IEEE VLSI Test Symposium (VTS'11)},
  publisher = {IEEE Computer Society},
  year = {2011},
  pages = {166--171},
  keywords = {test generation; test power; at-speed scan testing; power supply noise; launch safety},
  abstract = {At-speed scan testing may suffer from severe yield loss due to the launch safety problem, where test responses are invalidated by excessive launch switching activity (LSA) caused by test stimulus launching in the at-speed test cycle. However, previous low-power test generation techniques can only reduce LSA to some extent but cannot guarantee launch safety. This paper proposes a novel & practical power-aware test generation flow, featuring guaranteed launch safety. The basic idea is to enhance ATPG with a unique two-phase (rescue & mask) scheme by targeting at the real cause of the launch safety problem, i.e., the excessive LSA in the neighboring areas (namely impact areas) around long paths sensitized by a test vector. The rescue phase is to reduce excessive LSA in impact areas in a focused manner, and the mask phase is to exclude from use in fault detection the uncertain test response at the endpoint of any long sensitized path that still has excessive LSA in its impact area even after the rescue phase is executed. This scheme is the first of its kind for achieving guaranteed launch safety with minimal impact on test quality and test costs, which is the ultimate goal of power-aware at-speed scan test generation.},
  doi = {http://dx.doi.org/10.1109/VTS.2011.5783778},
  file = {http://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2011/VTS_WenEMYKKGT2011.pdf}
}
13. SAT-Based Fault Coverage Evaluation in the Presence of Unknown Values
Kochte, M.A. and Wunderlich, H.-J.
Proceedings of the ACM/IEEE Design Automation and Test in Europe (DATE'11), Grenoble, France, 14-18 March 2011, pp. 1303-1308
2011
DOI URL PDF 
Keywords: Unknown values; fault coverage; precise fault simulation
Abstract: Fault simulation of digital circuits must correctly compute fault coverage to assess test and product quality. In case of unknown values (X-values), fault simulation is pessimistic and underestimates actual fault coverage, resulting in increased test time and data volume, as well as higher overhead for design- for-test. This work proposes a novel algorithm to determine fault coverage with significantly increased accuracy, offering increased fault coverage at no cost, or the reduction of test costs for the targeted coverage. The algorithm is compared to related work and evaluated on benchmark and industrial circuits.
BibTeX:
@inproceedings{KochtW2011,
  author = {Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{SAT-Based Fault Coverage Evaluation in the Presence of Unknown Values}},
  booktitle = {Proceedings of the ACM/IEEE Design Automation and Test in Europe (DATE'11)},
  publisher = {IEEE Computer Society},
  year = {2011},
  pages = {1303--1308},
  keywords = {Unknown values; fault coverage; precise fault simulation},
  abstract = {Fault simulation of digital circuits must correctly compute fault coverage to assess test and product quality. In case of unknown values (X-values), fault simulation is pessimistic and underestimates actual fault coverage, resulting in increased test time and data volume, as well as higher overhead for design- for-test. This work proposes a novel algorithm to determine fault coverage with significantly increased accuracy, offering increased fault coverage at no cost, or the reduction of test costs for the targeted coverage. The algorithm is compared to related work and evaluated on benchmark and industrial circuits.},
  url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5763209},
  doi = {http://dx.doi.org/10.1109/DATE.2011.5763209},
  file = {http://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2011/DATE_KochtW2011.pdf}
}
12. On Determining the Real Output Xs by SAT-Based Reasoning
Elm, M., Kochte, M.A. and Wunderlich, H.-J.
Proceedings of the IEEE 19th Asian Test Symposium (ATS'10), Shanghai, China, 1-4 December 2010, pp. 39-44
2010
DOI URL PDF 
Keywords: X-Masking
Abstract: Embedded testing, built-in self-test and methods for test compression rely on efficient test response compaction. Often, a circuit under test contains sources of unknown values (X), uninitialized memories for instance. These X values propagate through the circuit and may spoil the response signatures. The standard way to overcome this problem is X-masking.
Outputs which carry an X value are usually determined by logic simulation. In this paper, we show that the amount of Xs is significantly overestimated, and in consequence outputs are overmasked, too. An efficient way for the exact computation of output Xs is presented for the first time. The resulting X-masking promises significant gains with respect to test time, test volume and fault coverage.
BibTeX:
@inproceedings{ElmKW2010,
  author = {Elm, Melanie and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{On Determining the Real Output Xs by SAT-Based Reasoning}},
  booktitle = {Proceedings of the IEEE 19th Asian Test Symposium (ATS'10)},
  publisher = {IEEE Computer Society},
  year = {2010},
  pages = {39--44},
  keywords = {X-Masking},
  abstract = {Embedded testing, built-in self-test and methods for test compression rely on efficient test response compaction. Often, a circuit under test contains sources of unknown values (X), uninitialized memories for instance. These X values propagate through the circuit and may spoil the response signatures. The standard way to overcome this problem is X-masking.
Outputs which carry an X value are usually determined by logic simulation. In this paper, we show that the amount of Xs is significantly overestimated, and in consequence outputs are overmasked, too. An efficient way for the exact computation of output Xs is presented for the first time. The resulting X-masking promises significant gains with respect to test time, test volume and fault coverage.}, url = {http://www.computer.org/csdl/proceedings/ats/2010/4248/00/4248a039-abs.html}, doi = {http://dx.doi.org/10.1109/ATS.2010.16}, file = {http://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2010/ATS_ElmKW2010.pdf} }
11. Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level
Kochte, M.A., Zoellin, C.G., Baranowski, R., Imhof, M.E., Wunderlich, H.-J., Hatami, N., Di Carlo, S. and Prinetto, P.
Proceedings of the IEEE 19th Asian Test Symposium (ATS'10), Shanghai, China, 1-4 December 2010, pp. 3-8
2010
DOI URL PDF 
Keywords: Fault simulation; multi-level; transaction-level modeling
Abstract: In recent technology nodes, reliability is considered a part of the standard design flow at all levels of embedded system design. While techniques that use only low-level models at gate- and register transfer-level offer high accuracy, they are too inefficient to consider the overall application of the embedded system. Multi-level models with high abstraction are essential to efficiently evaluate the impact of physical defects on the system. This paper provides a methodology that leverages state-of-the-art techniques for efficient fault simulation of structural faults together with transaction-level modeling. This way it is possible to accurately evaluate the impact of the faults on the entire hardware/software system. A case study of a system consisting of hardware and software for image compression and data encryption is presented and the method is compared to a standard gate/RT mixed-level approach.
BibTeX:
@inproceedings{KochtZBIWHDP2010b,
  author = {Kochte, Michael A. and Zoellin, Christian G. and Baranowski, Rafal and Imhof, Michael E. and Wunderlich, Hans-Joachim and Hatami, Nadereh and Di Carlo, Stefano and Prinetto, Paolo},
  title = {{Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level}},
  booktitle = {Proceedings of the IEEE 19th Asian Test Symposium (ATS'10)},
  publisher = {IEEE Computer Society},
  year = {2010},
  pages = {3--8},
  keywords = {Fault simulation; multi-level; transaction-level modeling},
  abstract = {In recent technology nodes, reliability is considered a part of the standard design flow at all levels of embedded system design. While techniques that use only low-level models at gate- and register transfer-level offer high accuracy, they are too inefficient to consider the overall application of the embedded system. Multi-level models with high abstraction are essential to efficiently evaluate the impact of physical defects on the system. This paper provides a methodology that leverages state-of-the-art techniques for efficient fault simulation of structural faults together with transaction-level modeling. This way it is possible to accurately evaluate the impact of the faults on the entire hardware/software system. A case study of a system consisting of hardware and software for image compression and data encryption is presented and the method is compared to a standard gate/RT mixed-level approach.},
  url = {http://www.computer.org/csdl/proceedings/ats/2010/4248/00/4248a003-abs.html},
  doi = {http://dx.doi.org/10.1109/ATS.2010.10},
  file = {http://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2010/ATS_KochtZBIWHDP2010.pdf}
}
10. System Reliability Evaluation Using Concurrent Multi-Level Simulation of Structural Faults
Kochte, M.A., Zoellin, C.G., Baranowski, R., Imhof, M.E., Wunderlich, H.-J., Hatami, N., Di Carlo, S. and Prinetto, P.
IEEE International Test Conference (ITC'10), Austin, Texas, USA, 31 October-5 November 2010
2010
DOI PDF 
Abstract: This paper provides a methodology that leverages state-of-the-art techniques for efficient fault simulation of structural faults together with transaction level modeling. This way it is possible to accurately evaluate the impact of the faults on the entire hardware/software system.
BibTeX:
@inproceedings{KochtZBIWHDP2010,
  author = {Kochte, Michael A. and Zoellin, Christian G. and Baranowski, Rafal and Imhof, Michael E. and Wunderlich, Hans-Joachim and Hatami, Nadereh and Di Carlo, Stefano and Prinetto, Paolo},
  title = {{System Reliability Evaluation Using Concurrent Multi-Level Simulation of Structural Faults}},
  booktitle = {IEEE International Test Conference (ITC'10)},
  publisher = {IEEE Computer Society},
  year = {2010},
  abstract = {This paper provides a methodology that leverages state-of-the-art techniques for efficient fault simulation of structural faults together with transaction level modeling. This way it is possible to accurately evaluate the impact of the faults on the entire hardware/software system.},
  doi = {http://dx.doi.org/10.1109/TEST.2010.5699309},
  file = {http://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2010/ITC_KochtZBIWHDP2010.pdf}
}
9. Efficient Concurrent Self-Test with Partially Specified Patterns
Kochte, M.A., Zoellin, C.G. and Wunderlich, H.-J.
Journal of Electronic Testing: Theory and Applications (JETTA)
Vol. 26(5), October 2010, pp. 581-594
2010
DOI URL  
Keywords: Concurrent self-test; BIST; Test generation; VLSI
Abstract: Structural on-line self-test may be performed to detect permanent faults and avoid their accumulation in the system. This paper improves existing techniques for concurrent BIST that are based on a deterministic test set. Here, the test patterns are specially generated with a small number of specified bits. This results in very low test length and fault detection latency, which allows to frequently test critical faults. As a consequence, the likelihood of fault accumulation is reduced. Experiments with benchmark circuits show that the hardware overhead is significantly lower than the overhead of the state of the art. Moreover, a case-study on a super-scalar RISC processor demonstrates the feasibility of the method.
BibTeX:
@article{KochtZW2010,
  author = {Kochte, Michael A. and Zoellin, Christian G. and Wunderlich, Hans-Joachim},
  title = {{Efficient Concurrent Self-Test with Partially Specified Patterns}},
  journal = {Journal of Electronic Testing: Theory and Applications (JETTA)},
  publisher = {Springer-Verlag},
  year = {2010},
  volume = {26},
  number = {5},
  pages = {581--594},
  keywords = {Concurrent self-test; BIST; Test generation; VLSI},
  abstract = {Structural on-line self-test may be performed to detect permanent faults and avoid their accumulation in the system. This paper improves existing techniques for concurrent BIST that are based on a deterministic test set. Here, the test patterns are specially generated with a small number of specified bits. This results in very low test length and fault detection latency, which allows to frequently test critical faults. As a consequence, the likelihood of fault accumulation is reduced. Experiments with benchmark circuits show that the hardware overhead is significantly lower than the overhead of the state of the art. Moreover, a case-study on a super-scalar RISC processor demonstrates the feasibility of the method.},
  url = {http://dl.acm.org/citation.cfm?id=1897730.1897739},
  doi = {http://dx.doi.org/10.1007/s10836-010-5167-6}
}
8. Effiziente Simulation von strukturellen Fehlern für die Zuverlässigkeitsanalyse auf Systemebene
Kochte, M.A., Zöllin, C.G., Baranowski, R., Imhof, M.E., Wunderlich, H.-J., Hatami, N., Di Carlo, S. and Prinetto, P.
4. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE'10)
Vol. 66, Wildbad Kreuth, Germany, 13-15 September 2010, pp. 25-32
2010
URL PDF 
Keywords: Transaktionsebenen-Modellierung; Ebenenübergreifende Fehlersimulation
Abstract: In aktueller Prozesstechnologie muss die Zuverlässigkeit in allen Entwurfsschritten von eingebetteten Systemen betrachtet werden. Methoden, die nur Modelle auf unteren Abstraktionsebenen, wie Gatter- oder Registertransferebene, verwenden, bieten zwar eine hohe Genauigkeit, sind aber zu ineffizient, um komplexe Hardware/Software-Systeme zu analysieren. Hier werden ebenenübergreifende Verfahren benötigt, die auch hohe Abstraktion unterstützen, um effizient die Auswirkungen von Defekten im System bewerten zu können. Diese Arbeit stellt eine Methode vor, die aktuelle Techniken für die effiziente Simulation von strukturellen Fehlern mit Systemmodellierung auf Transaktionsebene kombiniert. Auf dieseWeise ist es möglich, eine präzise Bewertung der Fehlerauswirkung auf das gesamte Hardware/Software-System durchzuführen. Die Ergebnisse einer Fallstudie eines Hardware/Software-Systems zur Datenverschlüsselung und Bildkompression werden diskutiert und die Methode wird mit einem Standard-Fehlerinjektionsverfahren verglichen.
BibTeX:
@inproceedings{KochtZBIWHDP2010a,
  author = {Kochte, Michael A. and Zöllin, Christian G. and Baranowski, Rafal and Imhof, Michael E. and Wunderlich, Hans-Joachim and Hatami, Nadereh and Di Carlo, Stefano and Prinetto, Paolo},
  title = {{Effiziente Simulation von strukturellen Fehlern für die Zuverlässigkeitsanalyse auf Systemebene}},
  booktitle = {4. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE'10)},
  publisher = {VDE VERLAG GMBH},
  year = {2010},
  volume = {66},
  pages = {25--32},
  keywords = {Transaktionsebenen-Modellierung; Ebenenübergreifende Fehlersimulation},
  abstract = {In aktueller Prozesstechnologie muss die Zuverlässigkeit in allen Entwurfsschritten von eingebetteten Systemen betrachtet werden. Methoden, die nur Modelle auf unteren Abstraktionsebenen, wie Gatter- oder Registertransferebene, verwenden, bieten zwar eine hohe Genauigkeit, sind aber zu ineffizient, um komplexe Hardware/Software-Systeme zu analysieren. Hier werden ebenenübergreifende Verfahren benötigt, die auch hohe Abstraktion unterstützen, um effizient die Auswirkungen von Defekten im System bewerten zu können. Diese Arbeit stellt eine Methode vor, die aktuelle Techniken für die effiziente Simulation von strukturellen Fehlern mit Systemmodellierung auf Transaktionsebene kombiniert. Auf dieseWeise ist es möglich, eine präzise Bewertung der Fehlerauswirkung auf das gesamte Hardware/Software-System durchzuführen. Die Ergebnisse einer Fallstudie eines Hardware/Software-Systems zur Datenverschlüsselung und Bildkompression werden diskutiert und die Methode wird mit einem Standard-Fehlerinjektionsverfahren verglichen.},
  url = {http://www.vde-verlag.de/proceedings-de/453299003.html},
  file = {http://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2010/ZuE_KochtZBIWHCP2010.pdf}
}
7. Efficient Fault Simulation on Many-Core Processors
Kochte, M.A., Schaal, M., Wunderlich, H.-J. and Zoellin, C.G.
Proceedings of the 47th ACM/IEEE Design Automation Conference (DAC'10), Anaheim, California, USA, 13-18 June 2010, pp. 380-385
2010
DOI URL PDF 
Keywords: Parallel Fault Simulation, Many-Core Processors, PPSFP
Abstract: Fault simulation is essential in test generation, design for test and reliability assessment of integrated circuits. Reliability analysis and the simulation of self-test structures are particularly computationally expensive as a large number of patterns has to be evaluated.
In this work, we propose to map a fault simulation algorithm based on the parallel-pattern single-fault propagation (PPSFP) paradigm to many-core architectures and describe the involved algorithmic optimizations. Many-core architectures are characterized by a high number of simple execution units with small local memory. The proposed fault simulation algorithm exploits the parallelism of these architectures by use of parallel data structures. The algorithm is implemented for the NVIDIA GT200 Graphics Processing Unit (GPU) architecture and achieves a speed-up of up to 17x compared to an existing GPU fault-simulation algorithm and up to 16x compared to state-of-the-art algorithms on conventional processor architectures.
BibTeX:
@inproceedings{KochtSWZ2010,
  author = {Kochte, Michael A. and Schaal, Marcel and Wunderlich, Hans-Joachim and Zoellin, Christian G.},
  title = {{Efficient Fault Simulation on Many-Core Processors}},
  booktitle = {Proceedings of the 47th ACM/IEEE Design Automation Conference (DAC'10)},
  publisher = {ACM},
  year = {2010},
  pages = {380--385},
  keywords = {Parallel Fault Simulation, Many-Core Processors, PPSFP},
  abstract = {Fault simulation is essential in test generation, design for test and reliability assessment of integrated circuits. Reliability analysis and the simulation of self-test structures are particularly computationally expensive as a large number of patterns has to be evaluated.
In this work, we propose to map a fault simulation algorithm based on the parallel-pattern single-fault propagation (PPSFP) paradigm to many-core architectures and describe the involved algorithmic optimizations. Many-core architectures are characterized by a high number of simple execution units with small local memory. The proposed fault simulation algorithm exploits the parallelism of these architectures by use of parallel data structures. The algorithm is implemented for the NVIDIA GT200 Graphics Processing Unit (GPU) architecture and achieves a speed-up of up to 17x compared to an existing GPU fault-simulation algorithm and up to 16x compared to state-of-the-art algorithms on conventional processor architectures.}, url = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5523154}, doi = {http://dx.doi.org/10.1145/1837274.1837369}, file = {http://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2010/DAC_KochteSWZ2010.pdf} }
6. Test Encoding for Extreme Response Compaction
Kochte, M.A., Holst, S., Elm, M. and Wunderlich, H.-J.
Proceedings of the 14th IEEE European Test Symposium (ETS'09), Sevilla, Spain, 25-29 May 2009, pp. 155-160
2009
DOI URL PDF 
Keywords: Design for Test; Embedded Diagnosis; Response Compaction; Test Compression
Abstract: Optimizing bandwidth by compression and compaction always has to solve the trade-off between input bandwidth reduction and output bandwidth reduction. Recently it has been shown that splitting scan chains into shorter segments and compacting the shift data outputs into a singleparity bit reduces the test response data to one bit per cycle without affecting fault coverage and diagnostic resolution if the compactor's structure is included into the ATPG process.

This test data reduction at the output side comes with challenges at the input side. The bandwidth requirement grows due to the increased number of chains and due to a drastically decreased amount of don't care values in the test patterns.

The paper at hand presents a new iterative approach to test set encoding which optimizes bandwidth on both input and output side while keeping the diagnostic resolution and fault coverage. Experiments with industrial designs demonstrate that test application time, test data volume and diagnostic resolution are improved at the same time and for most designs testing with a bandwidth of three bits per cycle is possible.

BibTeX:
@inproceedings{KochtHEW2009,
  author = {Kochte, Michael A. and Holst, Stefan and Elm, Melanie and Wunderlich, Hans-Joachim},
  title = {{Test Encoding for Extreme Response Compaction}},
  booktitle = {Proceedings of the 14th IEEE European Test Symposium (ETS'09)},
  publisher = {IEEE Computer Society},
  year = {2009},
  pages = {155--160},
  keywords = {Design for Test; Embedded Diagnosis; Response Compaction; Test Compression},
  abstract = {Optimizing bandwidth by compression and compaction always has to solve the trade-off between input bandwidth reduction and output bandwidth reduction. Recently it has been shown that splitting scan chains into shorter segments and compacting the shift data outputs into a singleparity bit reduces the test response data to one bit per cycle without affecting fault coverage and diagnostic resolution if the compactor's structure is included into the ATPG process.

This test data reduction at the output side comes with challenges at the input side. The bandwidth requirement grows due to the increased number of chains and due to a drastically decreased amount of don't care values in the test patterns.

The paper at hand presents a new iterative approach to test set encoding which optimizes bandwidth on both input and output side while keeping the diagnostic resolution and fault coverage. Experiments with industrial designs demonstrate that test application time, test data volume and diagnostic resolution are improved at the same time and for most designs testing with a bandwidth of three bits per cycle is possible.}, url = {http://www.computer.org/csdl/proceedings/ets/2009/3703/00/3703a155-abs.html}, doi = {http://dx.doi.org/10.1109/ETS.2009.22}, file = {http://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2009/ETS_KochtHEW2009.pdf} }

5. Concurrent Self-Test with Partially Specified Patterns For Low Test Latency and Overhead
Kochte, M.A., Zoellin, C.G. and Wunderlich, H.-J.
Proceedings of the 14th IEEE European Test Symposium (ETS'09), Sevilla, Spain, 25-29 May 2009, pp. 53-58
2009
DOI URL PDF 
Keywords: BIST; Concurrent self test; test generation
Abstract: Structural on-line self-test may be performed to detect permanent faults and avoid their accumulation. This paper improves concurrent BIST techniques based on a deterministic test set. Here, the test patterns are specially generated with a small number of specified bits. This results in very low test latency, which reduces the likelihood of fault accumulation. Experiments with a large number of circuits show that the hardware overhead is significantly lower than the overhead for previously published methods. Furthermore, the method allows to tradeoff fault coverage, test latency and hardware overhead.
BibTeX:
@inproceedings{KochtZW2009,
  author = {Kochte, Michael A. and Zoellin, Christian G. and Wunderlich, Hans-Joachim},
  title = {{Concurrent Self-Test with Partially Specified Patterns For Low Test Latency and Overhead}},
  booktitle = {Proceedings of the 14th IEEE European Test Symposium (ETS'09)},
  publisher = {IEEE Computer Society},
  year = {2009},
  pages = {53--58},
  keywords = {BIST; Concurrent self test; test generation},
  abstract = {Structural on-line self-test may be performed to detect permanent faults and avoid their accumulation. This paper improves concurrent BIST techniques based on a deterministic test set. Here, the test patterns are specially generated with a small number of specified bits. This results in very low test latency, which reduces the likelihood of fault accumulation. Experiments with a large number of circuits show that the hardware overhead is significantly lower than the overhead for previously published methods. Furthermore, the method allows to tradeoff fault coverage, test latency and hardware overhead.},
  url = {http://www.computer.org/csdl/proceedings/ets/2009/3703/00/3703a053-abs.html},
  doi = {http://dx.doi.org/10.1109/ETS.2009.26},
  file = {http://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2009/ETS_KochtZW2009.pdf}
}
4. Test Exploration and Validation Using Transaction Level Models
Kochte, M.A., Zoellin, C.G., Imhof, M.E., Salimi Khaligh, R., Radetzki, M., Wunderlich, H.-J., Di Carlo, S. and Prinetto, P.
Proceedings of the Conference on Design, Automation and Test in Europe (DATE'09), Nice, France, 20-24 April 2009, pp. 1250-1253
2009
DOI URL PDF 
Keywords: Test of systems-on-chip; design-for-test, transaction level modeling
Abstract: The complexity of the test infrastructure and test strategies in systems-on-chip approaches the complexity of the functional design space. This paper presents test design space exploration and validation of test strategies and schedules using transaction level models (TLMs). All aspects of the test infrastructure such as test access mechanisms, test wrappers, test data compression and test controllers are modeled at transaction level. Since many aspects of testing involve the transfer of a significant amount of test stimuli and responses, the communication-centric view of TLMs suits this purpose exceptionally well. A case study shows how TLMs can be used to efficiently evaluate DfT decisions in early design steps and how to evaluate test scheduling and resource partitioning during test planning. The presented approach has significantly higher simulation efficiency than RTL and gate level approaches.
BibTeX:
@inproceedings{KochtZISRWDP2009,
  author = {Kochte, Michael A. and Zoellin, Christian G. and Imhof, Michael E. and Salimi Khaligh, Rauf and Radetzki, Martin and Wunderlich, Hans-Joachim and Di Carlo, Stefano and Prinetto, Paolo},
  title = {{Test Exploration and Validation Using Transaction Level Models}},
  booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe (DATE'09)},
  publisher = {IEEE Computer Society},
  year = {2009},
  pages = {1250--1253},
  keywords = {Test of systems-on-chip; design-for-test, transaction level modeling},
  abstract = {The complexity of the test infrastructure and test strategies in systems-on-chip approaches the complexity of the functional design space. This paper presents test design space exploration and validation of test strategies and schedules using transaction level models (TLMs). All aspects of the test infrastructure such as test access mechanisms, test wrappers, test data compression and test controllers are modeled at transaction level. Since many aspects of testing involve the transfer of a significant amount of test stimuli and responses, the communication-centric view of TLMs suits this purpose exceptionally well. A case study shows how TLMs can be used to efficiently evaluate DfT decisions in early design steps and how to evaluate test scheduling and resource partitioning during test planning. The presented approach has significantly higher simulation efficiency than RTL and gate level approaches.},
  url = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5090856},
  doi = {http://dx.doi.org/10.1109/DATE.2009.5090856},
  file = {http://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2009/DATE_KochtZISRWDP2009.pdf}
}
3. Zur Zuverlässigkeitsmodellierung von Hardware-Software-Systemen;
On the Reliability Modeling of Hardware-Software-Systems

Kochte, M.A., Baranowski, R. and Wunderlich, H.-J.
2. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE'08)
Vol. 57, Ingolstadt, Germany, 29 September-1 October 2008, pp. 83-90
2008
URL PDF 
Keywords: Modellierung; Zuverlässigkeit; eingebettete Systeme; System-Level; Systems-on-Chip; Modeling; reliability; embedded systems; system-level; systems-on-chip
Abstract: Zur Zuverlässigkeitsanalyse von Hardware-Software-Systemen ist ein Systemmodell notwendig, welches sowohl Struktur und Architektur der Hardware als auch die ausgeführte Funktion betrachtet. Wird einer dieser Aspekte des Gesamtsystems vernachlässigt, kann sich eine zu optimische oder zu konservative Schätzung der Zuverlässigkeit ergeben. Ein reines Strukturmodell der Hardware erlaubt, den Einfluss von logischer und struktureller Fehlermaskierung auf die Fehlerhäufigkeit der Hardware zu bestimmen. Allerdings kann ein solches Modell nicht die Fehlerhäufigkeit des Gesamtsystems hinreichend genau schätzen. Die Ausführung der Funktion auf dem System führt zu speziellen Nutzungs- und Kommunikationsmustern der Systemkomponenten, die zu erhöhter oder verminderter Anfälligkeit gegenüber Fehlern führen. Diese Arbeit motiviert die Modellierung funktionaler Aspekte zusammen mit der Struktur des Systems. Mittels Fehlerinjektion und Simulation wird der starke Einfluss der Funktion auf die Fehleranfälligkeit des Systems aufgezeigt. Die vorgestellte Methodik, funktionale Aspekte mit in die Zuverlässigkeitsmodellierung einzubinden, verspricht eine realistischere Bewertung von Hardware-Software-Systemen.

Estimating the reliability of hardware-software systems allows to determine the robustness of design alternatives during design exploration. A system model used to derive such a reliability estimate has to incorporate the hardware structure and architecture of the system as well as the performed function. If merely the functional model or the structural model is considered separate from the other one, reliability estimation may be either too optimistic or too conservative.
While an architectural model allows to determine the impact of logical and architectural fault masking on the design's error rate, it fails to correctly predict the failure rate of the overall system. The function that is performed by the design exhibits particular usage and communication patterns that may--depending on the function--result in increased or reduced susceptibility to faults.
This work motivates to model functional aspects together with the architecture of the system. Fault injection and simulation show the strong influence of the function on the susceptability of the system. The proposed methodology to incorporate functional aspects into the system model for reliability estimation promises a more accurate assessment of hardware-software systems.

BibTeX:
@inproceedings{KochtBW2008,
  author = {Kochte, Michael A. and Baranowski, Rafal and Wunderlich, Hans-Joachim},
  title = {{Zur Zuverlässigkeitsmodellierung von Hardware-Software-Systemen;
On the Reliability Modeling of Hardware-Software-Systems}}, booktitle = {2. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE'08)}, publisher = {VDE VERLAG GMBH}, year = {2008}, volume = {57}, pages = {83--90}, keywords = {Modellierung; Zuverlässigkeit; eingebettete Systeme; System-Level; Systems-on-Chip; Modeling; reliability; embedded systems; system-level; systems-on-chip}, abstract = {Zur Zuverlässigkeitsanalyse von Hardware-Software-Systemen ist ein Systemmodell notwendig, welches sowohl Struktur und Architektur der Hardware als auch die ausgeführte Funktion betrachtet. Wird einer dieser Aspekte des Gesamtsystems vernachlässigt, kann sich eine zu optimische oder zu konservative Schätzung der Zuverlässigkeit ergeben. Ein reines Strukturmodell der Hardware erlaubt, den Einfluss von logischer und struktureller Fehlermaskierung auf die Fehlerhäufigkeit der Hardware zu bestimmen. Allerdings kann ein solches Modell nicht die Fehlerhäufigkeit des Gesamtsystems hinreichend genau schätzen. Die Ausführung der Funktion auf dem System führt zu speziellen Nutzungs- und Kommunikationsmustern der Systemkomponenten, die zu erhöhter oder verminderter Anfälligkeit gegenüber Fehlern führen. Diese Arbeit motiviert die Modellierung funktionaler Aspekte zusammen mit der Struktur des Systems. Mittels Fehlerinjektion und Simulation wird der starke Einfluss der Funktion auf die Fehleranfälligkeit des Systems aufgezeigt. Die vorgestellte Methodik, funktionale Aspekte mit in die Zuverlässigkeitsmodellierung einzubinden, verspricht eine realistischere Bewertung von Hardware-Software-Systemen.

Estimating the reliability of hardware-software systems allows to determine the robustness of design alternatives during design exploration. A system model used to derive such a reliability estimate has to incorporate the hardware structure and architecture of the system as well as the performed function. If merely the functional model or the structural model is considered separate from the other one, reliability estimation may be either too optimistic or too conservative.
While an architectural model allows to determine the impact of logical and architectural fault masking on the design's error rate, it fails to correctly predict the failure rate of the overall system. The function that is performed by the design exhibits particular usage and communication patterns that may--depending on the function--result in increased or reduced susceptibility to faults.
This work motivates to model functional aspects together with the architecture of the system. Fault injection and simulation show the strong influence of the function on the susceptability of the system. The proposed methodology to incorporate functional aspects into the system model for reliability estimation promises a more accurate assessment of hardware-software systems.}, url = {http://www.vde-verlag.de/proceedings-de/453119013.html}, file = {http://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2008/ZuE_KochtBW2008.pdf} }

2. A Framework for Scheduling Parallel DBMS User-Defined Programs on an Attached High-Performance Computer
Kochte, M.A. and Natarajan, R.
Proceedings of the 2008 conference on Computing frontiers (CF'08), Ischia, Italy, 5-7 May 2008, pp. 97-104
2008
DOI PDF 
Keywords: database accelerators; high-performance computing; parallel user-defined programs
Abstract: We describe a software framework for deploying, scheduling and executing parallel DBMS user-defined programs on an attached high-performance computer (HPC) platform. This framework is advantageous for many DBMS workloads in the following two aspects. First, the long-running user-defined programs can be speeded up by taking advantage of the greater hardware parallelism available on the attached HPC platform. Second, the interactive response time of the remaining applications on the database server platform is improved by the off-loading of long-running user-defined programs to the attached HPC platform. Our framework provides a new approach for integrating high-performance computing into the workflow of query-oriented, computationally-intensive applications.
BibTeX:
@inproceedings{KochtN2008,
  author = {Kochte, Michael A. and Natarajan, Ramesh},
  title = {{A Framework for Scheduling Parallel DBMS User-Defined Programs on an Attached High-Performance Computer}},
  booktitle = {Proceedings of the 2008 conference on Computing frontiers (CF'08)},
  publisher = {ACM},
  year = {2008},
  pages = {97--104},
  keywords = {database accelerators; high-performance computing; parallel user-defined programs},
  abstract = {We describe a software framework for deploying, scheduling and executing parallel DBMS user-defined programs on an attached high-performance computer (HPC) platform. This framework is advantageous for many DBMS workloads in the following two aspects. First, the long-running user-defined programs can be speeded up by taking advantage of the greater hardware parallelism available on the attached HPC platform. Second, the interactive response time of the remaining applications on the database server platform is improved by the off-loading of long-running user-defined programs to the attached HPC platform. Our framework provides a new approach for integrating high-performance computing into the workflow of query-oriented, computationally-intensive applications.},
  doi = {http://dx.doi.org/10.1145/1366230.1366245},
  file = {http://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2008/KochtN2008.pdf}
}
1. Test Set Stripping Limiting the Maximum Number of Specified Bits
Kochte, M.A., Zoellin, C.G., Imhof, M.E. and Wunderlich, H.-J.
Proceedings of the 4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA'08), Hong Kong, China, 23-25 January 2008, pp. 581-586
Best paper award
2008
DOI URL PDF 
Keywords: test relaxation; test generation; tailored ATPG
Abstract: This paper presents a technique that limits the maximum number of specified bits of any pattern in a given test set. The outlined method uses algorithms similar to ATPG, but exploits the information in the test set to quickly find test patterns with the desired properties. The resulting test sets show a significant reduction in the maximum number of specified bits in the test patterns. Furthermore, results for commercial ATPG test sets show that even the overall number of specified bits is reduced substantially
BibTeX:
@inproceedings{KochtZIW2008,
  author = {Kochte, Michael A. and Zoellin, Christian G. and Imhof, Michael E. and Wunderlich, Hans-Joachim},
  title = {{Test Set Stripping Limiting the Maximum Number of Specified Bits}},
  booktitle = {Proceedings of the 4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA'08)},
  publisher = {IEEE Computer Society},
  year = {2008},
  pages = {581--586},
  keywords = {test relaxation; test generation; tailored ATPG},
  abstract = {This paper presents a technique that limits the maximum number of specified bits of any pattern in a given test set. The outlined method uses algorithms similar to ATPG, but exploits the information in the test set to quickly find test patterns with the desired properties. The resulting test sets show a significant reduction in the maximum number of specified bits in the test patterns. Furthermore, results for commercial ATPG test sets show that even the overall number of specified bits is reduced substantially},
  url = {http://www.computer.org/csdl/proceedings/delta/2008/3110/00/3110a581-abs.html},
  doi = {http://dx.doi.org/10.1109/DELTA.2008.64},
  file = {http://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2008/DELTA_KochtZIW2008.pdf}
}
Created by JabRef on 13/06/2017.

Workshop Contributions

Matching entries: 0
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11. Autonomous Testing for 3D-ICs with IEEE Std. 1687
Ye, J.-C., Kochte, M.A., Lee, K.-J. and Wunderlich, H.-J.
First International Test Standards Application Workshop (TESTA), co-located with IEEE European Test Symposium, Amsterdam, The Netherlands, 26-27 May 2016
2016
 
BibTeX:
@inproceedings{YeKLW2016,
  author = {Ye, Jin-Cun and Kochte, Michael A. and Lee, Kuen-Jong and Wunderlich, Hans-Joachim},
  title = {{Autonomous Testing for 3D-ICs with IEEE Std. 1687}},
  booktitle = {First International Test Standards Application Workshop (TESTA), co-located with IEEE European Test Symposium},
  year = {2016}
}
10. Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler
Hellebrand, S., Indlekofer, T., Kampmann, M., Kochte, M.A., Liu, C. and Wunderlich, H.-J.
27th GI/GMM/ITG Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'15), Bad Urach, Germany, 1-3 March 2015
2015
 
BibTeX:
@inproceedings{HelleIKKLW2015,
  author = {Hellebrand, Sybille and Indlekofer, Thomas and Kampmann, Matthias and Kochte, Michael A. and Liu, Chang and Wunderlich, Hans-Joachim},
  title = {{Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler}},
  booktitle = {27th GI/GMM/ITG Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'15)},
  year = {2015}
}
9. Hochbeschleunigte Simulation von Verzögerungsfehlern unter Prozessvariationen
Schneider, E., Kochte, M.A. and Wunderlich, H.-J.
27th GI/GMM/ITG Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'15), Bad Urach, Germany, 1-3 March 2015
2015
 
Abstract: Die Simulation kleiner Verzögerungsfehler ist ein wichtiger Bestandteil der Validierung nano-elektronischer Schaltungen. Prozessvariationen während der Herstellung haben großen Einfluss auf die Erkennung dieser Fehler und müssen bei der Simulation berücksichtigt werden. Die zeitgenaue Simulation von Verzögerungsfehlern ist verglichen mit traditioneller Logiksimulation oder statischer Zeitanalyse sehr aufwändig und die Rechenkomplexität steigt durch die Berücksichtigung von Variationen zusätzlich an. In dieser Arbeit wird ein hochparalleles Verfahren vorgestellt, welches Grafikprozessoren zur beschleunigten parallelen Simulation kleiner Verzögerungsfehler unter Variation anwendet. Das Verfahren berechnet akkurate Signalverläufe in der Schaltung und ermöglicht die Bestimmung einer Monte-Carlo-basierten statistischen Fehlererfassung für industrielle Schaltkreise unter zufälliger sowie systematischer Variation.
BibTeX:
@inproceedings{SchneKW2015,
  author = {Schneider, Eric and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Hochbeschleunigte Simulation von Verzögerungsfehlern unter Prozessvariationen}},
  booktitle = {27th GI/GMM/ITG Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'15)},
  year = {2015},
  abstract = {Die Simulation kleiner Verzögerungsfehler ist ein wichtiger Bestandteil der Validierung nano-elektronischer Schaltungen. Prozessvariationen während der Herstellung haben großen Einfluss auf die Erkennung dieser Fehler und müssen bei der Simulation berücksichtigt werden. Die zeitgenaue Simulation von Verzögerungsfehlern ist verglichen mit traditioneller Logiksimulation oder statischer Zeitanalyse sehr aufwändig und die Rechenkomplexität steigt durch die Berücksichtigung von Variationen zusätzlich an. In dieser Arbeit wird ein hochparalleles Verfahren vorgestellt, welches Grafikprozessoren zur beschleunigten parallelen Simulation kleiner Verzögerungsfehler unter Variation anwendet. Das Verfahren berechnet akkurate Signalverläufe in der Schaltung und ermöglicht die Bestimmung einer Monte-Carlo-basierten statistischen Fehlererfassung für industrielle Schaltkreise unter zufälliger sowie systematischer Variation.}
}
8. Cross-Layer Dependability Modeling and Abstraction in Systems on Chip
Herkersdorf, A., Engel, M., Glaß, M., Henkel, J., Kleeberger, V.B., Kochte, M.A., Kühn, J.M., Nassif, S.R., Rauchfuss, H., Rosenstiel, W., Schlichtmann, U., Shafique, M., Tahoori, M.B., Teich, J., Wehn, N., Weis, C. and Wunderlich, H.-J.
Selse-9: The 9th Workshop on Silicon Errors in Logic - System Effects, Stanford, California, USA, 26-27 March 2013
2013
 
Keywords: Reliability Modeling, Cross-Layer
Abstract: The Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture level resilience methods.
BibTeX:
@inproceedings{HerkersdorfEGHKKKNRRSSTTWWW2013,
  author = {Herkersdorf, Andreas and Engel, Michael and Glaß, Michael and Henkel, Jörg and Kleeberger, Veit B. and Kochte, Michael A. and Kühn, Johannes M. and Nassif, Sani R. and Rauchfuss, Holm and Rosenstiel, Wolfgang and Schlichtmann, Ulf and Shafique, Muhammad and Tahoori, Mehdi B. and Teich, Jürgen and Wehn, Norbert and Weis, Christian and Wunderlich, Hans-Joachim},
  title = {{Cross-Layer Dependability Modeling and Abstraction in Systems on Chip}},
  booktitle = {Selse-9: The 9th Workshop on Silicon Errors in Logic - System Effects},
  year = {2013},
  keywords = {Reliability Modeling, Cross-Layer},
  abstract = {The Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture level resilience methods.}
}
7. Fault Modeling in Testing
Holst, S., Kochte, M.A. and Wunderlich, H.-J.
RAP Day Workshop, DFG SPP 1500, Munich, Germany, 21 December 2012
2012
 
Keywords: Fault modeling, generalized fault models, conditional fault models
BibTeX:
@inproceedings{HolstKW2012,
  author = {Holst, Stefan and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Fault Modeling in Testing}},
  booktitle = {RAP Day Workshop, DFG SPP 1500},
  year = {2012},
  keywords = {Fault modeling, generalized fault models, conditional fault models}
}
6. SAT-Based Fault Coverage Evaluation in the Presence of Unknown Values
Kochte, M.A. and Wunderlich, H.-J.
Fault Tolerant Computing Workshop (FTC Kenkyuukai), Ena, Gifu, Japan, 20-22 January 2011
2011
 
Keywords: Unknown values; fault coverage; precise fault simulation
Abstract: Fault simulation of digital circuits must correctly compute fault coverage to assess test and product quality. In case of unknown values (X-values), fault simulation is pessimistic and underestimates actual fault coverage, resulting in increased test time and data volume, as well as higher overhead for design- for-test. This work proposes a novel algorithm to determine fault coverage with significantly increased accuracy, offering increased fault coverage at no cost, or the reduction of test costs for the targeted coverage. The algorithm is compared to related work and evaluated on benchmark and industrial circuits.
BibTeX:
@inproceedings{KochtW2011,
  author = {Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{SAT-Based Fault Coverage Evaluation in the Presence of Unknown Values}},
  booktitle = {Fault Tolerant Computing Workshop (FTC Kenkyuukai)},
  year = {2011},
  keywords = {Unknown values; fault coverage; precise fault simulation},
  abstract = {Fault simulation of digital circuits must correctly compute fault coverage to assess test and product quality. In case of unknown values (X-values), fault simulation is pessimistic and underestimates actual fault coverage, resulting in increased test time and data volume, as well as higher overhead for design- for-test. This work proposes a novel algorithm to determine fault coverage with significantly increased accuracy, offering increased fault coverage at no cost, or the reduction of test costs for the targeted coverage. The algorithm is compared to related work and evaluated on benchmark and industrial circuits.}
}
5. Low-Capture-Power Post-Processing of Test Vectors for Test Compression Using SAT Solver
Miyase, K., Kochte, M.A., Wen, X., Kajihara, S. and Wunderlich, H.-J.
IEEE International Workshop on Defect and Data-Driven Testing (D3T'10), Austin, Texas, USA, 4-5 November 2010
2010
 
Keywords: Low power testing, power-safe test
BibTeX:
@inproceedings{MiyaseKWKW2010a,
  author = {Miyase, K. and Kochte, Michael A. and Wen, X. and Kajihara, S. and Wunderlich, Hans-Joachim},
  title = {{Low-Capture-Power Post-Processing of Test Vectors for Test Compression Using SAT Solver}},
  booktitle = {IEEE International Workshop on Defect and Data-Driven Testing (D3T'10)},
  year = {2010},
  keywords = {Low power testing, power-safe test}
}
4. On Determining the Real Output Xs by SAT-Based Reasoning
Elm, M., Kochte, M.A. and Wunderlich, H.-J.
Fault Tolerant Computing Workshop (FTC Kenkyuukai), Chichibu, Japan, 15-17 July 2010
2010
 
Keywords: X-Masking
Abstract: Embedded testing, built-in self-test and methods for test compression rely on efficient test response compaction. Often, a circuit under test contains sources of unknown values (X), uninitialized memories for instance. These X values propagate through the circuit and may spoil the response signatures. The standard way to overcome this problem is X-masking.
Outputs which carry an X value are usually determined by logic simulation. In this paper, we show that the amount of Xs is significantly overestimated, and in consequence outputs are overmasked, too. An efficient way for the exact computation of output Xs is presented for the first time. The resulting X-masking promises significant gains with respect to test time, test volume and fault coverage.
BibTeX:
@inproceedings{ElmKW2010,
  author = {Elm, Melanie and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{On Determining the Real Output Xs by SAT-Based Reasoning}},
  booktitle = {Fault Tolerant Computing Workshop (FTC Kenkyuukai)},
  year = {2010},
  keywords = {X-Masking},
  abstract = {Embedded testing, built-in self-test and methods for test compression rely on efficient test response compaction. Often, a circuit under test contains sources of unknown values (X), uninitialized memories for instance. These X values propagate through the circuit and may spoil the response signatures. The standard way to overcome this problem is X-masking.
Outputs which carry an X value are usually determined by logic simulation. In this paper, we show that the amount of Xs is significantly overestimated, and in consequence outputs are overmasked, too. An efficient way for the exact computation of output Xs is presented for the first time. The resulting X-masking promises significant gains with respect to test time, test volume and fault coverage.} }
3. Effiziente Fehlersimulation auf Many-Core-Architekturen
Kochte, M.A., Schaal, M., Wunderlich, H.-J. and Zöllin, C.
22nd ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'10), Paderborn, Germany, 28 February-2 March 2010
2010
 
BibTeX:
@inproceedings{KochtSWZ2010,
  author = {Kochte, Michael A. and Schaal, Marcel and Wunderlich, Hans-Joachim and Zöllin, Christian},
  title = {{Effiziente Fehlersimulation auf Many-Core-Architekturen}},
  booktitle = {22nd ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'10)},
  year = {2010}
}
2. Modellierung der Testinfrastruktur auf der Transaktionsebene
Kochte, M.A., Zöllin, C., Imhof, M.E., Salimi Khaligh, R., Radetzki, M., Wunderlich, H.-J., Di Carlo, S. and Prinetto, P.
21th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'09), Bremen, Germany, 15-17 February 2009, pp. 61-66
2009
 
Keywords: Reliability; Testing; Fault-Tolerance; CR B.8.1
Abstract: Dieser Artikel stellt eine Methode vor, den Entwurfsraum beim prüfgerechten Entwurf (engl. Design-for-Test, DfT) zu untersuchen und Teststrategien und Testschedules zu validieren. Alle Teile der Testinfrastruktur, wie etwa die Testeranbindung (Test Access Mechanisms), die Testwrapper, die Testdatenkompression sowie die entsprechenden Steuerwerke werden auf Transaktionsebenenmodelle (TLMs) abgebildet. Die kommunikationsbezogene Sicht der TLMs eignet sich besonders, da viele Aspekte des Tests die Übertragung großer Mengen an Teststimuli und -antworten erfordern. An einer Fallstudie wird der Einsatz von TLMs in frühen Entwurfsphasen erläutert. Der vorgestellte Ansatz hat wesentlich höhere Simulationseffizienz als Ansätze auf Register-Transfer- und Gatterebene.
BibTeX:
@inproceedings{KochtZISRWDP2009,
  author = {Kochte, Michael A. and Zöllin, Christian and Imhof, Michael E. and Salimi Khaligh, Rauf and Radetzki, Martin and Wunderlich, Hans-Joachim and Di Carlo, Stefano and Prinetto, Paolo},
  title = {{Modellierung der Testinfrastruktur auf der Transaktionsebene}},
  booktitle = {21th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'09)},
  year = {2009},
  pages = {61--66},
  keywords = {Reliability; Testing; Fault-Tolerance; CR B.8.1},
  abstract = {Dieser Artikel stellt eine Methode vor, den Entwurfsraum beim prüfgerechten Entwurf (engl. Design-for-Test, DfT) zu untersuchen und Teststrategien und Testschedules zu validieren. Alle Teile der Testinfrastruktur, wie etwa die Testeranbindung (Test Access Mechanisms), die Testwrapper, die Testdatenkompression sowie die entsprechenden Steuerwerke werden auf Transaktionsebenenmodelle (TLMs) abgebildet. Die kommunikationsbezogene Sicht der TLMs eignet sich besonders, da viele Aspekte des Tests die Übertragung großer Mengen an Teststimuli und -antworten erfordern. An einer Fallstudie wird der Einsatz von TLMs in frühen Entwurfsphasen erläutert. Der vorgestellte Ansatz hat wesentlich höhere Simulationseffizienz als Ansätze auf Register-Transfer- und Gatterebene.}
}
1. On the Reliability Modeling of Embedded Hardware-Software Systems
Kochte, M.A., Baranowski, R. and Wunderlich, H.-J.
1st IEEE Workshop on Design for Reliability and Variability (DRV'08), Santa Clara, California, USA, 30-31 October 2008
2008
 
Keywords: Reliability; Testing; Fault-Tolerance; CR B.8.1
BibTeX:
@inproceedings{KochtBW2008,
  author = {Kochte, Michael A. and Baranowski, Rafal and Wunderlich, Hans-Joachim},
  title = {{On the Reliability Modeling of Embedded Hardware-Software Systems}},
  booktitle = {1st IEEE Workshop on Design for Reliability and Variability (DRV'08)},
  year = {2008},
  keywords = {Reliability; Testing; Fault-Tolerance; CR B.8.1}
}
Created by JabRef on 13/06/2017.

Professional Activities

  • Reviewer for IEEE Transactions on VLSI Systems, IEEE Transactions on Computer Aided Design, IEEE International Test Conference
  • Program committee member of the IEEE Workshop of RTL and High Level Testing (WRTLT), since 2012
  • Program committee member of the IEEE European Test Symposium (ETS), since 2016
  • Program committee member of the GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen Workshop (TuZ), since 2016


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