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Laura Rodríguez Gómez

Name:

Dipl.-Inf. Laura Rodríguez Gómez

Adresse:

Universität Stuttgart

Institut für Technische Informatik

Pfaffenwaldring 47

70569 Stuttgart

Raum:

3.174

Sprechstunde:

Mittwoch, 10:00 - 11:00

Telefon:

+49 - 711 - 685 - 88276

Fax:

+49 - 711 - 685 - 88288

Mail:

laura.rodriguez@iti.uni-stuttgart.de

Laufende Projekte

SHIVA: Sichere Hardware in der Informationsverarbeitung

Projektseite: SHIVA: Sichere Hardware in der Informationsverarbeitung

Das Projekt „SHIVA: Sichere Hardware in der Informationsverarbeitung“, koordiniert von Prof. Dr. Wunderlich (Institut für Technische Informatik), erforscht Entwurfs- und Verifikationsmethoden zur Steigerung der Sicherheit mikroelektronischer Hardware, beispielsweise aus der Automobilelektronik, der Medizintechnik oder auch der Fertigungstechnik. Es soll damit der Ausschluss einer Manipulation des Systems, der Ausschluss der Beobachtung interner Daten, verwendeter Verfahren und Prozesse und der Schutz des geistigen Eigentums an der Hardware garantiert werden.

seit 02.2016,    

Diana: BMBF Projekt: Durchgängige Diagnosefähigkeit für Elektroniksysteme im Automobil

Projektseite: BMBF Projekt: Durchgängige Diagnosefähigkeit für Elektroniksysteme im Automobil

Gemeinsam werden AUDI AG, Continental AG, Infineon Technologies AG und ZMD AG erforschen, wie sich die Analyse- und Diagnosefähigkeiten von elektronischen Steuergeräten im Fahrzeug verbessern lassen. Unter der Leitung von Infineon arbeiten die vier Partner bis 2013 daran, wie eine gezielte Fehlererkennung und damit schnellere Fehlerbehebung beim Automobilhersteller bzw. in der Werkstatt möglich sind. DIANA steht für "Durchgängige Diagnosefähigkeit in Halbleiterbauelementen und übergeordneten Systemen zur Analyse von permanenten und sporadischen Fehlern im Gesamtsystem Automobil". Die Projektpartner werden dabei von zahlreichen Forschungseinrichtungen und Universitäten unterstützt: dem Fraunhofer-Institut für Integrierte Schaltungen Dresden, der Universität der Bundeswehr München und den Universitäten Cottbus, Erlangen-Nürnberg und Stuttgart.

07.2010 - 07.2013, BMBF-Projekt    

INTESYS: Modellbasierte Testdatenerzeugung zur effizienten Prüfung integrierter Hardware-/Softwaresysteme

Projektseite: Modellbasierte Testdatenerzeugung zur effizienten Prüfung integrierter Hardware-/Softwaresysteme

Funktionen in eingebetteten Systemen werden heutzutage immer häufiger durch integrierte Hard- ware-/Softwaresysteme realisiert, insbesondere ist dies auch bei Prozessautomatisierungssystemen zu beobachten. Merkmal dieser Hardware-/Softwaresysteme ist die enge Kopplung mit technischen Prozessen, wie etwa in den Steuerungen und Regelungen eines Kraftfahrzeugs, die eine zeitabhängige und diskret-kontinuierliche Dynamik aufweisen. Die Prüfung der korrekten Funktionalität des Entwurfs als auch des gefertigten Systems macht aufgrund der hohen Komplexität einen hohen Anteil der Gesamtkosten aus. Es wird daher ein effizientes Vorgehen zur gemeinsamen Prüfung von Hardware und Software dieser eingebetteten Systeme benötigt, das die einzelnen Aspekte Validierung, Debug, Diagnose und Test in sich vereint. Dies beinhaltet die automatisierte Ermittlung von Testdaten, welche Fehler zügig aufdecken und gleichzeitig eine hohe Produktqualität sicherstellen.
Modellbasierte und modellgetriebene Entwicklungs- und Testverfahren gewinnen sowohl in der Forschung als auch in der industriellen Praxis an Bedeutung, da sie die schrittweise Entwicklung von den Anforderungen bis hin zur Implementierung systematisieren. Durch Nutzung von Modellen, welche die Funktionen integrierter Hardware-/Softwaresysteme beschreiben, wird eine höhere Effizienz der Prüfung angestrebt. Wesentliche Ziele des Forschungsvorhabens sind die Testdaten- generierung für Funktion und Struktur aus einem Systemmodell eingebetteter Hardware-/Software- systeme sowie die automatische Auswertung und Fehlerdiagnose. Dies stellt eine Herausforderung dar, welche bis heute nicht zufrieden stellend gelöst werden konnte.

10.2010 - 09.2013, DFG-Projekt: WU 245/9-1    

Publications

Journal and Conference Proceedings
Matching entries: 0
settings...
5. Specification and Verification of Security in Reconfigurable Scan Networks
Kochte, M.A., Sauer, M., Rodríguez Gómez, L., Raiola, P., Becker, B. and Wunderlich, H.-J.
Proceedings of the 22nd IEEE European Test Symposium (ETS'17), Limassol, Cyprus, 22-26 May 2017, pp. 1-6
2017
DOI PDF 
Keywords: Keywords-Access Control, On-Chip Infrastructure, Reconfigurable Scan Network, Verification, Side-Channel Attack, IEEE Std 1687, IJTAG, Hardware Security
Abstract: A large amount of on-chip infrastructure, such as design-for-test, debug, monitoring, or calibration, is required for the efficient manufacturing, debug, and operation of complex hardware systems. The access to such infrastructure poses severe system safety and security threats since it may constitute a side-channel exposing internal state, sensitive data, or IP to attackers. Reconfigurable scan networks (RSNs) have been proposed as a scalable and flexible scan-based access mechanism to on-chip infrastructure. The increasing number and variety of integrated infrastructure as well as diverse access constraints over the system lifetime demand for systematic methods for the specification and formal verification of access protection and security properties in RSNs. This work presents a novel method to specify and verify fine-grained access permissions and restrictions to instruments attached to an RSN. The permissions and restrictions are transformed into predicates that are added to a formal model of a given RSN to prove which access properties hold or do not hold.
BibTeX:
@inproceedings{KochtSRRBW2017,
  author = {Kochte, Michael A. and Sauer, Matthias and Rodríguez Gómez, Laura and Raiola, Pascal and Becker, Bernd and Wunderlich, Hans-Joachim},
  title = {{Specification and Verification of Security in Reconfigurable Scan Networks}},
  booktitle = {Proceedings of the 22nd IEEE European Test Symposium (ETS'17)},
  year = {2017},
  pages = {1--6},
  keywords = {Keywords-Access Control, On-Chip Infrastructure, Reconfigurable Scan Network, Verification, Side-Channel Attack, IEEE Std 1687, IJTAG, Hardware Security},
  abstract = {A large amount of on-chip infrastructure, such as design-for-test, debug, monitoring, or calibration, is required for the efficient manufacturing, debug, and operation of complex hardware systems. The access to such infrastructure poses severe system safety and security threats since it may constitute a side-channel exposing internal state, sensitive data, or IP to attackers. Reconfigurable scan networks (RSNs) have been proposed as a scalable and flexible scan-based access mechanism to on-chip infrastructure. The increasing number and variety of integrated infrastructure as well as diverse access constraints over the system lifetime demand for systematic methods for the specification and formal verification of access protection and security properties in RSNs. This work presents a novel method to specify and verify fine-grained access permissions and restrictions to instruments attached to an RSN. The permissions and restrictions are transformed into predicates that are added to a formal model of a given RSN to prove which access properties hold or do not hold.},
  doi = {http://dx.doi.org/10.1109/ETS.2017.7968247},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2017/ETS_KochtSRRBW2017.pdf}
}
4. A Neural-Network-Based Fault Classifier
Rodríguez Gómez, L. and Wunderlich, H.-J.
Proceedings of the 25th IEEE Asian Test Symposium (ATS'16), Hiroshima, Japan, 21-24 November 2016, pp. 144-149
2016
DOI PDF 
Keywords: Neural networks, machine learning, fault classification, diagnosis
Abstract: In order to reduce the number of defective parts and increase yield, especially in early stages of production, systematic defects must be identified and corrected as soon as possible. This paper presents a technique to move defect classification to the earliest phase of volume testing without any special diagnostic test patterns. A neural-network-based fault classifier is described, which is able to raise a warning, if the frequency of certain defect mechanisms increases. Only in this case more sophisticated diagnostic patterns or the even more expensive physical failure analysis have to be applied. The fault classification method presented here is able to extract underlying fault types with high confidence by identifying relevant features from the circuit topology and from logic simulation.
BibTeX:
@inproceedings{RodriW2016,
  author = {Rodríguez Gómez, Laura and Wunderlich, Hans-Joachim},
  title = {{A Neural-Network-Based Fault Classifier}},
  booktitle = {Proceedings of the 25th IEEE Asian Test Symposium (ATS'16)},
  year = {2016},
  pages = {144--149},
  keywords = {Neural networks, machine learning, fault classification, diagnosis},
  abstract = {In order to reduce the number of defective parts and increase yield, especially in early stages of production, systematic defects must be identified and corrected as soon as possible. This paper presents a technique to move defect classification to the earliest phase of volume testing without any special diagnostic test patterns. A neural-network-based fault classifier is described, which is able to raise a warning, if the frequency of certain defect mechanisms increases. Only in this case more sophisticated diagnostic patterns or the even more expensive physical failure analysis have to be applied. The fault classification method presented here is able to extract underlying fault types with high confidence by identifying relevant features from the circuit topology and from logic simulation.},
  doi = {http://dx.doi.org/10.1109/ATS.2016.46},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2016/ATS_RodriW2016.pdf}
}
3. Adaptive Bayesian Diagnosis of Intermittent Faults
Rodríguez Gómez, L., Cook, A., Indlekofer, T., Hellebrand, S. and Wunderlich, H.-J.
Journal of Electronic Testing: Theory and Applications (JETTA)
Vol. 30(5), 30 September 2014, pp. 527-540
2014
DOI URL PDF 
Keywords: Built-In Self-Test, Built-in diagnosis, Transient faults, Intermittent faults, Bayesian diagnosis
Abstract: With increasing transient error rates, distinguishing intermittent and transient faults is especially challenging. In addition to particle strikes relatively high transient error rates are observed in architectures for opportunistic computing and in technologies under high variations. This paper presents a method to classify faults into permanent, intermittent and transient faults based on some intermediate signatures during embedded test or built-in self-test.
Permanent faults are easily determined by repeating test sessions. Intermittent and transient faults can be identified by the amount of failing test sessions in many cases. For the remaining faults, a Bayesian classification technique has been developed which is applicable to large digital circuits. The combination of these methods is able to identify intermittent faults with a probability of more than 98 %.
BibTeX:
@article{RodriCIHW2014,
  author = {Rodríguez Gómez, Laura and Cook, Alejandro and Indlekofer, Thomas and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
  title = {{Adaptive Bayesian Diagnosis of Intermittent Faults}},
  journal = {Journal of Electronic Testing: Theory and Applications (JETTA)},
  year = {2014},
  volume = {30},
  number = {5},
  pages = {527--540},
  keywords = { Built-In Self-Test, Built-in diagnosis, Transient faults, Intermittent faults, Bayesian diagnosis },
  abstract = { With increasing transient error rates, distinguishing intermittent and transient faults is especially challenging. In addition to particle strikes relatively high transient error rates are observed in architectures for opportunistic computing and in technologies under high variations. This paper presents a method to classify faults into permanent, intermittent and transient faults based on some intermediate signatures during embedded test or built-in self-test.
Permanent faults are easily determined by repeating test sessions. Intermittent and transient faults can be identified by the amount of failing test sessions in many cases. For the remaining faults, a Bayesian classification technique has been developed which is applicable to large digital circuits. The combination of these methods is able to identify intermittent faults with a probability of more than 98 %.}, url = { http://link.springer.com/article/10.1007/s10836-014-5477-1 }, doi = {http://dx.doi.org/10.1007/s10836-014-5477-1}, file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/JETTA_RodriCIHW2014.pdf} }
2. Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures
Reimann, F., Glaß, M., Teich, J., Cook, A., Rodríguez Gómez, L., Ull, D., Wunderlich, H.-J., Abelein, U. and Engelke, P.
Proceedings of the 51st ACM/IEEE Design Automation Conference (DAC'14), San Francisco, California, USA, 1-5 June 2014, pp. 1-9
HiPEAC Paper Award
2014
DOI PDF 
Abstract: The constantly growing amount of semiconductors in automotive systems increases the number of possible defect mechanisms, and therefore raises also the effort to maintain a sufficient level of quality and reliability. A promising solution to this problem is the on-line application of structural tests in key components, typically ECUs. In this work, an approach for the optimized integration of both Software-Based Self-Tests (SBST) and Built-In Self-Tests (BIST) into E/E architectures is presented. The approach integrates the execution of the tests non-intrusively, i. e., it (a) does not affect functional applications and (b) does not require costly changes in the communication schedules or additional communication overhead. Via design space exploration, optimized implementations with respect to multiple conflicting objectives, i. e., monetary costs, safety, test quality, and required execution time are derived.
BibTeX:
@inproceedings{ReimaGTCRUWAE2014,
  author = {Reimann, Felix and Glaß, Michael and Teich, Jürgen and Cook, Alejandro and Rodríguez Gómez, Laura and Ull, Dominik and Wunderlich, Hans-Joachim and Abelein, Ulrich and Engelke, Piet},
  title = {{Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures}},
  booktitle = {Proceedings of the 51st ACM/IEEE Design Automation Conference (DAC'14)},
  year = {2014},
  pages = {1--9},
  abstract = {The constantly growing amount of semiconductors in automotive systems increases the number of possible defect mechanisms, and therefore raises also the effort to maintain a sufficient level of quality and reliability. A promising solution to this problem is the on-line application of structural tests in key components, typically ECUs. In this work, an approach for the optimized integration of both Software-Based Self-Tests (SBST) and Built-In Self-Tests (BIST) into E/E architectures is presented. The approach integrates the execution of the tests non-intrusively, i. e., it (a) does not affect functional applications and (b) does not require costly changes in the communication schedules or additional communication overhead. Via design space exploration, optimized implementations with respect to multiple conflicting objectives, i. e., monetary costs, safety, test quality, and required execution time are derived.},
  doi = {http://dx.doi.org/10.1145/2593069.2602971},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/DAC_ReimaGTCRUWAE2014.pdf}
}
1. Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures
Abelein, U., Cook, A., Engelke, P., Glaß, M., Reimann, F., Rodríguez Gómez, L., Russ, T., Teich, J., Ull, D. and Wunderlich, H.-J.
Proceedings of the Design, Automation and Test in Europe (DATE'14), Dresden, Germany, 24-28 March 2014
2014
DOI URL PDF 
Keywords: Automotive Structural Diagnosis, BIST
Abstract: With ever more complex automotive systems, the current approach of using functional tests to locate faulty components results in very long analysis procedures and poor diagnostic accuracy. Built-In Self-Test (BIST) offers a promising alternative to collect structural diagnostic information during E/E-architecture test. However, as the automotive industry is quite cost-driven, structural diagnosis shall not deteriorate traditional design objectives. With this goal in mind, the work at hand proposes a design space exploration to integrate structural diagnostic capabilities into an E/E-architecture design. The proposed integration is performed non-intrusively, i. e., the addition and execution of tests (a) does not affect any functional applications and (b) does not require any costly changes in the communication schedules.
BibTeX:
@inproceedings{AbeleCEGRRRTUW2014,
  author = {Abelein, Ulrich and Cook, Alejandro and Engelke, Piet and Glaß, Michael and Reimann, Felix and Rodríguez Gómez, Laura and Russ, Thomas and Teich, Jürgen and Ull, Dominik and Wunderlich, Hans-Joachim},
  title = {{Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures}},
  booktitle = {Proceedings of the Design, Automation and Test in Europe (DATE'14)},
  year = {2014},
  keywords = {Automotive Structural Diagnosis, BIST},
  abstract = {With ever more complex automotive systems, the current approach of using functional tests to locate faulty components results in very long analysis procedures and poor diagnostic accuracy. Built-In Self-Test (BIST) offers a promising alternative to collect structural diagnostic information during E/E-architecture test. However, as the automotive industry is quite cost-driven, structural diagnosis shall not deteriorate traditional design objectives. With this goal in mind, the work at hand proposes a design space exploration to integrate structural diagnostic capabilities into an E/E-architecture design. The proposed integration is performed non-intrusively, i. e., the addition and execution of tests (a) does not affect any functional applications and (b) does not require any costly changes in the communication schedules.},
  url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6800574},
  doi = {http://dx.doi.org/10.7873/DATE.2014.373},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/DATE_AbeleCEGRRRTUW2014.pdf}
}
Created by JabRef on 31/07/2017.
Workshop Contributions
Matching entries: 0
settings...
2. Quantifying Security in Reconfigurable Scan Networks
Rodríguez Gómez, L., Kochte, M.A., Atteya, A. and Wunderlich, H.-J.
2nd International Test Standards Application Workshop (TESTA), co-located with IEEE European Test Symposium, Limassol, Cyprus, 25-26 May 2017
2017
 
BibTeX:
@inproceedings{RodriKAW2017,
  author = {Rodríguez Gómez, Laura and Kochte, Michael A. and Atteya, Ahmed and Wunderlich, Hans-Joachim},
  title = {{Quantifying Security in Reconfigurable Scan Networks}},
  booktitle = {2nd International Test Standards Application Workshop (TESTA), co-located with IEEE European Test Symposium},
  year = {2017}
}
1. Adaptive Test and Diagnosis of Intermittent Faults
Cook, A., Rodriguez, L., Hellebrand, S., Indlekofer, T. and Wunderlich, H.-J.
14th Latin American Test Workshop (LATW'13), Cordoba, Argentina, 3-5 April 2013
2013
 
BibTeX:
@inproceedings{CookRHIW2013,
  author = {Cook, Alejandro and Rodriguez, Laura and Hellebrand, Sybille and Indlekofer, Thomas and Wunderlich, Hans-Joachim},
  title = {{Adaptive Test and Diagnosis of Intermittent Faults}},
  booktitle = {14th Latin American Test Workshop (LATW'13)},
  year = {2013}
}
Created by JabRef on 31/07/2017.

Lehre

Fachpraktika und Übungen

Master- / Bachelorarbeiten und Software Praktika

     Laufende Themen
  • Master Thesis: Evaluation of the fault tolerance of Artificial Neural Networks and investigation of their precision requirements
    Nika Hamidi
    10.2016 - 04.2017
     Abgeschlossene Themen