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Eric Schneider

Name:

Dipl.-Inf. Eric Schneider

Address:

University of Stuttgart

Institute of Computer Architecture and Computer Engineering

Pfaffenwaldring 47

D-70569 Stuttgart

Room:

2.171

Phone:

+49-711-685-88-370

E-Mail:

schneiec at iti dot uni-stuttgart dot de

Public key:

545E 43FB 704F 0E35 84BD 802A F635 EBEF 9FCE 2CEF

Short-Bio

Eric Schneider received the diploma degree in computer science (Dipl.-Inf.) from the University of Stuttgart, Germany, in 2012. There he joined the Institute of Computer Architecture and Computer Engineering (ITI), where he is currently working towards his Ph.D. His research interests include accelerated circuit simulation on Graphics Processing Units (GPUs), circuit test and diagnosis. He is a Student Member of the IEEE since 2014.

Projects

Contributions to ongoing and completed projects:

HiPS: High-Performance Simulation for High Quality Small Delay Fault Testing

Projektseite: High-Performance Simulation (HiPS) for High Quality Small Delay Fault Testing

Projektpartner:  Department of Creative Informatics - Kyushu Institute of Technology

This project aims to find novel abstraction and algorithm mapping methods to allow highly accurate timing and NFP-aware simulation of multi-million gate circuits on data-parallel architectures such as graphics processing units (GPUs). The expected dramatic speedup compared to the existing state-of-the-art allows fault simulation of millions of faults and thousands of patterns. The increased accuracy of the simulation results allow to optimize test patterns w.r.t. test power and small delay defect coverage in presence of power noise, clock skew or even circuit variations.

01.2015 - 12.2016, DAAD/JSPS PPP Japan Projekt: #57155440  

PARSIVAL: Parallel High-Throughput Simulations for Efficient Nanoelectronic Design and Test Validation

Projektseite: PARSIVAL: Parallel High-Throughput Simulations for Efficient Nanoelectronic Design and Test Validation

Design and test validation is one of the most important and complex tasks within modern semi-conductor product development cycles. The design validation process analyzes and assesses a developed design with respect to certain validation targets to ensure its compliance with given specifications and customer requirements. Test validation evaluates the defect coverage obtained by certain test strategies and assesses the quality of the products tested and delivered. The validation targets include both, functional and non-functional properties, as well as the complex interactions and interdependencies between them. The validation means rely mainly on compute-intensive simulations which require more and more highly parallel hardware acceleration.

In this project novel methods for versatile simulation-based VLSI design and test validation on high throughput data-parallel architectures will be developed, which enable a wide range of important state-of-the-art validation tasks for large circuits. In general, due to the nature of the design validation processes and due to the massive amount of data involved, parallelism and throughput-optimization are the keys for making design validation feasible for future industrial-sized designs. The main focus and key features lie in the structure of the simulation model, the abstraction level and the used algorithms, as well as their parallelization on data-parallel architectures. The simulation algorithms should be kept simple to run fast, yet accurate enough to produce acceptable and valuable data for cross-layer validation of complex digital systems.

seit 10.2014, DFG-Projekt: WU 245/16-1    

OTERA: Online Test Strategies for Reliable Reconfigurable Architectures

Projektseite: Online Test Strategies for Reliable Reconfigurable Architectures

Dynamisch rekonfigurierbare Architekturen ermöglichen eine signifikante Beschleunigung verschiedener Anwendungen durch die Anpassung und Optimierung der Struktur des Systems zur Laufzeit. Permanente und transiente Fehler bedrohen die zuverlässigen Betrieb einer solchen Architektur. Dieses Projekt zielt darauf ab, die Zuverlässigkeit von Laufzeit-rekonfigurierbaren Systemen durch eine neuartige System- Level-Strategie für Online-Tests und Online-Anpassung an Fehler zu erhöhen. Dies wird erreicht durch (a) Scheduling, so dass Tests für rekonfigurierbare Ressourcen mit minimaler Auswirkung auf die Leistung ausgeführt werden, (b) Ressourcen-Management, so dass teilweise fehlerhafte Ressourcen für Komponenten verwendet werden, die den fehlerhaften Teil nicht verwenden, und (c) Online-Uberwachung und Error-Checking. Um eine zuverlässige Rekonfiguration zur Laufzeit zu gewährleisten, wird jeder Rekonfigurationsprozess durch eine neuartige und effiziente Kombination von Online-Struktur- und Funktionstests gründlich getestet. Im Vergleich zu bisherigen Fehlertoleranzkonzepten vermeidet dieser Ansatz die hohen Hardwarekosten von struktureller Redundanz. Die eingesparten Ressourcen können zur weiteren Beschleunigung der Anwendungen verwendet werden. Dennoch deckt das vorgeschlagene Verfahren Fehler in den rekonfigurierbaren Ressourcen, der Anwendungslogik und Fehler im Rekonfigurationsprozess ab.

seit 10.2010, DFG-Projekt: WU 245/10-1, 10-2, 10-3   

REALTEST: Test und Zuverlässigkeit nanoelektronischer Systeme



Projektseite: Test und Zuverlässigkeit nanoelektronischer Systeme

Zukünftige nanoelektronische Schaltungen zeigen eine hohe Empfindlichkeit gegenüber sog. Soft Errors, die hier nicht nur die Speicherfelder betrifft, sondern insbesondere auch Speicherelemente in freier Logik (z.B. Flip-Flops). Eines der Ziele von Realtest ist die Entwicklung von robusten Registern für freie Logik die eine bessere Flächeneffizienz besitzen als existierende Ansätze.

01.2006 - 07.2013, DFG-Projekt: WU 245/5-1, 5-2    

Student Theses
  • Hochbeschleunigte IR-Drop Analyse  von integrierten Schaltungen
    (Bachelor Thesis - Nr. TBA)

    Hagemann, P.
    Mar. 1 - Sep. 1, 2017.
  • Inter-gate Fault Modeling for GPU-accelerated Fault Simulation
    (Master Thesis
    - Nr. 00731-005)
    Frosi, A.
    May 25 - Nov. 24, 2016.
  • Realistic Gate Model for efficient Timing Analysis of very deep submicron CMOS circuits
    (Master Thesis
    - Nr. 00731-001)
    Murali, D.

    Sep. 14, 2015 - Mar. 15, 2016.
  • Switching activity based estimation of IR-drop
    (Projekt INF)
    Hardes, D., Hagemann, P., Knabben, M.
    Feb. 5 - Aug. 7, 2015.
  • Adaptierung an Zeitverhalten-Variationen in rekonfigurierbaren Hardwarestrukturen
    (Bachelor Thesis - Nr. 179)

    Brandhofer, S.
    Oct. 20, 2014 - Apr. 20, 2015.
  • Analysis of Hardware-Accelerated Applications in Reconfigurable Network-on-a-Chip Based Systems
    (Projekt INF)
    Brandhofer, S., Göttlich, P., Lanksweirt, A.
    Jun. 1 - Dec. 1, 2014.
Current Topics

Publications

Journals and Conference Proceedings
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14. Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors
Holst, S., Schneider, E., Kawagoe, K., Kochte, M.A., Miyase, K., Wunderlich, H.-J., Kajihara, S. and Wen, X.
to appear in Proceedings of the IEEE International Test Conference (ITC'17), Fort Worth, Texas, USA, 31 October-2 November 2017
2017
 
BibTeX:
@inproceedings{HolstSKKMWKW2017,
  author = {Holst, Stefan and Schneider, Eric and Kawagoe, Koshi and Kochte, Michael A. and Miyase, Kohei and Wunderlich, Hans-Joachim and Kajihara, Seiji and Wen, Xiaoqing},
  title = {{Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors}},
  booktitle = {to appear in Proceedings of the IEEE International Test Conference (ITC'17)},
  year = {2017}
}
13. Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures
Zhang, H., Bauer, L., Kochte, M.A., Schneider, E., Wunderlich, H.-J. and Henkel, J.
IEEE Transactions on Computers
Vol. 66(6), 1 June 2017, pp. 957-970
2017
DOI PDF 
Keywords: Runtime reconfiguration, aging mitigation, fault-tolerance, resilience, graceful degradation, FPGA
Abstract: Runtime reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) allow area- and power-efficient acceleration of complex applications. However, being manufactured in latest semiconductor process technologies, FPGAs are increasingly prone to aging effects, which reduce the reliability and lifetime of such systems. Aging mitigation and fault tolerance techniques for the reconfigurable fabric become essential to realize dependable reconfigurable architectures. This article presents an accelerator diversification method that creates multiple configurations for runtime reconfigurable accelerators that are diversified in their usage of Configurable Logic Blocks (CLBs). In particular, it creates a minimal number of configurations such that all single-CLB and some multi-CLB faults can be tolerated. For each fault we ensure that there is at least one configuration that does not use that CLB.
Secondly, a novel runtime accelerator placement algorithm is presented that exploits the diversity in resource usage of these configurations to balance the stress imposed by executions of the accelerators on the reconfigurable fabric. By tracking the stress due to accelerator usage at runtime, the stress is balanced both within a reconfigurable region as well as over all reconfigurable regions of the system. The accelerator placement algorithm also considers faulty CLBs in the regions and selects the appropriate configuration such that the system maintains a high performance in presence of multiple permanent faults.
Experimental results demonstrate that our methods deliver up to 3.7x higher performance in presence of faults at marginal runtime costs and 1.6x higher MTTF than state-of-the-art aging mitigation methods.
BibTeX:
@article{ZhangBKSWH2017,
  author = {Zhang, Hongyan and Bauer, Lars and Kochte, Michael A. and Schneider, Eric and Wunderlich, Hans-Joachim and Henkel, Jörg},
  title = {{Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures}},
  journal = {IEEE Transactions on Computers},
  year = {2017},
  volume = {66},
  number = {6},
  pages = {957--970},
  keywords = {Runtime reconfiguration, aging mitigation, fault-tolerance, resilience, graceful degradation, FPGA},
  abstract = {Runtime reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) allow area- and power-efficient acceleration of complex applications. However, being manufactured in latest semiconductor process technologies, FPGAs are increasingly prone to aging effects, which reduce the reliability and lifetime of such systems. Aging mitigation and fault tolerance techniques for the reconfigurable fabric become essential to realize dependable reconfigurable architectures. This article presents an accelerator diversification method that creates multiple configurations for runtime reconfigurable accelerators that are diversified in their usage of Configurable Logic Blocks (CLBs). In particular, it creates a minimal number of configurations such that all single-CLB and some multi-CLB faults can be tolerated. For each fault we ensure that there is at least one configuration that does not use that CLB.
Secondly, a novel runtime accelerator placement algorithm is presented that exploits the diversity in resource usage of these configurations to balance the stress imposed by executions of the accelerators on the reconfigurable fabric. By tracking the stress due to accelerator usage at runtime, the stress is balanced both within a reconfigurable region as well as over all reconfigurable regions of the system. The accelerator placement algorithm also considers faulty CLBs in the regions and selects the appropriate configuration such that the system maintains a high performance in presence of multiple permanent faults.
Experimental results demonstrate that our methods deliver up to 3.7x higher performance in presence of faults at marginal runtime costs and 1.6x higher MTTF than state-of-the-art aging mitigation methods. }, doi = {http://dx.doi.org/10.1109/TC.2016.2616405}, file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2017/TC_ZhangBKSWH2017.pdf} }
12. GPU-Accelerated Simulation of Small Delay Faults
Schneider, E., Kochte, M.A., Holst, S., Wen, X. and Wunderlich, H.-J.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
Vol. 36(5), May 2017, pp. 829-841
2017
DOI PDF 
Keywords: Circuit faults, Computational modeling, Delays, Instruction sets, Integrated circuit modeling, Logic gates, Fault simulation, graphics processing unit (GPU), parallel, process variation, small gate delay faults, timing-accurate, waveform
Abstract: Delay fault simulation is an essential task during test pattern generation and reliability assessment of electronic circuits. With the high sensitivity of current nano-scale designs towards even smallest delay deviations, the simulation of small gate delay faults has become extremely important. Since these faults have a subtle impact on the timing behavior, traditional fault simulation approaches based on abstract timing models are not sufficient. Furthermore, the detection of these faults is compromised by the ubiquitous variations in the manufacturing processes, which causes the actual fault coverage to vary from circuit instance to circuit instance, and makes the use of timing accurate methods mandatory. However, the application of timing accurate techniques quickly becomes infeasible for larger designs due to excessive computational requirements. In this work, we present a method for fast and waveformaccurate simulation of small delay faults on graphics processing units with exceptional computational performance. By exploiting multiple dimensions of parallelism from gates, faults, waveforms and circuit instances, the proposed approach allows for timing-accurate and exhaustive small delay fault simulation under process variation for designs with millions of gates.
BibTeX:
@article{SchneKHWW2016,
  author = {Schneider, Eric and Kochte, Michael A. and Holst, Stefan and Wen, Xiaoqing and Wunderlich, Hans-Joachim},
  title = {{GPU-Accelerated Simulation of Small Delay Faults}},
  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)},
  year = {2017},
  volume = {36},
  number = {5},
  pages = {829--841},
  keywords = {Circuit faults, Computational modeling, Delays, Instruction sets, Integrated circuit modeling, Logic gates, Fault simulation, graphics processing unit (GPU), parallel, process variation, small gate delay faults, timing-accurate, waveform},
  abstract = {Delay fault simulation is an essential task during test pattern generation and reliability assessment of electronic circuits. With the high sensitivity of current nano-scale designs towards even smallest delay deviations, the simulation of small gate delay faults has become extremely important. Since these faults have a subtle impact on the timing behavior, traditional fault simulation approaches based on abstract timing models are not sufficient. Furthermore, the detection of these faults is compromised by the ubiquitous variations in the manufacturing processes, which causes the actual fault coverage to vary from circuit instance to circuit instance, and makes the use of timing accurate methods mandatory. However, the application of timing accurate techniques quickly becomes infeasible for larger designs due to excessive computational requirements. In this work, we present a method for fast and waveformaccurate simulation of small delay faults on graphics processing units with exceptional computational performance. By exploiting multiple dimensions of parallelism from gates, faults, waveforms and circuit instances, the proposed approach allows for timing-accurate and exhaustive small delay fault simulation under process variation for designs with millions of gates.},
  doi = {http://dx.doi.org/10.1109/TCAD.2016.2598560},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2016/TCAD_SchneKHWW2016.pdf}
}
11. Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test
Holst, S., Schneider, E., Wen, X., Kajihara, S., Yamato, Y., Wunderlich, H.-J. and Kochte, M.A.
Proceedings of the 25th IEEE Asian Test Symposium (ATS'16), Hiroshima, Japan, 21-24 November 2016, pp. 19-24
2016
DOI PDF 
Abstract: IR-drop induced false capture failures and test clock stretch are severe problems in at-speed scan testing. We propose a new method to efficiently and accurately identify these problems. For the first time, our approach considers the additional dynamic power caused by glitches, the spatial and temporal distribution of all toggles, and their impact on both logic paths and the clock tree without time-consuming electrical simulations.
BibTeX:
@inproceedings{HolstSWKYWK2016,
  author = {Holst, Stefan and Schneider, Eric and Wen, Xiaoqing and Kajihara, Seiji and Yamato, Yuta and Wunderlich, Hans-Joachim and Kochte, Michael A.},
  title = {{Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test}},
  booktitle = {Proceedings of the 25th IEEE Asian Test Symposium (ATS'16)},
  year = {2016},
  pages = {19--24},
  abstract = {IR-drop induced false capture failures and test clock stretch are severe problems in at-speed scan testing. We propose a new method to efficiently and accurately identify these problems. For the first time, our approach considers the additional dynamic power caused by glitches, the spatial and temporal distribution of all toggles, and their impact on both logic paths and the clock tree without time-consuming electrical simulations.},
  doi = {http://dx.doi.org/10.1109/ATS.2016.49},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2016/ATS_HolstSWKYWK2016.pdf}
}
10. High-Throughput Transistor-Level Fault Simulation on GPUs
Schneider, E. and Wunderlich, H.-J.
Proceedings of the 25th IEEE Asian Test Symposium (ATS'16), Hiroshima, Japan, 21-24 November 2016, pp. 150-155
2016
DOI PDF 
Keywords: fault simulation; transistor level; switch level; GPUs
Abstract: Deviations in the first-order parameters of CMOS cells can lead to severe errors in the functional and time domain. With increasing sensitivity of these parameters to manufacturing defects and variation, parametric and parasitic-aware fault simulation is becoming crucial in order to support test pattern generation. Traditional approaches based on gate-level models are not sufficient to represent and capture the impact of deviations in these parameters in either an efficient or accurate manner. Evaluation at electrical level, on the other hand, severely lacks execution speed and quickly becomes inapplicable to larger designs due to high computational demands. This work presents a novel fault simulation approach considering first-order parameters in CMOS circuits to explicitly capture CMOS-specific behavior in the functional and time domain with transistor granularity. The approach utilizes massive parallelization in order to achieve high-throughput acceleration on Graphics Processing Units (GPUs) by exploiting parallelism of cells, stimuli and faults. Despite the more precise level of abstraction, the simulator is able to process designs with millions of gates and even outperforms conventional simulation at logic level in terms of modeling accuracy and simulation speed.
BibTeX:
@inproceedings{SchneW2016,
  author = {Schneider, Eric and Wunderlich, Hans-Joachim},
  title = {{High-Throughput Transistor-Level Fault Simulation on GPUs}},
  booktitle = {Proceedings of the 25th IEEE Asian Test Symposium (ATS'16)},
  year = {2016},
  pages = {150--155},
  keywords = {fault simulation; transistor level; switch level; GPUs},
  abstract = {Deviations in the first-order parameters of CMOS cells can lead to severe errors in the functional and time domain. With increasing sensitivity of these parameters to manufacturing defects and variation, parametric and parasitic-aware fault simulation is becoming crucial in order to support test pattern generation. Traditional approaches based on gate-level models are not sufficient to represent and capture the impact of deviations in these parameters in either an efficient or accurate manner. Evaluation at electrical level, on the other hand, severely lacks execution speed and quickly becomes inapplicable to larger designs due to high computational demands. This work presents a novel fault simulation approach considering first-order parameters in CMOS circuits to explicitly capture CMOS-specific behavior in the functional and time domain with transistor granularity. The approach utilizes massive parallelization in order to achieve high-throughput acceleration on Graphics Processing Units (GPUs) by exploiting parallelism of cells, stimuli and faults. Despite the more precise level of abstraction, the simulator is able to process designs with millions of gates and even outperforms conventional simulation at logic level in terms of modeling accuracy and simulation speed.},
  doi = {http://dx.doi.org/10.1109/ATS.2016.9},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2016/ATS_SchneW2016.pdf}
}
9. Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch
Asada, K., Wen, X., Holst, S., Miyase, K., Kajihara, S., Kochte, M.A., Schneider, E., Wunderlich, H.-J. and Qian, J.
Proceedings of the 24th IEEE Asian Test Symposium (ATS'15), Mumbai, India, 22-25 November 2015, pp. 103-108
ATS 2015 Best Paper Award
2015
DOI PDF 
Keywords: launch switching activity, IR-drop, logic path, clock path, false capture failure, test clock stretch, X-filling
Abstract: IR-drop induced by launch switching activity (LSA) in capture mode during at-speed scan testing increases delay along not only logic paths (LPs) but also clock paths (CPs). Excessive extra delay along LPs compromises test yields due to false capture failures, while excessive extra delay along CPs compromises test quality due to test clock stretch. This paper is the first to mitigate the impact of LSA on both LPs and CPs with a novel LCPA (Logic/Clock-Path-Aware) at-speed scan test generation scheme, featuring (1) a new metric for assessing the risk of false capture failures based on the amount of LSA around both LPs and CPs, (2) a procedure for avoiding false capture failures by reducing LSA around LPs or masking uncertain test responses, and (3) a procedure for reducing test clock stretch by reducing LSA around CPs. Experimental results demonstrate the effectiveness of the LCPA scheme in improving test yields and test quality.
BibTeX:
@inproceedings{AsadaWHMKKSWQ2015,
  author = {Asada, Koji and Wen, Xiaoqing and Holst, Stefan and Miyase, Kohei and Kajihara, Seiji and Kochte, Michael A. and Schneider, Eric and Wunderlich, Hans-Joachim and Qian, Jun},
  title = {{Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch}},
  booktitle = {Proceedings of the 24th IEEE Asian Test Symposium (ATS'15)},
  year = {2015},
  pages = {103-108},
  keywords = { launch switching activity, IR-drop, logic path, clock path, false capture failure, test clock stretch, X-filling },
  abstract = {IR-drop induced by launch switching activity (LSA) in capture mode during at-speed scan testing increases delay along not only logic paths (LPs) but also clock paths (CPs). Excessive extra delay along LPs compromises test yields due to false capture failures, while excessive extra delay along CPs compromises test quality due to test clock stretch. This paper is the first to mitigate the impact of LSA on both LPs and CPs with a novel LCPA (Logic/Clock-Path-Aware) at-speed scan test generation scheme, featuring (1) a new metric for assessing the risk of false capture failures based on the amount of LSA around both LPs and CPs, (2) a procedure for avoiding false capture failures by reducing LSA around LPs or masking uncertain test responses, and (3) a procedure for reducing test clock stretch by reducing LSA around CPs. Experimental results demonstrate the effectiveness of the LCPA scheme in improving test yields and test quality.},
  doi = {http://dx.doi.org/10.1109/ATS.2015.25},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/ATS_AsadaWHMKKSWQ2015.pdf}
}
8. Optimized Selection of Frequencies for Faster-Than-at-Speed Test
Kampmann, M., Kochte, M.A., Schneider, E., Indlekofer, T., Hellebrand, S. and Wunderlich, H.-J.
Proceedings of the 24th IEEE Asian Test Symposium (ATS'15), Mumbai, India, 22-25 November 2015, pp. 109-114
2015
DOI PDF 
Keywords: BIST, small delay defects, delay test, faster-than-at-speed-test
Abstract: Small gate delay faults (SDFs) are not detectable at-speed, if they can only be propagated along short paths. These hidden delay faults (HDFs) do not influence the circuit’s behavior initially, but they may indicate design marginalities leading to early-life failures, and therefore they cannot be neglected. HDFs can be detected by faster-than-at-speed test (FAST), where typically several different frequencies are used to maximize the coverage. A given set of test patterns P potentially detects a HDF if it contains a test pattern sensitizing a path through the fault site, and the efficiency of FAST can be measured as the ratio of actually detected HDFs to potentially detected HDFs. The paper at hand targets maximum test efficiency with a minimum number of frequencies. The procedure starts with a test set for transition delay faults and a set of preselected equidistant frequencies. Timing-accurate simulation of this initial setup identifies the hard-to-detect faults, which are then targeted by a more complex timing-aware ATPG procedure. For the yet undetected HDFs, a minimum number of frequencies are determined using an efficient hypergraph algorithm. Experimental results show that with this approach, the number of test frequencies required for maximum test efficiency can be reduced considerably. Furthermore, test set inflation is limited as timing-aware ATPG is only used for a small subset of HDFs.
BibTeX:
@inproceedings{KampmKSIHW2015,
  author = {Kampmann, Matthias and Kochte, Michael A. and Schneider, Eric and Indlekofer, Thomas and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
  title = {{Optimized Selection of Frequencies for Faster-Than-at-Speed Test}},
  booktitle = {Proceedings of the 24th IEEE Asian Test Symposium (ATS'15)},
  year = {2015},
  pages = {109-114},
  keywords = {BIST, small delay defects, delay test, faster-than-at-speed-test},
  abstract = {Small gate delay faults (SDFs) are not detectable at-speed, if they can only be propagated along short paths. These hidden delay faults (HDFs) do not influence the circuit’s behavior initially, but they may indicate design marginalities leading to early-life failures, and therefore they cannot be neglected. HDFs can be detected by faster-than-at-speed test (FAST), where typically several different frequencies are used to maximize the coverage. A given set of test patterns P potentially detects a HDF if it contains a test pattern sensitizing a path through the fault site, and the efficiency of FAST can be measured as the ratio of actually detected HDFs to potentially detected HDFs. The paper at hand targets maximum test efficiency with a minimum number of frequencies. The procedure starts with a test set for transition delay faults and a set of preselected equidistant frequencies. Timing-accurate simulation of this initial setup identifies the hard-to-detect faults, which are then targeted by a more complex timing-aware ATPG procedure. For the yet undetected HDFs, a minimum number of frequencies are determined using an efficient hypergraph algorithm. Experimental results show that with this approach, the number of test frequencies required for maximum test efficiency can be reduced considerably. Furthermore, test set inflation is limited as timing-aware ATPG is only used for a small subset of HDFs.},
  doi = {http://dx.doi.org/10.1109/ATS.2015.26},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/ATS_KampmKSIHW2015.pdf}
}
7. STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures
Zhang, H., Kochte, M.A., Schneider, E., Bauer, L., Wunderlich, H.-J. and Henkel, J.
Proceedings of the 34th IEEE/ACM International Conference on Computer-Aided Design (ICCAD'15), Austin, Texas, USA, 2-6 November 2015, pp. 38-45
2015
URL PDF 
Abstract: Aging effects in nano-scale CMOS circuits impair the reliability and Mean Time to Failure (MTTF) of embedded systems. Especially for FPGAs that are manufactured in the latest technology node, aging is a major concern. We introduce the first cross-layer aging-aware placement method for accelerators in FPGA-based runtime reconfigurable architectures. It optimizes stress distribution by accelerator placement at runtime, i.e. to which reconfigurable region an accelerator shall be reconfigured. Additionally, it optimizes logic placement at synthesis time to diversify the resource usage of individual accelerators, i.e. which CLBs of a reconfigurable region shall be used by an accelerator. Both layers together balance the intra- and inter-region stress induced by the application workload at negligible performance cost. Experimental results show significant reduction of maximum stress of up to 64% and 35%, which leads to up to 177% and 14% MTTF improvement relative to state-of- the-art methods w.r.t. HCI and BTI aging, respectively.
BibTeX:
@inproceedings{ZhangKSBWH2015,
  author = {Zhang, Hongyan and Kochte, Michael A. and Schneider, Eric and Bauer, Lars and Wunderlich, Hans-Joachim and Henkel, Jörg},
  title = {{STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures}},
  booktitle = {Proceedings of the 34th IEEE/ACM International Conference on Computer-Aided Design (ICCAD'15)},
  year = {2015},
  pages = {38-45},
  abstract = {Aging effects in nano-scale CMOS circuits impair the reliability and Mean Time to Failure (MTTF) of embedded systems. Especially for FPGAs that are manufactured in the latest technology node, aging is a major concern. We introduce the first cross-layer aging-aware placement method for accelerators in FPGA-based runtime reconfigurable architectures. It optimizes stress distribution by accelerator placement at runtime, i.e. to which reconfigurable region an accelerator shall be reconfigured. Additionally, it optimizes logic placement at synthesis time to diversify the resource usage of individual accelerators, i.e. which CLBs of a reconfigurable region shall be used by an accelerator. Both layers together balance the intra- and inter-region stress induced by the application workload at negligible performance cost. Experimental results show significant reduction of maximum stress of up to 64% and 35%, which leads to up to 177% and 14% MTTF improvement relative to state-of- the-art methods w.r.t. HCI and BTI aging, respectively.},
  url = { http://dl.acm.org/citation.cfm?id=2840825 },
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/ICCAD_ZhangKSBWH2015.pdf}
}
6. GPU-Accelerated Small Delay Fault Simulation
Schneider, E., Holst, S., Kochte, M.A., Wen, X. and Wunderlich, H.-J.
Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE'15), Grenoble, France, 9-13 March 2015, pp. 1174-1179
Best Paper Candidate
2015
URL PDF 
Abstract: The simulation of delay faults is an essential task in design validation and reliability assessment of circuits. Due to the high sensitivity of current nano-scale designs against smallest delay deviations, small delay faults recently became the focus of test research. Because of the subtle delay impact, traditional fault simulation approaches based on abstract timing models are not sufficient for representing small delay faults. Hence, timing accurate simulation approaches have to be utilized, which quickly become inapplicable for larger designs due to high computational requirements. In this work we present a waveform-accurate approach for fast high-throughput small delay fault simulation on Graphics Processing Units (GPUs). By exploiting parallelism from gates, faults and patterns, the proposed approach enables accurate exhaustive small delay fault simulation even for multi-million gate designs without fault dropping for the first time.
BibTeX:
@inproceedings{SchneHKWW2015,
  author = { Schneider, Eric and Holst, Stefan and Kochte, Michael A. and Wen, Xiaoqing and Wunderlich, Hans-Joachim },
  title = {{GPU-Accelerated Small Delay Fault Simulation}},
  booktitle = {Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE'15)},
  year = {2015},
  pages = {1174--1179},
  abstract = {The simulation of delay faults is an essential task in design validation and reliability assessment of circuits. Due to the high sensitivity of current nano-scale designs against smallest delay deviations, small delay faults recently became the focus of test research. Because of the subtle delay impact, traditional fault simulation approaches based on abstract timing models are not sufficient for representing small delay faults. Hence, timing accurate simulation approaches have to be utilized, which quickly become inapplicable for larger designs due to high computational requirements. In this work we present a waveform-accurate approach for fast high-throughput small delay fault simulation on Graphics Processing Units (GPUs). By exploiting parallelism from gates, faults and patterns, the proposed approach enables accurate exhaustive small delay fault simulation even for multi-million gate designs without fault dropping for the first time.},
  url = { http://dl.acm.org/citation.cfm?id=2757084 },
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/DATE_SchneHKWW2015.pdf}
}
5. Data-Parallel Simulation for Fast and Accurate Timing Validation of CMOS Circuits
Schneider, E., Holst, S., Wen, X. and Wunderlich, H.-J.
Proceedings of the 33rd IEEE/ACM International Conference on Computer-Aided Design (ICCAD'14), San Jose, California, USA, 3-6 November 2014, pp. 17-23
2014
URL PDF 
Abstract: Gate-level timing simulation of combinational CMOS circuits is the foundation of a whole array of important EDA tools such as timing analysis and power-estimation, but the demand for higher simulation accuracy drastically increases the runtime complexity of the algorithms. Data-parallel accelerators such as Graphics Processing Units (GPUs) provide vast amounts of computing performance to tackle this problem, but require careful attention to control-flow and memory access patterns. This paper proposes the novel High-Throughput Oriented Parallel Switch-level Simulator (HiTOPS), which is especially designed to take full advantage of GPUs and provides accurate time- simulation for multi-million gate designs at an unprecedented throughput. HiTOPS models timing at transistor granularity and supports all major timing-related effects found in CMOS including pattern-dependent delay, glitch filtering and transition ramps, while achieving speedups of up to two orders of magnitude compared to traditional gate-level simulators.
BibTeX:
@inproceedings{SchneHWW2014,
  author = {Schneider, Eric and Holst, Stefan and Wen, Xiaoqing and Wunderlich, Hans-Joachim},
  title = {{Data-Parallel Simulation for Fast and Accurate Timing Validation of CMOS Circuits}},
  booktitle = {Proceedings of the 33rd IEEE/ACM International Conference on Computer-Aided Design (ICCAD'14)},
  year = {2014},
  pages = {17--23},
  abstract = {Gate-level timing simulation of combinational CMOS circuits is the foundation of a whole array of important EDA tools such as timing analysis and power-estimation, but the demand for higher simulation accuracy drastically increases the runtime complexity of the algorithms. Data-parallel accelerators such as Graphics Processing Units (GPUs) provide vast amounts of computing performance to tackle this problem, but require careful attention to control-flow and memory access patterns. This paper proposes the novel High-Throughput Oriented Parallel Switch-level Simulator (HiTOPS), which is especially designed to take full advantage of GPUs and provides accurate time- simulation for multi-million gate designs at an unprecedented throughput. HiTOPS models timing at transistor granularity and supports all major timing-related effects found in CMOS including pattern-dependent delay, glitch filtering and transition ramps, while achieving speedups of up to two orders of magnitude compared to traditional gate-level simulators.},
  url = { http://dl.acm.org/citation.cfm?id=2691369 },
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ICCAD_SchneHWW2014.pdf}
}
4. Variation-Aware Deterministic ATPG
Sauer, M., Polian, I., Imhof, M.E., Mumtaz, A., Schneider, E., Czutro, A., Wunderlich, H.-J. and Becker, B.
Proceedings of the 19th IEEE European Test Symposium (ETS'14), Paderborn, Germany, 26-30 May 2014, pp. 87-92
Best paper award
2014
DOI URL PDF 
Keywords: Variation-aware test, fault efficiency, ATPG
Abstract: In technologies affected by variability, the detection status of a small-delay fault may vary among manufactured circuit instances. The same fault may be detected, missed or provably undetectable in different circuit instances. We introduce the first complete flow to accurately evaluate and systematically maximize the test quality under variability. As the number of possible circuit instances is infinite, we employ statistical analysis to obtain a test set that achieves a fault-efficiency target with an user-defined confidence level. The algorithm combines a classical path-oriented test-generation procedure with a novel waveformaccurate engine that can formally prove that a small-delay fault is not detectable and does not count towards fault efficiency. Extensive simulation results demonstrate the performance of the generated test sets for industrial circuits affected by uncorrelated and correlated variations.
BibTeX:
@inproceedings{SauerPIMSCWB2014,
  author = {Sauer, Matthias and Polian, Ilia and Imhof, Michael E. and Mumtaz, Abdullah and Schneider, Eric and Czutro, Alexander and Wunderlich, Hans-Joachim and Becker, Bernd},
  title = {{Variation-Aware Deterministic ATPG}},
  booktitle = {Proceedings of the 19th IEEE European Test Symposium (ETS'14)},
  year = {2014},
  pages = {87--92},
  keywords = {Variation-aware test, fault efficiency, ATPG},
  abstract = {In technologies affected by variability, the detection status of a small-delay fault may vary among manufactured circuit instances. The same fault may be detected, missed or provably undetectable in different circuit instances. We introduce the first complete flow to accurately evaluate and systematically maximize the test quality under variability. As the number of possible circuit instances is infinite, we employ statistical analysis to obtain a test set that achieves a fault-efficiency target with an user-defined confidence level. The algorithm combines a classical path-oriented test-generation procedure with a novel waveformaccurate engine that can formally prove that a small-delay fault is not detectable and does not count towards fault efficiency. Extensive simulation results demonstrate the performance of the generated test sets for industrial circuits affected by uncorrelated and correlated variations.},
  url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6847806},
  doi = {http://dx.doi.org/10.1109/ETS.2014.6847806},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ETS_SauerPIMSCWB2014.pdf}
}
3. Module Diversification: Fault Tolerance and Aging Mitigation for Runtime Reconfigurable Architectures
Zhang, H., Bauer, L., Kochte, M.A., Schneider, E., Braun, C., Imhof, M.E., Wunderlich, H.-J. and Henkel, J.
Proceedings of the IEEE International Test Conference (ITC'13), Anaheim, California, USA, 10-12 September 2013
2013
DOI URL PDF 
Keywords: Reliability, online test, fault-tolerance, aging mitigation, partial runtime reconfiguration, FPGA
Abstract: Runtime reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) are attractive for realizing complex applications. However, being manufactured in latest semiconductor process technologies, FPGAs are increasingly prone to aging effects, which reduce the reliability of such systems and must be tackled by aging mitigation and application of fault tolerance techniques. This paper presents module diversification, a novel design method that creates different configurations for runtime reconfigurable modules. Our method provides fault tolerance by creating the minimal number of configurations such that for any faulty Configurable Logic Block (CLB) there is at least one configuration that does not use that CLB. Additionally, we determine the fraction of time that each configuration should be used to balance the stress and to mitigate the aging process in FPGA-based runtime reconfigurable systems. The generated configurations significantly improve reliability by fault-tolerance and aging mitigation.
BibTeX:
@inproceedings{ZhangBKSBIWH2013,
  author = {Zhang, Hongyan and Bauer, Lars and Kochte, Michael A. and Schneider, Eric and Braun, Claus and Imhof, Michael E. and Wunderlich, Hans-Joachim and Henkel, Jörg},
  title = {{Module Diversification: Fault Tolerance and Aging Mitigation for Runtime Reconfigurable Architectures}},
  booktitle = {Proceedings of the IEEE International Test Conference (ITC'13)},
  year = {2013},
  keywords = {Reliability, online test, fault-tolerance, aging mitigation, partial runtime reconfiguration, FPGA},
  abstract = {Runtime reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) are attractive for realizing complex applications. However, being manufactured in latest semiconductor process technologies, FPGAs are increasingly prone to aging effects, which reduce the reliability of such systems and must be tackled by aging mitigation and application of fault tolerance techniques. This paper presents module diversification, a novel design method that creates different configurations for runtime reconfigurable modules. Our method provides fault tolerance by creating the minimal number of configurations such that for any faulty Configurable Logic Block (CLB) there is at least one configuration that does not use that CLB. Additionally, we determine the fraction of time that each configuration should be used to balance the stress and to mitigate the aging process in FPGA-based runtime reconfigurable systems. The generated configurations significantly improve reliability by fault-tolerance and aging mitigation.},
  url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6651926},
  doi = {http://dx.doi.org/10.1109/TEST.2013.6651926},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2013/ITC_ZhangBKSBIWH2013.pdf}
}
2. Test Strategies for Reliable Runtime Reconfigurable Architectures
Bauer, L., Braun, C., Imhof, M.E., Kochte, M.A., Schneider, E., Zhang, H., Henkel, J. and Wunderlich, H.-J.
IEEE Transactions on Computers
Vol. 62(8), Los Alamitos, California, USA, August 2013, pp. 1494-1507
2013
DOI URL PDF 
Keywords: FPGA, Reconfigurable Architectures, Online Test
Abstract: FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. The reliability of FPGAs, being manufactured in latest technologies, is threatened by soft errors, as well as aging effects and latent defects.To ensure reliable reconfiguration, it is mandatory to guarantee the correct operation of the reconfigurable fabric. This can be achieved by periodic or on-demand online testing. This paper presents a reliable system architecture for runtime-reconfigurable systems, which integrates two non-concurrent online test strategies: Pre-configuration online tests (PRET) and post-configuration online tests (PORT). The PRET checks that the reconfigurable hardware is free of faults by periodic or on-demand tests. The PORT has two objectives: It tests reconfigured hardware units after reconfiguration to check that the configuration process completed correctly and it validates the expected functionality. During operation, PORT is used to periodically check the reconfigured hardware units for malfunctions in the programmable logic. Altogether, this paper presents PRET, PORT, and the system integration of such test schemes into a runtime-reconfigurable system, including the resource management and test scheduling. Experimental results show that the integration of online testing in reconfigurable systems incurs only minimum impact on performance while delivering high fault coverage and low test latency.
BibTeX:
@article{BauerBIKSZHW2013,
  author = {Bauer, Lars and Braun, Claus and Imhof, Michael E. and Kochte, Michael A. and Schneider, Eric and Zhang, Hongyan and Henkel, Jörg and Wunderlich, Hans-Joachim},
  title = {{Test Strategies for Reliable Runtime Reconfigurable Architectures}},
  journal = {IEEE Transactions on Computers},
  publisher = {IEEE Computer Society},
  year = {2013},
  volume = {62},
  number = {8},
  pages = {1494--1507},
  keywords = {FPGA, Reconfigurable Architectures, Online Test},
  abstract = {FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. The reliability of FPGAs, being manufactured in latest technologies, is threatened by soft errors, as well as aging effects and latent defects.To ensure reliable reconfiguration, it is mandatory to guarantee the correct operation of the reconfigurable fabric. This can be achieved by periodic or on-demand online testing. This paper presents a reliable system architecture for runtime-reconfigurable systems, which integrates two non-concurrent online test strategies: Pre-configuration online tests (PRET) and post-configuration online tests (PORT). The PRET checks that the reconfigurable hardware is free of faults by periodic or on-demand tests. The PORT has two objectives: It tests reconfigured hardware units after reconfiguration to check that the configuration process completed correctly and it validates the expected functionality. During operation, PORT is used to periodically check the reconfigured hardware units for malfunctions in the programmable logic. Altogether, this paper presents PRET, PORT, and the system integration of such test schemes into a runtime-reconfigurable system, including the resource management and test scheduling. Experimental results show that the integration of online testing in reconfigurable systems incurs only minimum impact on performance while delivering high fault coverage and low test latency.},
  url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6475939},
  doi = {http://dx.doi.org/10.1109/TC.2013.53},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2013/TC_BauerBIKSZHW2013.pdf}
}
1. Scan Test Power Simulation on GPGPUs
Holst, S., Schneider, E. and Wunderlich, H.-J.
Proceedings of the 21st IEEE Asian Test Symposium (ATS'12), Niigata, Japan, 19-22 November 2012, pp. 155-160
2012
DOI PDF 
Keywords: GPGPU, Data–Parallelism, Scan–Test, Power, Time–Simulation, Hazards, Pulse–Filtering
Abstract: The precise estimation of dynamic power consumption, power droop and temperature development during scan test require a very large number of time–aware gate–level logic simulations. Until now, such characterizations have been feasible only for rather small designs or with reduced precision due to the high computational demands. We propose a new, throughput–optimized timing simulator on running on GPGPUs to accelerate these tasks by more than two orders of magnitude and thus providing for the first time precise and comprehensive toggle data for industrial–sized designs and over long scan test operations. Hazards and pulse–filtering are supported for the first time in a GPGPU accelerated simulator, and the system can easily be extended to even more sophisticated delay and power models.
BibTeX:
@inproceedings{HolstSW2012,
  author = {Holst, Stefan and Schneider, Eric and Wunderlich, Hans-Joachim},
  title = {{Scan Test Power Simulation on GPGPUs}},
  booktitle = {Proceedings of the 21st IEEE Asian Test Symposium (ATS'12)},
  publisher = {IEEE Computer Society},
  year = {2012},
  pages = {155--160},
  keywords = {GPGPU, Data–Parallelism, Scan–Test, Power, Time–Simulation, Hazards, Pulse–Filtering},
  abstract = {The precise estimation of dynamic power consumption, power droop and temperature development during scan test require a very large number of time–aware gate–level logic simulations. Until now, such characterizations have been feasible only for rather small designs or with reduced precision due to the high computational demands. We propose a new, throughput–optimized timing simulator on running on GPGPUs to accelerate these tasks by more than two orders of magnitude and thus providing for the first time precise and comprehensive toggle data for industrial–sized designs and over long scan test operations. Hazards and pulse–filtering are supported for the first time in a GPGPU accelerated simulator, and the system can easily be extended to even more sophisticated delay and power models.},
  doi = {http://dx.doi.org/10.1109/ATS.2012.23},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2012/ATS_HolstSW2012.pdf}
}
Created by JabRef on 31/07/2017.
Workshop Contributions and Miscellaneous
Matching entries: 0
settings...
1. Hochbeschleunigte Simulation von Verzögerungsfehlern unter Prozessvariationen
Schneider, E., Kochte, M.A. and Wunderlich, H.-J.
27th GI/GMM/ITG Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'15), Bad Urach, Germany, 1-3 March 2015
2015
 
Abstract: Die Simulation kleiner Verzögerungsfehler ist ein wichtiger Bestandteil der Validierung nano-elektronischer Schaltungen. Prozessvariationen während der Herstellung haben großen Einfluss auf die Erkennung dieser Fehler und müssen bei der Simulation berücksichtigt werden. Die zeitgenaue Simulation von Verzögerungsfehlern ist verglichen mit traditioneller Logiksimulation oder statischer Zeitanalyse sehr aufwändig und die Rechenkomplexität steigt durch die Berücksichtigung von Variationen zusätzlich an. In dieser Arbeit wird ein hochparalleles Verfahren vorgestellt, welches Grafikprozessoren zur beschleunigten parallelen Simulation kleiner Verzögerungsfehler unter Variation anwendet. Das Verfahren berechnet akkurate Signalverläufe in der Schaltung und ermöglicht die Bestimmung einer Monte-Carlo-basierten statistischen Fehlererfassung für industrielle Schaltkreise unter zufälliger sowie systematischer Variation.
BibTeX:
@inproceedings{SchneKW2015,
  author = {Schneider, Eric and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Hochbeschleunigte Simulation von Verzögerungsfehlern unter Prozessvariationen}},
  booktitle = {27th GI/GMM/ITG Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'15)},
  year = {2015},
  abstract = {Die Simulation kleiner Verzögerungsfehler ist ein wichtiger Bestandteil der Validierung nano-elektronischer Schaltungen. Prozessvariationen während der Herstellung haben großen Einfluss auf die Erkennung dieser Fehler und müssen bei der Simulation berücksichtigt werden. Die zeitgenaue Simulation von Verzögerungsfehlern ist verglichen mit traditioneller Logiksimulation oder statischer Zeitanalyse sehr aufwändig und die Rechenkomplexität steigt durch die Berücksichtigung von Variationen zusätzlich an. In dieser Arbeit wird ein hochparalleles Verfahren vorgestellt, welches Grafikprozessoren zur beschleunigten parallelen Simulation kleiner Verzögerungsfehler unter Variation anwendet. Das Verfahren berechnet akkurate Signalverläufe in der Schaltung und ermöglicht die Bestimmung einer Monte-Carlo-basierten statistischen Fehlererfassung für industrielle Schaltkreise unter zufälliger sowie systematischer Variation.}
}
Created by JabRef on 31/07/2017.
Miscellaneous Activities

11.

Poster How-To
Schneider, E., Holst S.

Special lecture at 2016 International Symposium on Dependable Integrated Systems in collaboration with the Kyushu Institute of Technology, Fukuoka, JP, Nov. 28, 2016.

10.

Diagnosis of Small Delay Faults
Schneider, E.

2016 Joint Workshop on Dependable Integrated Systems in collaboration with the Kyushu Institute of Technology, Fukuoka, JP, Sep. 9, 2016.

9.

High-Throughput Parallel Simulation - The Key to Efficient Design and Test Validation
Schneider, E.
Special lecture at Kyushu Institute of Technology, Iizuka, JP, Sep. 8, 2016.

8.

How to master a Master in Germany?
Schneider, E.
Special lecture at Kyushu Institute of Technology, Iizuka, JP, Sep. 8, 2016.

7.

Hazard-Activated Stuck-Open Fault Simulation
Schneider, E.

2016 Joint DAAD/JSPS Spring Research Workshop (Stuttgart-Iizuka), University of Stuttgart, Stuttgart, DE, Mar. 2-5, 2016.

6.

GPU-Accelerated Small Delay Fault Simulation
Schneider, E.
Invited talk at 2015 Joint Workshop on Dependable Integrated Systems in collaboration with the Kyushu Institute of Technology, Fukuoka, JP, Sep. 3, 2015.

5.

GPU-Accelerated Small Delay Fault Simulation
Schneider, E.
Invited talk at Osaka University, Osaka, JP, Aug. 31, 2015.

4.

INFORMATIK 2014
Plödereder, E., Grunske, L., Schneider, E., Ull, D. (Hrsg.)
GI-Edition - Lecture Notes in Informatics (LNI), Vol. P-232, Gesellschaft für Informatik e.V. (GI), Sep. 22-26, 2014,
ISBN: 978-3-88579-626-8, Bonner Köllen Verlag, Bonn, DE, 2014.

3.

Massive Throughput Computing: GPUs and their Application in EDA
Schneider, E.
Special lecture at Kyushu Institute of Technology, Iizuka, JP, Sep. 19, 2014.

2.

Data-Parallel Switch-Level Simulation for Fast and Accurate Timing Validation of CMOS Circuits
Schneider, E., Holst, S., Wen, X., Wunderlich, H.-J.
Poster at 51st Design Automation Conf. (DAC), San Francisco, CA, USA, Jun. 1-5, 2014.

1.

GPU-Accelerated Small Delay Fault Simulation
Schneider, E., Holst, S., Wunderlich, H.-J.
Poster at Dependable GPU Computing Workshop, ACM/IEEE Conf. on Design and Test in Europe (DATE),
Dresden, DE, Mar. 24-28, 2014.

 

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