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Chang Liu

M. Sc. Chang Liu

Name:

M. Sc. Chang Liu

Adresse:

Universität Stuttgart

Institut für Technische Informatik

Pfaffenwaldring 47

70569 Stuttgart

Raum:

3.163

Sprechstunde:

nach Vereinbarung

Telefon:

+49 - 711 - 685 - 88282

Fax:

+49 - 711 - 685 - 88288

E-Mail:

Chang.Liu@informatik.uni-stuttgart.de

Laufende Projekte

OASIS: Online-Ausfallvorhersage mikroelektronischer Schaltungen mittels Alterungssignaturen

Projektseite: Online-Ausfallvorhersage mikroelektronischer Schaltungen mittels Alterungssignaturen

Mikroelektronische Schaltungen sind, wie auch mechanische Komponenten, lebenszeitbegrenzenden Alterungsprozessen ausgesetzt. Um Ausfälle aufgrund der Alterung vorherzusagen, werden Verfahren entwickelt und untersucht, die online (während des Betriebs) die Leistungsfähigkeit und die noch zu erwartende Lebensdauer bestimmen. Mittels Monitoring werden Betriebsbedingungen und Alterungsindikatoren in einer Infrastruktur analysiert, so dass durch Früherkennung einem Ausfall durch systemtechnische Maßnahmen vorgebeugt werden kann. Neue Wartungskonzepte ermöglichen eine erhebliche Vereinfachung von strukturellen Fehlertoleranzmaßnahmen (z.B. Redundanzkonzepten) selbst in sicherheitskritischen Anwendungen, da gezielte Maßnahmen vor Eintritt altersbedingter Fehlfunktionen ergriffen werden können. Die effektive Lebensdauer eines mikroelektronischen Produkts kann mit Hilfe eines derartigen Online-Monitorings auf ein Vielfaches erhöht werden.

03.2011 - 12.2014, DFG-Projekt: WU 245/11-1    

Publikationen

Zeitschriften und Konferenzbeiträge
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5. Aging Monitor Reuse for Small Delay Fault Testing
Liu, C., Kochte, M.A. and Wunderlich, H.-J.
Proceedings of the 35th VLSI Test Symposium (VTS'17), Caesars Palace, Las Vegas, Nevada, USA, 9-12 April 2017
2017
DOI PDF 
Keywords: Delay monitoring, delay test, faster-than-at-speed test, stability checker, small delay fault, ATPG
Abstract: Small delay faults receive more and more attention, since they may indicate a circuit reliability marginality even if they do not violate the timing at the time of production. At-speed test and faster-than-at-speed test (FAST) are rather expensive tasks to test for such faults. The paper at hand avoids complex on-chip structures or expensive high-speed ATE for test response evaluation, if aging monitors which are integrated into the device under test anyway are reused. The main challenge in reusing aging monitors for FAST consists in possible false alerts at higher frequencies. While a certain test vector pair makes a delay fault observable at one monitor, it may also exceed the time slack in the fault free case at a different monitor which has to be masked. Therefore, a multidimensional optimizing problem has to be solved for minimizing the masking overhead and the number of test vectors while maximizing delay fault coverage.
BibTeX:
@inproceedings{LiuKW2017,
  author = {Liu, Chang and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Aging Monitor Reuse for Small Delay Fault Testing}},
  booktitle = {Proceedings of the 35th VLSI Test Symposium (VTS'17)},
  year = {2017},
  keywords = {Delay monitoring, delay test, faster-than-at-speed test, stability checker, small delay fault, ATPG},
  abstract = {Small delay faults receive more and more attention, since they may indicate a circuit reliability marginality even if they do not violate the timing at the time of production. At-speed test and faster-than-at-speed test (FAST) are rather expensive tasks to test for such faults. The paper at hand avoids complex on-chip structures or expensive high-speed ATE for test response evaluation, if aging monitors which are integrated into the device under test anyway are reused. The main challenge in reusing aging monitors for FAST consists in possible false alerts at higher frequencies. While a certain test vector pair makes a delay fault observable at one monitor, it may also exceed the time slack in the fault free case at a different monitor which has to be masked. Therefore, a multidimensional optimizing problem has to be solved for minimizing the masking overhead and the number of test vectors while maximizing delay fault coverage.},
  doi = {http://dx.doi.org/10.1109/VTS.2017.7928921},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2017/VTS_LiuKW2017.pdf}
}
4. Efficient Observation Point Selection for Aging Monitoring
Liu, C., Kochte, M.A. and Wunderlich, H.-J.
Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS'15), Elia, Halkidiki, Greece, 6-8 July 2015, pp. 176-181
2015
DOI PDF 
Keywords: Aging monitoring, delay monitoring, online test, concurrent test, stability checker, path selection
Abstract: Circuit aging causes a performance degradation and eventually a functional failure. It depends on the workload and the environmental condition of the system, which are hard to predict in early design phases resulting in pessimistic worst case design. Existing delay monitoring schemes measure the remaining slack of paths in the circuit, but cause a significant hardware penalty including global wiring. More importantly, the low sensitization ratio of long paths in applications may lead to a very low measurement frequency or even an unmonitored timing violation. In this work, we propose a delay monitor placement method by analyzing the topological circuit structure and sensitization of paths. The delay monitors are inserted at meticulously selected positions in the circuit, named observation points (OPs). This OP monitor placement method can reduce the number of inserted monitors by up to 98% compared to a placement at the end of long paths. The experimental validation shows the effectiveness of this aging indication, i.e. a monitor issues a timing alert always earlier than any imminent timing failure.
BibTeX:
@inproceedings{LiuKW2015,
  author = {Liu, Chang and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Efficient Observation Point Selection for Aging Monitoring}},
  booktitle = {Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS'15)},
  year = {2015},
  pages = {176--181},
  keywords = {Aging monitoring, delay monitoring, online test, concurrent test, stability checker, path selection},
  abstract = {Circuit aging causes a performance degradation and eventually a functional failure. It depends on the workload and the environmental condition of the system, which are hard to predict in early design phases resulting in pessimistic worst case design. Existing delay monitoring schemes measure the remaining slack of paths in the circuit, but cause a significant hardware penalty including global wiring. More importantly, the low sensitization ratio of long paths in applications may lead to a very low measurement frequency or even an unmonitored timing violation. In this work, we propose a delay monitor placement method by analyzing the topological circuit structure and sensitization of paths. The delay monitors are inserted at meticulously selected positions in the circuit, named observation points (OPs). This OP monitor placement method can reduce the number of inserted monitors by up to 98% compared to a placement at the end of long paths. The experimental validation shows the effectiveness of this aging indication, i.e. a monitor issues a timing alert always earlier than any imminent timing failure.},
  doi = {http://dx.doi.org/10.1109/IOLTS.2015.7229855},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/IOLTS_LiuKW2015.pdf}
}
3. On-Line Prediction of NBTI-induced Aging Rates
Baranowski, R., Firouzi, F., Kiamehr, S., Liu, C., Tahoori, M. and Wunderlich, H.-J.
Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE'15), Grenoble, France, 9-13 March 2015, pp. 589-592
2015
URL PDF 
Keywords: Representative critical gates, Workload monitoring, Aging prediction, NBTI
Abstract: Nanoscale technologies are increasingly susceptible to aging processes such as Negative-Bias Temperature Instability (NBTI) which undermine the reliability of VLSI systems. Existing monitoring techniques can detect the violation of safety margins and hence make the prediction of an imminent failure possible. However, since such techniques can only detect measurable degradation effects which appear after a relatively long period of system operation, they are not well suited to early aging prediction and proactive aging alleviation. This work presents a novel method for the monitoring of NBTI-induced degradation rate in digital circuits. It enables the timely adoption of proper mitigation techniques that reduce the impact of aging. The developed method employs machine learning techniques to find a small set of so called Representative Critical Gates (RCG), the workload of which is correlated with the degradation of the entire circuit. The workload of RCGs is observed in hardware using so called workload monitors. The output of the workload monitors is evaluated on-line to predict system degradation experienced within a configurable (short) period of time, e.g. a fraction of a second. Experimental results show that the developed monitors predict the degradation rate with an average error of only 1.6% at 4.2% area overhead.
BibTeX:
@inproceedings{BaranFKLWT2015,
  author = { Baranowski, Rafal and Firouzi, Farshad and Kiamehr, Saman and Liu, Chang and Tahoori, Mehdi and Wunderlich, Hans-Joachim },
  title = {{On-Line Prediction of NBTI-induced Aging Rates}},
  booktitle = {Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE'15)},
  year = {2015},
  pages = {589--592},
  keywords = {Representative critical gates, Workload monitoring, Aging prediction, NBTI},
  abstract = {Nanoscale technologies are increasingly susceptible to aging processes such as Negative-Bias Temperature Instability (NBTI) which undermine the reliability of VLSI systems. Existing monitoring techniques can detect the violation of safety margins and hence make the prediction of an imminent failure possible. However, since such techniques can only detect measurable degradation effects which appear after a relatively long period of system operation, they are not well suited to early aging prediction and proactive aging alleviation. This work presents a novel method for the monitoring of NBTI-induced degradation rate in digital circuits. It enables the timely adoption of proper mitigation techniques that reduce the impact of aging. The developed method employs machine learning techniques to find a small set of so called Representative Critical Gates (RCG), the workload of which is correlated with the degradation of the entire circuit. The workload of RCGs is observed in hardware using so called workload monitors. The output of the workload monitors is evaluated on-line to predict system degradation experienced within a configurable (short) period of time, e.g. a fraction of a second. Experimental results show that the developed monitors predict the degradation rate with an average error of only 1.6% at 4.2% area overhead.},
  url = { http://dl.acm.org/citation.cfm?id=2755886 },
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/DATE_BaranFKLTW2015.pdf}
}
2. FAST-BIST: Faster-than-At-Speed BIST Targeting Hidden Delay Defects
Hellebrand, S., Indlekofer, T., Kampmann, M., Kochte, M.A., Liu, C. and Wunderlich, H.-J.
Proceedings of the IEEE International Test Conference (ITC'14), Seattle, Washington, USA, 20-23 October 2014, pp. 1-8
2014
DOI PDF 
Abstract: Small delay faults may be an indicator of a reliability threat, even if they do not affect the system functionality yet. In recent years, Faster-than-at-Speed-Test (FAST) has become a feasible method to detect faults, which are hidden by the timing slack or by long critical paths in the combinational logic. FAST poses severe challenges to the automatic test equipment with respect to timing, performance, and resolution. In this paper, it is shown how logic built-in self-test (BIST) or embedded deterministic test can be used for an efficient FAST application. Running BIST just at a higher frequency is not an option, as outputs of long paths will receive undefined values due to set time violations and destroy the content of the signature registers. Instead, for a given test pattern sequence, faults are classified according to the optimal detection frequency. For each class, a MISR-based compaction scheme is adapted, such that the critical bits to be observed can be determined by algebraic computations. Experiments show that rather a small number of inter-mediate signatures have to be evaluated to observe a large fraction of hidden delay faults testable by the given test sequence.
BibTeX:
@inproceedings{HelleIKKLW2014,
  author = {Hellebrand, Sybille and Indlekofer, Thomas and Kampmann, Matthias and Kochte, Michael A. and Liu, Chang and Wunderlich, Hans-Joachim},
  title = {{FAST-BIST: Faster-than-At-Speed BIST Targeting Hidden Delay Defects}},
  booktitle = {Proceedings of the IEEE International Test Conference (ITC'14)},
  year = {2014},
  pages = {1--8},
  abstract = {Small delay faults may be an indicator of a reliability threat, even if they do not affect the system functionality yet. In recent years, Faster-than-at-Speed-Test (FAST) has become a feasible method to detect faults, which are hidden by the timing slack or by long critical paths in the combinational logic. FAST poses severe challenges to the automatic test equipment with respect to timing, performance, and resolution. In this paper, it is shown how logic built-in self-test (BIST) or embedded deterministic test can be used for an efficient FAST application. Running BIST just at a higher frequency is not an option, as outputs of long paths will receive undefined values due to set time violations and destroy the content of the signature registers. Instead, for a given test pattern sequence, faults are classified according to the optimal detection frequency. For each class, a MISR-based compaction scheme is adapted, such that the critical bits to be observed can be determined by algebraic computations. Experiments show that rather a small number of inter-mediate signatures have to be evaluated to observe a large fraction of hidden delay faults testable by the given test sequence.},
  doi = {http://dx.doi.org/10.1109/TEST.2014.7035360},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ITC_HelleIKKLW2014.pdf}
}
1. Synthesis of Workload Monitors for On-Line Stress Prediction
Baranowski, R., Cook, A., Imhof, M.E., Liu, C. and Wunderlich, H.-J.
Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'13), New York City, New York, USA, 2-4 October 2013, pp. 137-142
2013
DOI URL PDF 
Keywords: Reliability estimation, workload monitoring, aging prediction, NBTI
Abstract: Stringent reliability requirements call for monitoring mechanisms to account for circuit degradation throughout the complete system lifetime. In this work, we efficiently monitor the stress experienced by the system as a result of its current workload. To achieve this goal, we construct workload monitors that observe the most relevant subset of the circuit’s primary and pseudo-primary inputs and produce an accurate stress approximation. The proposed approach enables the timely adoption of
suitable countermeasures to reduce or prevent any deviation from the intended circuit behavior. The relation between monitoring accuracy and hardware cost can be adjusted according to design requirements. Experimental results show the efficiency of the proposed approach for the prediction of stress induced by Negative Bias Temperature Instability (NBTI) in critical and near-critical paths of a digital circuit.
BibTeX:
@inproceedings{BaranCILW2013,
  author = {Baranowski, Rafal and Cook, Alejandro and Imhof, Michael E. and Liu, Chang and Wunderlich, Hans-Joachim},
  title = {{Synthesis of Workload Monitors for On-Line Stress Prediction}},
  booktitle = {Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'13)},
  year = {2013},
  pages = {137--142},
  keywords = {Reliability estimation, workload monitoring, aging prediction, NBTI},
  abstract = {Stringent reliability requirements call for monitoring mechanisms to account for circuit degradation throughout the complete system lifetime. In this work, we efficiently monitor the stress experienced by the system as a result of its current workload. To achieve this goal, we construct workload monitors that observe the most relevant subset of the circuit’s primary and pseudo-primary inputs and produce an accurate stress approximation. The proposed approach enables the timely adoption of
suitable countermeasures to reduce or prevent any deviation from the intended circuit behavior. The relation between monitoring accuracy and hardware cost can be adjusted according to design requirements. Experimental results show the efficiency of the proposed approach for the prediction of stress induced by Negative Bias Temperature Instability (NBTI) in critical and near-critical paths of a digital circuit.}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6653596}, doi = {http://dx.doi.org/10.1109/DFT.2013.6653596}, file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2013/DFTS_BaranCILW2013.pdf} }
Created by JabRef on 13/06/2017.

Journals / Konferenzen

  • Dynamic Modeling of Zinc Oxide Thin Film Transistors (ZnO-TFTs)
  • C. Liu, H.-P. Keil, S. Pankalla, M. Glesner
    Large-area, Organic & Printed Electronics Convention (LOPE-C), Frankfurt, Germany, June 28-30, 2011

Lehre

Master- / Diplomarbeiten

    Vorgeschlagene Themen
    • Reliability Infrastructure and Controller for a Processor Core
     Abgeschlossene Themen
    • Master Thesis Nr.3436: Simulation-Based Analysis For NBTI Degradation In Gombinational CMOS VLSI Circuits
      Zdravko Georgiev
      21.11.2012 - 21.06.2013