Testability of NoC Structures

Master Thesis

Atefe Dalirsani

Advisor: Prof. Zainalabedin Navabi

University of Tehran - CAD Research Group - Dec. 2007

Abstract

Complexity of digital circuits in the coming billion transistors era is driving development of new design methodologies to provide a more structured communication fabric for system on chips. To meet the communication requirements of large SoCs, a network-on-a-chip (NoC) paradigm is emerging as a new design methodology. Like all digital circuits, we should investigate test and reliability capabilities of network on chips and propose new test methodologies to solve testability problems in NoCs.

            In this thesis, we will investigate testability concepts in NoCs. First, we have proposed an offline test methodology to test switches in an NoC architecture. Using the intra-switch regularity among ports of a switch and inter-switch regularity among routers of switches, the proposed method decreases the test application time and test data volume. The logic and memory parts of a switch are tested by appropriate memory and logic testing methods. Experimental results show less test application time and test power consumption, as compared with other methods in the literature.

            Then, we have proposed a functional test methodology to functionally test the routers of switches in an NoC architecture. Using multiple parallel paths in NoC architecture and regular topologies, the proposed method decreases test application time, test data volume, and test hardware overhead. Experimental results show that the test application time of our methodology for NoC mesh architecture is a liner function of mesh dimensions and is independent of switch complexity. Because this method tests switches in normal operation mode, we can use it in online testing.

            We classified switch faults of an NoC according to their impact on system functionality into two classes of faults: control faults, and data faults. Using this classification, we have proposed a reliability model to calculate reliability of NoC architectures. Reliability Factor is the probability that faults in the NoC infrastructure can be recovered without any effect on system functionality. We calculate the reliability factor based on error recovery parameter and probability of occurrence of a fault type. Our analytical model for reliability evaluation can be used to decide which fault tolerant techniques cause more improvement on system reliability. Also, using this model, we can choose more efficient test methods for online testing.