Mutation framework for defect analysis in very deep submicron CMOS circuits
With continued shrinking of semiconductor feature size, modern VLSI circuits are becoming ever more prone to physical defects. Depending on their shape, size and location on the chip, these defects can change the electrical properties of a chip in complex ways. A particular defect may or may not cause a malfunction during normal operation of the circuit, which can be predicted using SPICE simulation on electrical level. An accurate analysis requires the generation and SPICE simulation of a large number of random circuit mutations to study the impact of different kinds of defects on the circuit operation. Clearly, this analysis cannot be done manually.
The scope of this thesis is to develop an efficient framework for random defect analysis consisting of the following three steps:
1. Mutant generation using any of a set of mutation operations to e.g. place an extra resistor between two neighboring nodes
2. Update of SPICE netlist description, SPICE simulation and data collection
3. Evaluation of results and classification of defects based on observed circuit operation
The SPICE simulation can for example be performed using the Ngspice shared library.
Mandatory programming skills:
- J. P. Shen, W. Maly, and F. Joel Ferguson, “Inductive Fault Analysis of MOS Integrated Circuits,” IEEE Design and Test of Computers, vol. 2, no. 6, pp. 13-26, 1985.
- X. Tang, A. Xu, W. Li, and Z. Yang, “Fault Models of CMOS Gates: An Empirical Study Based on Mutation Analysis,” in International Conference on Dependable, Autonomic and Secure Computing, 2014, pp. 115-120.