Zur Webseite der Uni Stuttgart

Multi-level Simulation of Secure Accesses in Reconfigurable Scan Networks

The design of modern VLSI chips is a very complicated process. A large part of this complexity comes from the difficulty of testing and verifying the functionality of large and complex designs. This has led to the integration of a large number of instrumentation for post-silicon validation and debug, volume and test, diagnosis and in-field system maintenance. Due to the large number of embedded instruments, an efficient and scalable method to access this instrumentation is required. Reconfigurable Scan Networks (RSNs) which are standardized by IEEE Std. 1141.1-2013 and the IEEE Std. P1687 provide the access requirements for such instrumentation.

 

However, these structures pose a security risk and can open a side-channel for unauthorized users to access or manipulate safety critical information or configuration data. This security threat needs to be addressed for chips used in safety critical systems, such as Automotive or Avionics applications. Some techniques have been presented previously to secure RSNs. However, a new simulation environment is required to validate security and safety properties of the whole system. To avoid long runtimes and validate the required security properties over the entire system design, the simulation should use abstraction at multiple levels, high abstraction for the system functionality and low abstraction for the aspects relevant for security analysis. The resulting simulator should be able to automate the

 

The goal of this project is to develop a multi-level System-C simulation environment that models the System components and their attached instrumentation. The simulator should be able to simulate the system at a high-level Transaction Level Model (TLM) as well as the scan network at a lower cycle accurate level. This will give the advantage of low run times as high abstraction is used where applicable. In the simulation environment, given security requirements shall be annotated. If the simulation causes a violation of a requirement, a notification shall be given.


Recommended Prerequisites:

Lectures:

  •  Hardware Verification and Quality Assurance
  •  Advanced Processor Architecture

Programming:

  • Programming skills in: C/C++
  • Basic knowledge of SystemC/Verilog/VHDL

 

Contact: