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Frequency Optimization for Hidden Delay Fault Testing with Monitor Reuse Framework

Small Delay Faults (SDFs), which introduce an additional delay at cells or interconnects, may indicate marginal hardware that degrades into an early life failure (ELF) after a short period of operation. Hidden Delay Faults (HDFs) are a subset of SDFs, the fault magnitude of which is smaller than the slack of the longest sensitizable path through the fault site. As a result, HDFs are undetectable by at-speed or even timing-aware delay test.  They can be targeted by Faster-than-At-Speed Test (FAST), which applies test patterns at frequencies above the nominal operating speed.


During FAST, transitions propagated through long paths to the primary or pseudo-primary outputs may not reach their stable states in time and cause unknown values (X) in the test responses. Those X values can corrupt the response compaction results and therefore require dedicated structures for test control and evaluation. To avoid the sophisticated X-handling structures, [Liu17] reuses on-chip delay monitors integrated initially for aging prediction to detect the HDFs.


The goal of this thesis is to develop a test frequency selection algorithm. Since each HDF can be observed only at a given period with particular pattern pairs, the student first needs to build up the relation between the HDFs and their detection frequencies and patterns under the monitor reuse framework. Then, the student can propose a heuristic greedy algorithm to select a minimum number of frequencies for a maximum fault coverage. On the other hand, the number of frequencies minimization can also be modeled as a pseudo-Boolean optimization problem and solved by a SAT solver. Finally, the student should evaluate the selection algorithm by comparing the testing time and hardware overhead to conventional FAST schemes.


Recommended Prerequisites:

Lectures:

  •  Hardware-based Fault Tolerance
  •  Advanced Processor Architecture

Programming:

  • Basic knowledge for VHDL/ Verilog
  • Skilled in Java

This thesis can be written in English or German

 

Reference:

[Liu17] Aging Monitor Reuse for Small Delay Fault Testing
Liu, C., Kochte, M. A., and Wunderlich, H.-J.
Proceedings of the 35rd IEEE VLST Test Symposium (VTS'17), Las Vegas, NV, USA, 9-12 April 2017, pp. 1-6 

 

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