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RA - Abgeschlossene Diplomarbeiten

  • Studienarbeit Nr.2384: Framework für beschleunigte Monte Carlo Molekularsimulationen auf hybriden Architekturen
    S Halder
    01.06.2012 - 01.12.2012
  • Diplomarbeit Nr.3354: Effiziente mehrwertige Logiksimulation verzögerungsbehafteter Schaltungen auf datenparallelen Architekturen
    Alexander Schöll
    01.06.2012 - 01.12.2012
  • Master Thesis Nr.3239: Fault Tolerant Routing Algorithm for Fully- and Partially-defective NoC Switches
    Seyyed Mahdi Najmabadi
    01.09.2011 - 01.03.2012
  • Studienarbeit Nr.2347: Parallele Partikelsimulation auf GPGPU-Architekturen zur Evaluierung von Apoptose-Signalwegen
    Alexander Schöll
    01.09.2011 - 02.03.2012
  • Bachelor Project Nr.2334: Simulation of Realistic Defects for Validating Test and Diagnosis Algorithms
    Hossam Abouzeid Mohamed El Atali
    05.04.2011 - 31.08.2011
  • Diplomarbeit Nr.3146: Strukturelle Feldtests bei komplexen ASICs
    Dominik Ull
    10.01.2011 - 09.08.2011
  • Studienarbeit Nr.2306: CUDA-accelerated Delay Fault Simulation
    Eric Schneider
    1.11.2010 - 3.05.2011
  • Diplomarbeit Nr.3069: Simulation Framework for Built-In Diagnosis of Self-Checking Circuits
    Laura Rodriguez Gomez
    19.06.2010 - 18.01.2011

  • Diplomarbeit Nr.3380: Test Rekonfigurierbarer Scan-Netzwerke
    Marcel Schaal
    08.08.2012 - 07.02.2013
    Abstract
    Moderne Mikrochips enthalten zahlreiche Instrumente, die zur Auswertung der Betriebsparameter, zum Test oder zur Validierung der Funktionalität genutzt werden. Rekonfigurierbare Scan-Netzwerke bieten die Möglichkeit eines effizienteren, flexibleren und skalierbareren Zugriffs auf eingebettete Instrumente gegenüber üblichen statischen Scan-Ketten. Durch den Einsatz von Rekonfigurierbaren Scan-Netzwerken nimmt jedoch die Komplexität der Zugriffsinfrastruktur zu. Bestehende Tests für Scan-Ketten können die komplexere Steuerlogik bei Rekonfigurierbaren Scan-Netzwerken nicht ausreichend testen. Deshalb ist es notwendig, neuartige Teststrategien zu entwickeln, welche speziell an die Merkmale von Rekonfigurierbaren Scan-Netzwerken angepasst sind.
  • Diplomarbeit Nr.3245: Adaptive Simulationsbasierte Diagnose von Verzögerungsfehlern in kombinaotrischen Schaltungen
    Eric Schneider
    15.09.2011 - 16.03.2012
    Abstract
    Strukturen mit Dimensionen von wenigen Nanometern, wie man sie in modernen Chips findet, können nur noch mit erheblichem Aufwand in komplexen Herstellungsprozessen produziert werden. Hierbei können, in Abhängigkeit von Prozess-Parametern und Design, Defekte auftreten, die das Zeitverhalten der Schaltung beeinflussen und sowohl rein zufälliger, als auch systematischer Natur sein können. Durch die stetig steigenden Taktfrequenzen häuft sich dabei die Gefahr, dass kleine Verzögerungsfehler auftreten, welche im Vergleich zu statischen Fehlern nur unter Echtzeit-Bedingungen sichtbar werden. Um die Chipausbeute bei der Herstellung zu erhöhen und Qualitätsanforderungen zu gewährleisten, ist Diagnose deshalb von essentieller Bedeutung. Defekte müssen lokalisiert und anfällige Stellen in fehlerhaften Schaltkreisen ausfindig gemacht werden. Dadurch können das Design und der Herstellungsprozess optimiert und die Kosten pro fehlerfreien Chip bei der Entwicklung gesenkt werden. Die genaue Diagnose der kleinen Verzögerungsfehler stellt jedoch eine große Herausforderung dar, da das Verhalten und die Simulation dieser Fehler sehr komplex sind, und diese nicht mehr effektiv mit einfacheren Fehlermodellen, wie dem Transitionsfehlermodell [WLRI87] abgedeckt werden können. Zudem erschweren Variationen innerhalb der Schaltkreise die Diagnose. Das Ziel dieser Arbeit ist die Entwicklung eines Verfahrens zur Diagnose von kleinsten Verzögerungsfehlern, welches Defektstellen effizient lokalisieren und die Defektgrößen der Fehler abschätzen kann. Dabei soll ein simulationsbasierter Ansatz mit einem Zeitsimulator verwendet werden, um die Fehler präzise auszuwerten und stabile Ergebnisse bei Präsenz von Variationen zu ermöglichen.
  • Master Thesis Nr.3304: Modeling of Design-for-test infrastructure in complex Systems-on-chips
    David Prasetyo Buntoro
    17.02.2012 - 18.08.2012
    Abstract
    Every integrated circuit contains a piece of design-for-test (DFT) infrastructure in order to guarantee the chip quality after manufacture. The DFT resources are employed only once in the fab and are usually not available during regular system operation.
    In order to assess the hardware integrity of a chip over its complete life-cycle, it is promising to reuse the DFT infrastructure as part of system-level test. In this thesis, the provided system, a Tricore processor from Infineon, must be partitioned and modified in order to enable the autonomous structural test of every component of the system in the field without expensive external tester.
  • Master Thesis Nr.3221: Implementing Density Functional Theory Methods on GPGPU Accelerators
    Bishwajit Mohan Gosswami
    01.05.2011 - 31.10.2011
    Abstract
    Density Functional Theory (DFT) is one of the most widely used quantum mechanical methods for calculations of the electronic structure of molecules and surfaces, which achieves an excellent balance of accuracy and computational cost. However, for large molecular systems with few hundred atoms, the computational costs are become very high. Therefore, there is a fast growing demand for much more efficient implementations to utilize DFT for macro molecules. General Purpose Graphics Processors (GPUs) are highly parallel, multi-threaded, many-core processors with tremendous computational capability, which out-paces CPUs in terms of floating-point performance. They are particularly focused for computation intensive and highly data-parallel computations. This thesis will introduce the scope of one grained parallelism with highly data-parallel GPU implementations of several algorithmic parts of DFT. Furthermore, experimental results and benchmarks will be presented
  • Bachelor Project Nr.2332: Evaluation of Backtracking Diagnosis Algorithms
    Maha Badreldein
    05.04.2011 - 31.08.2011
    Abstract
    With the growing size and complexity of modern circuits, more algorithms are being developed nowadays for efficient fault diagnosis. Backtracing based diagnosis algorithms are e ffect-cause approaches that start from the failing outputs of the circuit and try to diagnose fault locations by backtracing lines toward the circuit inputs. In this thesis, general functionality was extracted between backtracing based diagnosis algorithms and implemented as an extension to an existing diagnosis framework. Furthermore, a simple graphical user interface was developed for the extended framework. The extended framework aims at facilitating the implementation and evaluation of diff erent backtracing based diagnosis algorithms. In order to demonstrate its powerfulness, two modern backtracing based diagnosis algorithms were implemented on top of the extended framework. A number of diagnosis experiments on benchmark circuits was carried out in order to evaluate the two implemented algorithms. The experimental tools used and the results obtained are presented.
  • Master Thesis Nr.3161: Evaluation of Advanced Techniques for Structural FPGA Self-Test
    Mohamed Abdelfattah
    01.03.2011 - 31.08.2011
    Abstract
    This thesis presents a comprehensive test generation framework for FPGA logic elements and interconnects. It is based on and extends the current state-of-the-art. The purpose of FPGA testing in this work is to achieve reliable reconfiguration for a FPGA-based runtime reconfigurable system. A pre-configuration test is performed on a portion of the FPGA before it is reconfigured as part of the system to ensure that the FPGA fabric is fault-free. The implementation platform is the Xilinx Virtex-5 FPGA family. Existing literature in FPGA testing is evaluated and reviewed thoroughly. The various approaches are compared against one another qualitatively and the approach most suitable to the target platform is chosen. The array testing method is employed in testing the FPGA logic for its low hardware overhead and optimal test time. All tests are additionally pipelined to reduce test application time and use a high test clock frequency. A hybrid fault model including both structural and functional faults is assumed. An algorithm for the optimization of the number of required FPGA test configurations is developed and implemented in Java using a pseudo-random set-covering heuristic. Optimal solutions are obtained for Virtex-5 logic slices. The algorithm effort is parameterizable with the number of loop iterations each of which take approximately one second for a Virtex-5 sliceL circuit. A flexible test architecture for interconnects is developed. Arbitrary wire types can be tested in the same test configuration with no hardware overhead. Furthermore, a routing algorithm is integrated with the test template generation to select the wires under test and route them appropriately. Nine test configurations are required to achieve full test coverage for the FPGA logic. For interconnect testing, a local router-based on depth-first graph traversal is implemented in Java as the basis for creating systematic interconnect test templates. Pent wire testing is additionally implemented as a proof of concept. The test clock frequency for all tests exceeds 170 MHz and the hardware overhead is always lower than seven CLBs. All implemented tests are parameterizable such that they can be applied to any portion of the FPGA regardless of size or position.
  • Master Thesis Nr.3097: Development of an Error Detection and Recovery Technique for a SPARCV8 Processor in FPGA technology
    Andrew Boktor
    19.10.2010 - 19.04.2011
    Abstract
    Field-Programmable Gate Arrays (FPGAs) found widespread use in many areas of applications, including safety and mission-critical systems. More and more manufacturers are choosing to implement designs on FPGAs. However, SRAM-based FPGAs are proven to be much more prone to Single Event Upsets (SEUs) compared to traditional Application-Specfi c Integrated Circuit (ASIC) designs. Moreover, SEU affects FPGAs in more severe ways compared to ASIC. Techniques to provide fault-tolerance for SRAM-based FPGAs become essential to maintain their advantages over other technologies. This thesis presents a fault-tolerance technique for pipeline architectures in FPGA technology. It provides fault-tolerance against SEUs in the design and is able to detect faults in the FPGA confi guration. It also proposes an additional mechanism that detects all SEUs independent of their location. Pipeline operation can be resumed with known techniques of partial reconfi guration. Both designs occupy a much smaller area compared to known techniques such as TMR in combination with Scrubbing. They introduce no additional time penalty in case of fault-free operation. Fault injection and simulation were used to validate the design and calculate the fault coverage.