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1. System-Level Simulation Models of Multicore Operating Systems (Master Thesis)

To simulate a processor running some piece of software, traditionally an instruction set simulator (ISS) of that processor is used. In shared- memory multicore platforms, software is often multithreaded and is built on top of a threading library which abstracts the details of context switching and scheduling from the programmers. This adds to the complexity of the model and using an ISS to simulate such models can be very slow. A more efficient alternative to instruction set simulation is source-level timing annotation where timing information is annotated in the software source code and the software is executed on the simulation host. However, timing annotation alone can not capture the effects of the thread scheduling and context switch overheads. The objective of this thesis is development of a transaction level simulation model for a multicore threading library. Combination of this model with the source level annotated software can provide a fast simulation model with an acceptable level of accuracy. Prerequisites: Very good knowledge of C/C++, multithreaded programming and good knowledge of computer architecture basics. Exposure to SystemC, transaction level modeling, and a hardware description language (VHDL or Verilog) would be a plus, but is not a requirement.

For more information please see here or contact Bastian Haetzer .

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1. Transaction-Level Instruction Set Simulator of An ATMEL AVR Microcontroller Core (Master Thesis)

Modern design flows require the simulation of software running on a CPU in a larger system context. For this purpose, an instruction set simulator (ISS) specific to the ATMEL AVR processor architecture shall be developed. To interface with the rest of the system simulation model, the ISS shall have a transaction-level interface. To transform AVR assembler code (generated with a given cross compiler from, e.g., C/C++ sources) into a representation suitable for compiled instruction set simulation, a preprocessor has to be developed. As time permits, the implementation of an interface with an IDE / debugger (AVR Studio or GNU gdb) is desirable.

The thesis is performed in our Embedded Systems Lab in close cooperation with ATMEL, Heilbronn, as part of the research project ROBUST. Post-thesis job opportunities with ATMEL exist.

For more infomation please see here or contact Bastian Haetzer .