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Publikationen

2017

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2015

 

2014

 

2013

2012

 

2011

2010

2009

2008

2007

2006

2005 and earlier

  • Brand, H.J.; Rülke, S.; Radetzki, M.: IP Qualification for Efficient System Design. Proc. International Symposium on Quality Electronic Design (ISQED), 2004.

  • Schaaf, M.; Freßmann, A.; Maximini, R.; Bergmann, R.; Tartakovski, A.; Radetzki, M.: Intelligent IP Retrieval Driven by Application Requirements. Integration - The VLSI Journal, 37(4): 253-287, 2004.

  • Vörg, A.; Radetzki, M.; Rosenstiel, W.: Measurement of IP Qualification Costs and Benefits. Proc. Design Automation and Test in Europe (DATE), Paris, 2004.

  • Badelt, U.; Kühl, H.; Radetzki, M.: sciPROVE: C++ Based Verification Environment for IP and SoC Design. Forum on Design Languages (FDL), Frankfurt, 2003.

  • Lange, H.; Radetzki, M.: IP Configuration Management with Abstract Parameterizations. IP Based SoC Design Workshop, Grenoble, 2002.

  • Radetzki, M.: Qualität und Qualitätssicherung wiederverwendbarer Schaltungsbesch­reibungen. Informationstechnik und Technische Informatik (it+ti) 44 (2002) 2, pp. 99­-102.

  • Saucier, G.; Ghanmi, L.; Hamdoun, M.; Pfirsch, Th.; ten Have, M.; Radetzki, M.; Neu­mann, P.: IP Transfer: A Mapping Problem. IP Based SoC Design Workshop, Grenoble, 2002.

  • Saucier, G.; Ghanmi, L.; Skiba, K.; ten Have, M.; Radetzki, M.; Neumann, P.: IP Exchange Platform. Open ToolIP Workshop, MEDEA+ Design Automation Confer­ence, Stresa, 2002.

  • Nebel, W.; Oppenheimer, F.; Schumacher, G.; Kabous, L.; Radetzki, M.; Putzke-Röming, W.: Object-Oriented Specification and Design of Embedded Hard Real-Time Systems. In: Ashenden, P.; Mermet, J.; Seepold, R. (Eds.): System-on-Chip Methodologies & Design Languages. Kluwer Academic Publishers, 2001.

  • Seepold, R.; Martinez Madrid, N.; Vörg, A.; Rosenstiel, W.; Radetzki, M.: A Qualification Platform for Design Reuse. Proc. Int'l Symposium on Quality Electronic Design (ISQED), San Jose, 2002.

  • Radetzki, M.; Neumann, P.; Haase, J.; Martinez Madrid, N.; Seepold, R.; Vörg, A.: Automated Qualification Flow for Soft IP. Proc. MEDEA+ Conference on Application-Oriented SoC Design, Veldhoven, 2001.

  • Radetzki, M.: Synthesis of Digital Circuits from Object-Oriented Specifications. Dissertation, Universität Oldenburg, 2000.

  • Radetzki, M.; Nebel, W.: Digital Circuit Design with Objective VHDL. In Mermet, J. (Ed.): Electronic Chips & Systems Design Languages. Kluwer Academic Publishers, 2001

  • Nebel, W.; Oppenheimer, F.; Schumacher, G.; Kabous, L.; Radetzki, M.; Putzke-Röming, W.: Object-Oriented Specification and Design of Embedded Hard Real-Time Systems. Proc. 16th IFIP World Congress, Peking, 2000.

  • Radetzki, M.; Nebel, W.: Synthesizing Hardware from Object-Oriented Descriptions. Proc. Forum on Design Languages (FDL), Lyon, 1999.

  • Radetzki, M.: Overview of Objective VHDL Language Features. Proc. Forum on Design Languages (FDL), Lyon, 1999.

  • Radetzki, M.; Nebel, W.: Synthesis of Hardware Structures from Object-Oriented Mod­els. Proc. 8th Int'l Symposium on Integrated Circuits, Devices and Systems (ISIC), Singapur, 1999.

  • Radetzki, M.; Stammermann, A.; Putzke-Röming, W.; Nebel, W.: Data Type Analysis for Hardware Synthesis from Object-Oriented Models. Proc. Design, Automation and Test in Europe (DATE), Munich, 1999.

  • Ashenden, P.J.; Wilsey, P.A.; Nebel, W.; Radetzki, M.; Putzke-Röming, W.; Peterson, G.D.: SUAVE and Objective VHDL: Object-Oriented Extensions to VHDL. Proc. Forum on Design Languages (FDL), Lyon, 1999.

  • Ashenden, P.J.; Radetzki, M.: Comparison of SUAVE and Objective VHDL Language Features. Proc. Forum on Design Languages (FDL), Lyon, 1999.